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Diffstat (limited to 'planAhead_run_3/planAhead.log')
| -rw-r--r-- | planAhead_run_3/planAhead.log | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/planAhead_run_3/planAhead.log b/planAhead_run_3/planAhead.log new file mode 100644 index 0000000..6d93eb0 --- /dev/null +++ b/planAhead_run_3/planAhead.log @@ -0,0 +1,70 @@ +#----------------------------------------------------------- +# PlanAhead v14.7 (64-bit) +# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013 +# Start of session at: Tue Feb 21 21:46:05 2017 +# Process ID: 24048 +# Log file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_3/planAhead.log +# Journal file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_3/planAhead.jou +#----------------------------------------------------------- +INFO: [Common 17-78] Attempting to get a license: PlanAhead +INFO: [Common 17-290] Got license for PlanAhead +INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml +Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml] +Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml] +start_gui +source /home/yannherklotz/Github/FPGA-led-lights/pa.fromNetlist.tcl +# create_project -name FPGA-led-lights -dir "/home/yannherklotz/Github/FPGA-led-lights/planAhead_run_3" -part xc6slx9tqg144-2 +# set_property design_mode GateLvl [get_property srcset [current_run -impl]] +# set_property edif_top_file "/home/yannherklotz/Github/FPGA-led-lights/led.ngc" [ get_property srcset [ current_run ] ] +# add_files -norecurse { {/home/yannherklotz/Github/FPGA-led-lights} } +# set_param project.pinAheadLayout yes +# set_property target_constrs_file "/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf" [current_fileset -constrset] +Adding file '/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf' to fileset 'constrs_1' +# add_files [list {/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf}] -fileset [get_property constrset [current_run]] +# link_design +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +Design is defaulting to project part: xc6slx9tqg144-2 +Release 14.7 - ngc2edif P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Release 14.7 - ngc2edif P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +Reading design led.ngc ... +WARNING:NetListWriters:298 - No output is written to led.xncf, ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file led.edif ... +ngc2edif: Total memory usage is 103532 kilobytes + +Parsing EDIF File [./planAhead_run_3/FPGA-led-lights.data/cache/led_ngc_cb841106.edif] +Finished Parsing EDIF File [./planAhead_run_3/FPGA-led-lights.data/cache/led_ngc_cb841106.edif] +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockRegion.xml +Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockBuffers.xml +Loading package pin functions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/PinFunctions.xml... +Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/tqg144/Package.xml +Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/IOStandards.xml +Loading device configuration modes from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/ConfigModes.xml +Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/drc.xml +Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf] +Finished Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf] +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1 instances were transformed. + BUFGP => BUFGP (IBUF, BUFG): 1 instances + +Phase 0 | Netlist Checksum: 23693229 +link_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:07 . Memory (MB): peak = 2838.551 ; gain = 157.191 +exit +ERROR: [#UNDEF] *** Exception: ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup() +HTclEvent: SIGNAL_MODIFY Classes: ui.views.aR +HTclEvent: DEBUG_PORT_CONFIG_CHANGE Classes: ui.views.aR +HTclEvent: DEBUG_CORE_CONFIG_CHANGE Classes: ui.views.aR +HTclEvent: SIGNAL_BUS_MODIFY Classes: ui.views.aR + (See /home/yannherklotz/Github/FPGA-led-lights/planAhead_pid24048.debug) +ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors. +INFO: [Common 17-206] Exiting PlanAhead at Tue Feb 21 21:46:54 2017... +INFO: [Common 17-83] Releasing license: PlanAhead |