diff options
Diffstat (limited to 'webtalk_pn.xml')
| -rw-r--r-- | webtalk_pn.xml | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/webtalk_pn.xml b/webtalk_pn.xml index e745db1..b5ece96 100644 --- a/webtalk_pn.xml +++ b/webtalk_pn.xml @@ -3,14 +3,15 @@ <!--The data in this file is primarily intended for consumption by Xilinx tools. The structure and the elements are likely to change over the next few releases. This means code written to parse this file will need to be revisited each subsequent release.--> -<application name="pn" timeStamp="Sun Feb 19 23:15:29 2017"> +<application name="pn" timeStamp="Tue Feb 21 22:16:54 2017"> <section name="Project Information" visible="false"> <property name="ProjectID" value="8C4A34387ED46BFEECE9D369B6F8AAAE" type="project"/> -<property name="ProjectIteration" value="0" type="project"/> +<property name="ProjectIteration" value="19" type="project"/> <property name="ProjectFile" value="/home/yannherklotz/Github/FPGA-led-lights/FPGA-led-lights.xise" type="project"/> <property name="ProjectCreationTimestamp" value="2017-02-19T23:09:37" type="project"/> </section> <section name="Project Statistics" visible="true"> +<property name="PROPEXT_xilxSynthMaxFanout_virtex2" value="100000" type="process"/> <property name="PROP_Enable_Message_Filtering" value="false" type="design"/> <property name="PROP_FitterReportFormat" value="HTML" type="process"/> <property name="PROP_LastAppliedGoal" value="Balanced" type="design"/> @@ -25,15 +26,18 @@ This means code written to parse this file will need to be revisited each subseq <property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/> <property name="PROP_intProjectCreationTimestamp" value="2017-02-19T23:09:37" type="design"/> <property name="PROP_intWbtProjectID" value="8C4A34387ED46BFEECE9D369B6F8AAAE" type="design"/> +<property name="PROP_intWbtProjectIteration" value="19" type="process"/> <property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> <property name="PROP_intWorkingDirUsed" value="No" type="design"/> +<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/> +<property name="PROP_xilxNgdbld_AUL" value="true" type="process"/> <property name="PROP_AutoTop" value="true" type="design"/> -<property name="PROP_DevFamily" value="Spartan3E" type="design"/> -<property name="PROP_DevDevice" value="xc3s250e" type="design"/> -<property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/> -<property name="PROP_DevPackage" value="vq100" type="design"/> +<property name="PROP_DevFamily" value="Spartan6" type="design"/> +<property name="PROP_DevDevice" value="xc6slx9" type="design"/> +<property name="PROP_DevFamilyPMName" value="spartan6" type="design"/> +<property name="PROP_DevPackage" value="tqg144" type="design"/> <property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/> -<property name="PROP_DevSpeed" value="-4" type="design"/> +<property name="PROP_DevSpeed" value="-2" type="design"/> <property name="PROP_PreferredLanguage" value="Verilog" type="design"/> <property name="FILE_UCF" value="1" type="source"/> <property name="FILE_VERILOG" value="1" type="source"/> |