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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/yannherklotz/Github/FPGA-led-lights/led.v" into library work</arg>
</msg>
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