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****** PlanAhead v14.7 (64-bit)
**** Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
INFO: [Common 17-78] Attempting to get a license: PlanAhead
INFO: [Common 17-290] Got license for PlanAhead
INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
start_gui
source /home/yannherklotz/Github/FPGA-led-lights/pa.fromNcd.tcl
# create_project -name FPGA-led-lights -dir "/home/yannherklotz/Github/FPGA-led-lights/planAhead_run_4" -part xc6slx9tqg144-2
# set srcset [get_property srcset [current_run -impl]]
# set_property design_mode GateLvl $srcset
# set_property edif_top_file "/home/yannherklotz/Github/FPGA-led-lights/led.ngc" [ get_property srcset [ current_run ] ]
# add_files -norecurse { {/home/yannherklotz/Github/FPGA-led-lights} }
# set_property target_constrs_file "/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf" [current_fileset -constrset]
Adding file '/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf' to fileset 'constrs_1'
# add_files [list {/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf}] -fileset [get_property constrset [current_run]]
# link_design
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
Design is defaulting to project part: xc6slx9tqg144-2
Release 14.7 - ngc2edif P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Release 14.7 - ngc2edif P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading design led.ngc ...
WARNING:NetListWriters:298 - No output is written to led.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file led.edif ...
ngc2edif: Total memory usage is 103540 kilobytes
Parsing EDIF File [./planAhead_run_4/FPGA-led-lights.data/cache/led_ngc_cb841106.edif]
Finished Parsing EDIF File [./planAhead_run_4/FPGA-led-lights.data/cache/led_ngc_cb841106.edif]
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockRegion.xml
Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockBuffers.xml
Loading package pin functions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/PinFunctions.xml...
Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/tqg144/Package.xml
Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/IOStandards.xml
Loading device configuration modes from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/ConfigModes.xml
Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/drc.xml
Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
Finished Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 1 instances were transformed.
BUFGP => BUFGP (IBUF, BUFG): 1 instances
Phase 0 | Netlist Checksum: 23693229
link_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 2864.305 ; gain = 189.508
# read_xdl -file "/home/yannherklotz/Github/FPGA-led-lights/led.ncd"
Release 14.7 - xdl P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
WARNING:XDL:213 - The resulting xdl output will not have LUT equation strings or RAM INIT strings.
Loading device for application Rf_Device from file '6slx9.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
"led" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2
Successfully converted design '/home/yannherklotz/Github/FPGA-led-lights/led.ncd' to '/home/yannherklotz/Github/FPGA-led-lights/led.xdl'.
INFO: [Designutils 20-669] Parsing Placement File : /home/yannherklotz/Github/FPGA-led-lights/led.ncd
INFO: [Designutils 20-658] Finished Parsing Placement File : /home/yannherklotz/Github/FPGA-led-lights/led.ncd
INFO: [Designutils 20-671] Placed 87 instances
read_xdl: Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 2864.305 ; gain = 0.000
# if {[catch {read_twx -name results_1 -file "/home/yannherklotz/Github/FPGA-led-lights/led.twx"} eInfo]} {
# puts "WARNING: there was a problem importing \"/home/yannherklotz/Github/FPGA-led-lights/led.twx\": $eInfo"
# }
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add wave clock enable
invalid command name "add"
ambiguous command name "add": add_cells_to_pblock add_files
create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}]
WARNING: [PlanAhead 12-584] No ports matched 'CLOCK_50'.
invalid command name "create_clock"
add
invalid command name "add"
ambiguous command name "add": add_cells_to_pblock add_files
run
invalid command name "run"
exit
ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
INFO: [Common 17-206] Exiting PlanAhead at Tue Feb 21 21:53:15 2017...
INFO: [Common 17-83] Releasing license: PlanAhead
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