16 files changed, 781 insertions, 0 deletions
diff --git a/mylib/LFSR.v b/mylib/LFSR.v
new file mode 100755
index 0000000..89ec82a
--- /dev/null
+++ b/mylib/LFSR.v
@@ -0,0 +1,11 @@
+module LFSR(CLK, COUNT);
+	input CLK;
+	output[7:1] COUNT;
+	reg[7:1] COUNT;
+	initial COUNT = 7'd1;
+		
+	always @ (posedge CLK)
+		COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};
+		
+endmodule
+	
+\ No newline at end of file
diff --git a/mylib/ROM.v b/mylib/ROM.v
new file mode 100755
index 0000000..296e57c
--- /dev/null
+++ b/mylib/ROM.v
@@ -0,0 +1,160 @@
+// megafunction wizard: %ROM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: ROM.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Altera and sold by Altera or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module ROM (
+	address,
+	clock,
+	q);
+
+	input	[9:0]  address;
+	input	  clock;
+	output	[9:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [9:0] sub_wire0;
+	wire [9:0] q = sub_wire0[9:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address),
+				.clock0 (clock),
+				.q_a (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.address_b (1'b1),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_a ({10{1'b1}}),
+				.data_b (1'b1),
+				.eccstatus (),
+				.q_b (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_a (1'b0),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_a = "NONE",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.init_file = "./rom_data/rom_data.mif",
+		altsyncram_component.intended_device_family = "Cyclone V",
+		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 1024,
+		altsyncram_component.operation_mode = "ROM",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "CLOCK0",
+		altsyncram_component.widthad_a = 10,
+		altsyncram_component.width_a = 10,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "./rom_data/rom_data.mif"
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
+// Retrieval info: PRIVATE: WidthData NUMERIC "10"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "./rom_data/rom_data.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]"
+// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 10 0 @q_a 0 0 10 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/mylib/add3_ge5.v b/mylib/add3_ge5.v
new file mode 100755
index 0000000..65a561d
--- /dev/null
+++ b/mylib/add3_ge5.v
@@ -0,0 +1,25 @@
+module add3_ge5(w,a);
+	output [3:0] a;
+	input [3:0] w;
+	
+	reg [3:0] a;
+	
+	always @ (w)
+		case(w)
+			4'b0000: a <= 4'b0000;
+			4'b0001: a <= 4'b0001;
+			4'b0010: a <= 4'b0010;
+			4'b0011: a <= 4'b0011;
+			4'b0100: a <= 4'b0100;
+			4'b0101: a <= 4'b1000;
+			4'b0110: a <= 4'b1001;
+			4'b0111: a <= 4'b1010;
+			4'b1000: a <= 4'b1011;
+			4'b1001: a <= 4'b1100;
+			4'b1010: a <= 4'b1101;
+			4'b1011: a <= 4'b1110;
+			4'b1100: a <= 4'b1111;
+			
+			default: a <= 4'b0000;
+		endcase
+endmodule
diff --git a/mylib/bin2bcd_16.v b/mylib/bin2bcd_16.v
new file mode 100755
index 0000000..fdfb655
--- /dev/null
+++ b/mylib/bin2bcd_16.v
@@ -0,0 +1,97 @@
+//------------------------------
+// Module name: bin2bcd_16
+// Function: Converts a 16-bit binary number to 5 digits BCD
+//            .... it uses a shift-and-add3 algorithm
+// Creator:  Peter Cheung
+// Version:  1.0
+// Date:     18 Sept 2016
+//------------------------------
+//   For more explanation of how this work, see 
+//     ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment
+
+module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
+
+	input [15:0]	B;		// binary input number
+	output [3:0]	BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;   // BCD digit LSD to MSD
+	
+	wire [3:0]	w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;
+	wire [3:0]	w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25;
+	wire [3:0]	w26,w27,w28,w29;
+	wire [3:0]	a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13;
+	wire [3:0]	a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25;
+	wire [3:0]	a26,a27,a28,a29;
+
+	// Instantiate a tree of add3-if-greater than or equal to 5 cells
+	//  ... input is w_n, and output is a_n
+	add3_ge5 A1 (w1,a1);
+	add3_ge5 A2 (w2,a2);
+	add3_ge5 A3 (w3,a3);
+	add3_ge5 A4 (w4,a4);
+	add3_ge5 A5 (w5,a5);
+	add3_ge5 A6 (w6,a6);
+	add3_ge5 A7 (w7,a7);
+	add3_ge5 A8 (w8,a8);
+	add3_ge5 A9 (w9,a9);
+	add3_ge5 A10 (w10,a10);
+	add3_ge5 A11 (w11,a11);
+	add3_ge5 A12 (w12,a12);
+	add3_ge5 A13 (w13,a13);
+	add3_ge5 A14 (w14,a14);
+	add3_ge5 A15 (w15,a15);
+	add3_ge5 A16 (w16,a16);
+	add3_ge5 A17 (w17,a17);
+	add3_ge5 A18 (w18,a18);
+	add3_ge5 A19 (w19,a19);
+	add3_ge5 A20 (w20,a20);
+	add3_ge5 A21 (w21,a21);
+	add3_ge5 A22 (w22,a22);
+	add3_ge5 A23 (w23,a23);
+	add3_ge5 A24 (w24,a24);
+	add3_ge5 A25 (w25,a25);
+	add3_ge5 A26 (w26,a26);
+	add3_ge5 A27 (w27,a27);
+	add3_ge5 A28 (w28,a28);
+	add3_ge5 A29 (w29,a29);
+		
+	// wire the tree of add3 modules together
+	assign  w1 = {B[14:11]};		// wn is the input port to module An
+	assign  w2 = {a1[2:0], B[10]};
+	assign  w3 = {1'b0, B[15], a1[3], a2[3]};
+	assign  w4 = {a2[2:0], B[9]};
+	assign  w5 = {a3[2:0], a4[3]};
+	assign  w6 = {a4[2:0], B[8]};
+	assign  w7 = {a5[2:0], a6[3]};
+	assign  w8 = {a6[2:0], B[7]};
+	assign  w9 = {1'b0, a3[3], a5[3], a7[3]};
+	assign  w10 = {a7[2:0], a8[3]};
+	assign  w11 = {a8[2:0], B[6]};
+	assign  w12 = {a9[2:0], a10[3]};
+	assign  w13 = {a10[2:0], a11[3]};
+	assign  w14 = {a11[2:0], B[5]};
+	assign  w15 = {a12[2:0], a13[3]};
+	assign  w16 = {a13[2:0], a14[3]};
+	assign  w17 = {a14[2:0], B[4]};
+	assign  w18 = {1'b0, a9[3], a12[3], a15[3]};
+	assign  w19 = {a15[2:0], a16[3]};
+	assign  w20 = {a16[2:0], a17[3]};
+	assign  w21 = {a17[2:0], B[3]};
+	assign  w22 = {a18[2:0], a19[3]};
+	assign  w23 = {a19[2:0], a20[3]};
+	assign  w24 = {a20[2:0], a21[3]};
+	assign  w25 = {a21[2:0], B[2]};
+	assign  w26 = {a22[2:0], a23[3]};
+	assign  w27 = {a23[2:0], a24[3]};
+	assign  w28 = {a24[2:0], a25[3]};
+	assign  w29 = {a25[2:0], B[1]};
+	
+	// connect up to four BCD digit outputs	
+	assign BCD_0 = {a29[2:0],B[0]};
+	assign BCD_1 = {a28[2:0],a29[3]};
+	assign BCD_2 = {a27[2:0],a28[3]};
+	assign BCD_3 = {a26[2:0],a27[3]};
+	assign BCD_4 = {1'b0, a18[3], a22[3], a26[3]};	
+endmodule
+
+	
+	
+
diff --git a/mylib/counter_10.v b/mylib/counter_10.v
new file mode 100755
index 0000000..72c96fa
--- /dev/null
+++ b/mylib/counter_10.v
@@ -0,0 +1,18 @@
+`timescale 1ns / 100ps
+
+module counter_10(clock,enable,count);
+
+	parameter BIT_SZ = 10;
+	input clock;
+	input enable;
+	output [BIT_SZ-1:0] count;
+	
+	reg [BIT_SZ-1:0] count;
+	
+	initial count = 0;
+	
+	always @ (posedge clock)
+		if(enable == 1'b1)
+			count <= count + 1'b1;
+			
+endmodule
+\ No newline at end of file
diff --git a/mylib/counter_16.v b/mylib/counter_16.v
new file mode 100755
index 0000000..c0ec549
--- /dev/null
+++ b/mylib/counter_16.v
@@ -0,0 +1,21 @@
+`timescale 1ns / 100ps
+
+module counter_16(clock,enable,reset,count);
+
+	parameter BIT_SZ = 16;
+	input clock, enable, reset;
+	output [BIT_SZ-1:0] count;
+	
+	reg [BIT_SZ-1:0] count;
+	
+	initial count = 0;
+	
+	always @ (posedge clock)
+		begin
+			if(enable == 1'b1)
+				count <= count + 1'b1;
+			if(reset == 1'b1)
+				count <= 16'b0;
+		end
+			
+endmodule
+\ No newline at end of file
diff --git a/mylib/counter_8.v b/mylib/counter_8.v
new file mode 100755
index 0000000..b45154a
--- /dev/null
+++ b/mylib/counter_8.v
@@ -0,0 +1,22 @@
+`timescale 1ns / 100ps
+
+module counter_8(
+	clock,
+	enable,
+	count
+	);
+
+	parameter BIT_SZ = 8;
+	input clock;
+	input enable;
+	output [BIT_SZ-1:0] count;
+	
+	reg [BIT_SZ-1:0] count;
+	
+	initial count = 0;
+	
+	always @ (posedge clock)
+		if(enable == 1'b1)
+			count <= count + 1'b1;
+			
+endmodule
+\ No newline at end of file
diff --git a/mylib/delay.v b/mylib/delay.v
new file mode 100755
index 0000000..a983085
--- /dev/null
+++ b/mylib/delay.v
@@ -0,0 +1,60 @@
+module delay(clk, N, trigger, time_out);
+
+	parameter BIT_SZ = 14;
+
+	input clk, trigger;
+	input [BIT_SZ-1:0] N;
+	output time_out;
+
+	reg[BIT_SZ-1:0] count;
+	reg time_out;
+
+	reg [1:0] state;
+
+	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;
+
+	initial begin
+		state = IDLE;
+	end
+	
+	always @ (posedge clk)
+		case(state)
+			IDLE: if(trigger == 1'b1)
+				begin
+					count <= N*128;
+					state <= COUNTING;
+				end
+			COUNTING: 
+				begin
+					if(count == 1'b0)
+						begin
+							state <= TIME_OUT;
+						end
+					else 
+						count <= count - 1'b1;
+				end
+			TIME_OUT: 
+				begin
+					if(trigger == 1'b0)
+						state <= IDLE;
+					else
+						state <= WAIT_LOW;
+				end
+			WAIT_LOW: 
+				if(trigger == 1'b0)
+					state <= IDLE;
+			default: ;
+		endcase
+		
+	always @ (*)
+		case(state)
+			IDLE:
+					time_out = 1'b0;
+			COUNTING: 
+					time_out = 1'b0;
+			TIME_OUT: time_out = 1'b1;
+			WAIT_LOW: time_out = 1'b0;
+			default: ;
+		endcase
+
+endmodule
+\ No newline at end of file
diff --git a/mylib/ex8.v b/mylib/ex8.v
new file mode 100755
index 0000000..aaa8488
--- /dev/null
+++ b/mylib/ex8.v
@@ -0,0 +1,23 @@
+module ex8(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);
+	
+	input CLOCK_50;
+	input [3:0] KEY;
+	output [9:0] LEDR;
+	output [6:0] HEX0, HEX1, HEX2;
+	
+	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;
+	wire [6:0] N;
+	wire [6:0] bcd_to_hex;
+	wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;
+	
+	tick_50000 TICK0(CLOCK_50, tick_ms);
+	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);
+	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);
+	LFSR LFSR0(tick_ms, en_lfsr, N);
+	delay DEL0(tick_ms, N, start_delay, time_out);
+	bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
+	hex_to_7seg SEG0(HEX0, BCD_0);
+	hex_to_7seg SEG1(HEX1, BCD_1);
+	hex_to_7seg SEG2(HEX2, BCD_2);
+	
+endmodule
+\ No newline at end of file
diff --git a/mylib/formula_fsm.v b/mylib/formula_fsm.v
new file mode 100755
index 0000000..90daa0c
--- /dev/null
+++ b/mylib/formula_fsm.v
@@ -0,0 +1,66 @@
+module formula_fsm(clk, tick, trigger, time_out, en_lfsr, start_delay, ledr);
+
+input clk, tick, trigger, time_out;
+output en_lfsr, start_delay;
+output [9:0] ledr;
+
+reg [1:0] state;
+reg led_on, en_lfsr, start_delay;
+reg [9:0] ledr;
+
+parameter WAIT_TRIGGER = 2'd0, LIGHT_UP_LEDS = 2'd1, WAIT_FOR_TIMEOUT = 2'd2;
+
+initial 
+	begin
+		state = WAIT_TRIGGER;
+		en_lfsr = 1'b0;
+		start_delay = 1'b0;
+	end
+
+always @ (posedge clk)
+	case(state)
+		WAIT_TRIGGER: 
+			begin
+				if(trigger == 1'b1)
+					state <= LIGHT_UP_LEDS;
+			end
+		LIGHT_UP_LEDS:
+				if(ledr == 10'h3ff)
+					state <= WAIT_FOR_TIMEOUT;
+		WAIT_FOR_TIMEOUT:
+				if(time_out == 1'b1)
+					 state <= WAIT_TRIGGER;
+		default: ;
+	endcase
+
+always @ (posedge tick)
+	case(state)
+		WAIT_TRIGGER:
+			ledr = 10'b0;
+		LIGHT_UP_LEDS:
+			ledr <= {ledr[8:0], 1'b1};
+		default:
+			ledr <= 10'h3ff;
+	endcase
+	
+always @ (*)
+	case(state)
+		WAIT_TRIGGER:
+			begin
+
+				en_lfsr = 1'b0;
+				start_delay = 1'b0;
+			end
+		LIGHT_UP_LEDS:
+			begin
+				en_lfsr = 1'b1;
+			end
+		WAIT_FOR_TIMEOUT:
+			begin
+				start_delay = 1'b1;
+				en_lfsr = 1'b0;
+			end
+		default: ;
+	endcase
+
+endmodule
+\ No newline at end of file
diff --git a/mylib/hex_to_7seg.v b/mylib/hex_to_7seg.v
new file mode 100755
index 0000000..82aa9a5
--- /dev/null
+++ b/mylib/hex_to_7seg.v
@@ -0,0 +1,27 @@
+module hex_to_7seg (out, in);
+
+	output [6:0] out;
+	input [3:0] in;
+	
+	reg [6:0] out;
+	
+	always @ (*)
+		case(in)
+			4'h0: out = 7'b1000000;
+			4'h1: out = 7'b1111001;
+			4'h2: out = 7'b0100100;
+			4'h3: out = 7'b0110000;
+			4'h4: out = 7'b0011001;
+			4'h5: out = 7'b0010010;
+			4'h6: out = 7'b0000010;
+			4'h7: out = 7'b1111000;
+			4'h8: out = 7'b0000000;
+			4'h9: out = 7'b0011000;
+			4'ha: out = 7'b0001000;
+			4'hb: out = 7'b0000011;
+			4'hc: out = 7'b1000110;
+			4'hd: out = 7'b0100001;
+			4'he: out = 7'b0000110;
+			4'hf: out = 7'b0001110;
+		endcase
+endmodule
diff --git a/mylib/pwm.v b/mylib/pwm.v
new file mode 100755
index 0000000..6a6e10c
--- /dev/null
+++ b/mylib/pwm.v
@@ -0,0 +1,25 @@
+module pwm(clk, data_in, load, pwm_out);
+
+	input clk;
+	input [9:0] data_in;
+	input load;
+	output pwm_out;
+	
+	reg[9:0] d;
+	reg [9:0] count;
+	reg pwm_out;
+	
+	always @ (posedge clk)
+		if(load == 1'b1) d <= data_in;
+		
+	initial count = 10'b0;
+	
+	always @ (posedge clk) begin
+		count <= count + 1'b1;
+		if(count > d)
+			pwm_out <= 1'b0;
+		else
+			pwm_out <= 1'b1;
+		end
+		
+endmodule
+\ No newline at end of file
diff --git a/mylib/spi2dac.v b/mylib/spi2dac.v
new file mode 100755
index 0000000..586a231
--- /dev/null
+++ b/mylib/spi2dac.v
@@ -0,0 +1,128 @@
+//------------------------------
+// Module name: spi2dac
+// Function: SPI interface for MPC4911 DAC
+// Creator:  Peter Cheung
+// Version:  2.0
+// Date:     8 Nov 2016
+//------------------------------
+
+module spi2dac (sysclk, data_in, load, dac_sdi, dac_cs, dac_sck, dac_ld);
+
+	input	sysclk;			// 50MHz system clock of DE1
+	input	[9:0]	data_in;	// input data to DAC
+	input	load;				// Pulse to load data to dac
+	output dac_sdi;		// SPI serial data out
+	output dac_cs;			// chip select - low when sending data to dac
+	output dac_sck;		// SPI clock, 16 cycles at half sysclk freq
+	output dac_ld;
+
+//-------------Input Ports-----------------------------
+// All the input ports should be wires
+	wire			sysclk, load;
+	wire [9:0]	data_in;
+	
+//-------------Output Ports-----------------------------
+// Output port can be a storage element (reg) or a wire
+	reg			dac_cs, dac_ld;
+	wire			dac_sck, dac_sdi;
+	
+	parameter	BUF=1'b1;		// 0:no buffer, 1:Vref buffered
+	parameter	GA_N=1'b1;		// 0:gain = 2x, 1:gain = 1x
+	parameter	SHDN_N=1'b1;	// 0:power down, 1:dac active
+	
+	wire [3:0] cmd = {1'b0,BUF,GA_N,SHDN_N};  // wire to VDD or GND
+	
+	// --- internal 1MHz symmetical clock generator -----
+	reg			clk_1MHz;	// 1Mhz clock derived from 50MHz
+	reg [4:0]	ctr;			// internal counter
+	
+	parameter	TC = 5'd24;  // Terminal count - change this for diff clk freq
+	initial begin
+		clk_1MHz = 0;			// don't need to reset - don't care if it is 1 or 0 to start
+		ctr = 5'b0;				//  ... Initialise when FPGA is configured
+	end
+		
+	always @ (posedge sysclk)    
+	  if (ctr==0) begin
+		  ctr <= TC;
+		  clk_1MHz <= ~clk_1MHz; // toggle the output clock for squarewave
+		end
+	  else
+		  ctr <= ctr - 1'b1;
+	// ---- end internal 1MHz symmetical clock generator ----------
+
+	// ---- FSM to detect rising edge of load and falling edge of dac_cs
+	// .... sr_state set on posedge of load
+	// .... sr_state reset when dac_cs goes high at the end of DAC output cycle
+	reg [1:0] 	sr_state;
+	parameter	IDLE  = 2'b00,WAIT_CSB_FALL = 2'b01, WAIT_CSB_HIGH = 2'b10;
+	reg			dac_start;		 // set if a DAC write is detected
+	
+	initial begin
+		sr_state = IDLE;
+		dac_start = 1'b0;	// set while sending data to DAC
+		end
+	
+	always @ (posedge sysclk)  // state transition
+		case (sr_state)
+			IDLE:	if (load==1'b1) sr_state <= WAIT_CSB_FALL;
+			WAIT_CSB_FALL: if (dac_cs==1'b0) sr_state <= WAIT_CSB_HIGH;
+			WAIT_CSB_HIGH: if (dac_cs==1'b1) sr_state <= IDLE;
+			default: sr_state <= IDLE;
+		endcase
+	
+	always @ (*)
+		case (sr_state)
+			IDLE: dac_start = 1'b0;
+			WAIT_CSB_FALL: dac_start = 1'b1;
+			WAIT_CSB_HIGH: dac_start = 1'b0;
+			default: dac_start = 1'b0;
+		endcase
+		
+	//------- End circuit to detect start and end of conversion	state machine
+
+	//------- spi controller FSM
+	// .... with 17 states (idle, and S1-S16 
+	// .... for the 16 cycles each sending 1-bit to dac)
+	reg [4:0] 	state;
+	
+	initial	begin	
+		state = 5'b0; dac_ld = 1'b0; dac_cs = 1'b1; 
+		end
+		
+	always @(posedge clk_1MHz)  // FSM state transition
+		case (state)
+			5'd0:	if (dac_start == 1'b1)    // waiting to start
+						state <= state + 1'b1; 
+					else 
+						state <= 5'b0; 
+			5'd17: 	state <= 5'd0;  // go back to idle state
+			default: state <= state + 1'b1;	// default go to next state
+		endcase
+	
+	always @ (*)	begin			// FSM output
+		dac_cs = 1'b0;  dac_ld = 1'b1;
+		case (state)
+			5'd0: 	dac_cs = 1'b1;
+			5'd17: 	begin dac_cs = 1'b1; dac_ld = 1'b0; end
+			default: begin dac_cs = 1'b0;	dac_ld = 1'b1;	end
+			endcase
+		end //always
+	// --------- END of spi controller FSM
+	
+	// shift register for output data
+	reg [15:0] shift_reg;
+	initial	begin	
+		shift_reg = 16'b0; 
+		end
+
+	always @(posedge clk_1MHz)
+		if((dac_start==1'b1)&&(dac_cs==1'b1))		// parallel load data to shift reg
+			shift_reg <= {cmd,data_in,2'b00};
+		else 													// .. else start shifting
+			shift_reg <= {shift_reg[14:0],1'b0};
+	
+	// Assign outputs to drive SPI interface to DAC
+			assign dac_sck = !clk_1MHz&!dac_cs;
+			assign dac_sdi = shift_reg[15];
+endmodule
+\ No newline at end of file
diff --git a/mylib/tick_2500.v b/mylib/tick_2500.v
new file mode 100755
index 0000000..e75a131
--- /dev/null
+++ b/mylib/tick_2500.v
@@ -0,0 +1,35 @@
+module tick_2500(CLOCK_IN, en, CLK_OUT);
+
+	parameter NBIT = 12;
+	
+	input CLOCK_IN, en;
+	output CLK_OUT;
+	
+	reg [NBIT-1:0] count;
+	
+	reg CLK_OUT;
+	
+	initial 
+		begin
+			count = 12'd2499;
+			CLK_OUT = 1'b0;
+		end
+	
+	always @ (posedge CLOCK_IN)
+		if(en == 1'b1)
+			begin
+				if(count == 1'b0)
+					begin
+						CLK_OUT <= 1'b1;
+						count <= 12'd2499;
+					end
+				else
+					begin
+						count <= count - 1'b1;
+						CLK_OUT <= 1'b0;
+					end
+			end
+		else 
+			CLK_OUT <= 1'b0;
+
+endmodule
+\ No newline at end of file
diff --git a/mylib/tick_5000.v b/mylib/tick_5000.v
new file mode 100755
index 0000000..a048386
--- /dev/null
+++ b/mylib/tick_5000.v
@@ -0,0 +1,32 @@
+module tick_5000(CLOCK_IN, CLK_OUT);
+
+	parameter NBIT = 16;
+	
+	input CLOCK_IN;
+	output CLK_OUT;
+	
+	reg [NBIT-1:0] count;
+	
+	reg CLK_OUT;
+	
+	initial 
+		begin
+			count = 16'd4999;
+			CLK_OUT = 1'b0;
+		end
+	
+	always @ (posedge CLOCK_IN)
+		begin
+			if(count == 16'b0)
+				begin
+					CLK_OUT <= 1'b1;
+					count <= 16'd4999;
+				end
+			else
+				begin
+					count <= count - 1'b1;
+					CLK_OUT <= 1'b0;
+				end
+		end
+
+endmodule
+\ No newline at end of file
diff --git a/mylib/tick_50000.v b/mylib/tick_50000.v
new file mode 100755
index 0000000..45c4166
--- /dev/null
+++ b/mylib/tick_50000.v
@@ -0,0 +1,31 @@
+module tick_50000(CLOCK_IN, CLK_OUT);
+
+	parameter NBIT = 16;
+	
+	input CLOCK_IN;
+	output CLK_OUT;
+	
+	reg [NBIT-1:0] count;
+	
+	reg CLK_OUT;
+	
+	initial 
+		begin
+			count = 16'd24999;
+			CLK_OUT = 1'b0;
+		end
+	
+	always @ (posedge CLOCK_IN)
+		begin
+			if(count == 16'b0)
+				begin
+					CLK_OUT <= ~CLK_OUT;
+					count <= 16'd24999;
+				end
+			else
+				begin
+					count <= count - 1'b1;
+				end
+		end
+
+endmodule
+\ No newline at end of file