1 files changed, 22 insertions, 0 deletions
diff --git a/part_2/ex5/verilog files/counter_8.v b/part_2/ex5/verilog files/counter_8.v
new file mode 100755
index 0000000..b45154a
--- /dev/null
+++ b/part_2/ex5/verilog files/counter_8.v
@@ -0,0 +1,22 @@
+`timescale 1ns / 100ps
+
+module counter_8(
+	clock,
+	enable,
+	count
+	);
+
+	parameter BIT_SZ = 8;
+	input clock;
+	input enable;
+	output [BIT_SZ-1:0] count;
+	
+	reg [BIT_SZ-1:0] count;
+	
+	initial count = 0;
+	
+	always @ (posedge clock)
+		if(enable == 1'b1)
+			count <= count + 1'b1;
+			
+endmodule
+\ No newline at end of file