1 files changed, 28 insertions, 0 deletions
diff --git a/part_3/ex13/db/ex10.map.qmsg b/part_3/ex13/db/ex10.map.qmsg
new file mode 100755
index 0000000..4005865
--- /dev/null
+++ b/part_3/ex13/db/ex10.map.qmsg
@@ -0,0 +1,28 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480420463362 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480420463364 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 29 11:54:23 2016 " "Processing started: Tue Nov 29 11:54:23 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480420463364 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420463364 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex10 -c ex10 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex10 -c ex10" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420463365 ""}
+{ "Critical Warning" "WHDB_IGNORED_ASGN_INVALID_NODE_NAME" "IO_STANDARD LEDR\[3\]#============================================================ " "Ignored assignment IO_STANDARD which contains an invalid node name \"LEDR\[3\]#============================================================\"" {  } {  } 1 136021 "Ignored assignment %1!s! which contains an invalid node name \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420463646 ""}
+{ "Critical Warning" "WHDB_IGNORED_ASGN_INVALID_NODE_NAME" "IO_STANDARD LEDR\[3\]#============================================================ " "Ignored assignment IO_STANDARD which contains an invalid node name \"LEDR\[3\]#============================================================\"" {  } {  } 1 136021 "Ignored assignment %1!s! which contains an invalid node name \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420463659 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480420463871 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480420463871 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/rom.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/rom.v" { { "Info" "ISGN_ENTITY_NAME" "1 ROM " "Found entity 1: ROM" {  } { { "verilog_files/ROM.v" "" { Text "C:/New folder/ex13/verilog_files/ROM.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420472180 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420472180 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_10.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_10.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_10 " "Found entity 1: counter_10" {  } { { "verilog_files/counter_10.v" "" { Text "C:/New folder/ex13/verilog_files/counter_10.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420472181 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420472181 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex13.v 1 1 " "Found 1 design units, including 1 entities, in source file ex13.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex13 " "Found entity 1: ex13" {  } { { "ex13.v" "" { Text "C:/New folder/ex13/ex13.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420472183 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420472183 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_5000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_5000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_5000 " "Found entity 1: tick_5000" {  } { { "verilog_files/tick_5000.v" "" { Text "C:/New folder/ex13/verilog_files/tick_5000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420472184 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420472184 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2dac.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2dac " "Found entity 1: spi2dac" {  } { { "verilog_files/spi2dac.v" "" { Text "C:/New folder/ex13/verilog_files/spi2dac.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420472186 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420472186 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Found entity 1: pwm" {  } { { "verilog_files/pwm.v" "" { Text "C:/New folder/ex13/verilog_files/pwm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420472188 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420472188 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex13 " "Elaborating entity \"ex13\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480420472214 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_5000 tick_5000:t " "Elaborating entity \"tick_5000\" for hierarchy \"tick_5000:t\"" {  } { { "ex13.v" "t" { Text "C:/New folder/ex13/ex13.v" 9 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420472220 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_10 counter_10:c " "Elaborating entity \"counter_10\" for hierarchy \"counter_10:c\"" {  } { { "ex13.v" "c" { Text "C:/New folder/ex13/ex13.v" 11 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420472221 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ROM ROM:r " "Elaborating entity \"ROM\" for hierarchy \"ROM:r\"" {  } { { "ex13.v" "r" { Text "C:/New folder/ex13/ex13.v" 13 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420472222 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ROM:r\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ROM:r\|altsyncram:altsyncram_component\"" {  } { { "verilog_files/ROM.v" "altsyncram_component" { Text "C:/New folder/ex13/verilog_files/ROM.v" 82 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420472278 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "ROM:r\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ROM:r\|altsyncram:altsyncram_component\"" {  } { { "verilog_files/ROM.v" "" { Text "C:/New folder/ex13/verilog_files/ROM.v" 82 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420472289 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ROM:r\|altsyncram:altsyncram_component " "Instantiated megafunction \"ROM:r\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom_data/rom_data.mif " "Parameter \"init_file\" = \"./rom_data/rom_data.mif\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone V " "Parameter \"intended_device_family\" = \"Cyclone V\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 10 " "Parameter \"width_a\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""}  } { { "verilog_files/ROM.v" "" { Text "C:/New folder/ex13/verilog_files/ROM.v" 82 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1480420472290 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_6ng1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_6ng1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_6ng1 " "Found entity 1: altsyncram_6ng1" {  } { { "db/altsyncram_6ng1.tdf" "" { Text "C:/New folder/ex13/db/altsyncram_6ng1.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420472331 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420472331 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_6ng1 ROM:r\|altsyncram:altsyncram_component\|altsyncram_6ng1:auto_generated " "Elaborating entity \"altsyncram_6ng1\" for hierarchy \"ROM:r\|altsyncram:altsyncram_component\|altsyncram_6ng1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420472332 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2dac spi2dac:s " "Elaborating entity \"spi2dac\" for hierarchy \"spi2dac:s\"" {  } { { "ex13.v" "s" { Text "C:/New folder/ex13/ex13.v" 15 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420472354 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm pwm:p " "Elaborating entity \"pwm\" for hierarchy \"pwm:p\"" {  } { { "ex13.v" "p" { Text "C:/New folder/ex13/ex13.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420472355 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480420472975 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480420473259 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420473259 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "115 " "Implemented 115 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480420473301 ""} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Implemented 5 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480420473301 ""} { "Info" "ICUT_CUT_TM_LCELLS" "99 " "Implemented 99 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480420473301 ""} { "Info" "ICUT_CUT_TM_RAMS" "10 " "Implemented 10 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1480420473301 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480420473301 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "902 " "Peak virtual memory: 902 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480420473313 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 29 11:54:33 2016 " "Processing ended: Tue Nov 29 11:54:33 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480420473313 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480420473313 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480420473313 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420473313 ""}