diff options
Diffstat (limited to 'dot_product/dot_product/dot_product.v5/schedule.gnt')
| -rw-r--r-- | dot_product/dot_product/dot_product.v5/schedule.gnt | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/dot_product/dot_product/dot_product.v5/schedule.gnt b/dot_product/dot_product/dot_product.v5/schedule.gnt new file mode 100644 index 0000000..0f012ab --- /dev/null +++ b/dot_product/dot_product/dot_product.v5/schedule.gnt @@ -0,0 +1,43 @@ +set a(0-191) {NAME MAC:asn TYPE ASSIGN PAR 0-190 XREFS 525 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{262 0 0-226 {}}} SUCCS {{259 0 0-192 {}} {256 0 0-226 {}}} CYCLES {}} +set a(0-192) {NAME MAC:select TYPE SELECT PAR 0-190 XREFS 526 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{259 0 0-191 {}}} SUCCS {} CYCLES {}} +set a(0-193) {NAME MAC:asn#4 TYPE ASSIGN PAR 0-190 XREFS 527 LOC {0 1.0 1 0.6507022499999999 1 0.6507022499999999 1 0.6507022499999999} PREDS {{262 0 0-226 {}}} SUCCS {{259 0 0-194 {}} {256 0 0-226 {}}} CYCLES {}} +set a(0-194) {NAME MAC:not#2 TYPE NOT PAR 0-190 XREFS 528 LOC {1 0.0 1 0.6507022499999999 1 0.6507022499999999 1 0.6507022499999999} PREDS {{259 0 0-193 {}}} SUCCS {{259 0 0-195 {}}} CYCLES {}} +set a(0-195) {NAME MAC:exs#1 TYPE SIGNEXTEND PAR 0-190 XREFS 529 LOC {1 0.0 1 0.6507022499999999 1 0.6507022499999999 1 0.6507022499999999} PREDS {{259 0 0-194 {}}} SUCCS {{259 0 0-196 {}}} CYCLES {}} +set a(0-196) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(3,2) AREA_SCORE 2.19 QUANTITY 1 NAME MAC:and#1 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-190 XREFS 530 LOC {1 0.0 1 0.6507022499999999 1 0.6507022499999999 1 0.6671089812638539 1 0.6671089812638539} PREDS {{262 0 0-225 {}} {259 0 0-195 {}}} SUCCS {{258 0 0-208 {}} {258 0 0-214 {}} {258 0 0-217 {}} {256 0 0-225 {}}} CYCLES {}} +set a(0-197) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,40) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_a:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-190 XREFS 531 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{80 0 0-198 {}}} SUCCS {{80 0 0-198 {}} {258 0 0-203 {}} {258 0 0-204 {}} {258 0 0-205 {}} {258 0 0-206 {}} {258 0 0-207 {}}} CYCLES {}} +set a(0-198) {LIBRARY mgc_ioport MODULE mgc_in_wire(2,40) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_b:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-190 XREFS 532 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{80 0 0-197 {}}} SUCCS {{80 0 0-197 {}} {258 0 0-209 {}} {258 0 0-210 {}} {258 0 0-211 {}} {258 0 0-212 {}} {258 0 0-213 {}}} CYCLES {}} +set a(0-199) {NAME MAC:asn#5 TYPE ASSIGN PAR 0-190 XREFS 533 LOC {0 1.0 1 0.910898475 1 0.910898475 1 0.910898475} PREDS {{262 0 0-226 {}}} SUCCS {{259 0 0-200 {}} {256 0 0-226 {}}} CYCLES {}} +set a(0-200) {NAME MAC:not#1 TYPE NOT PAR 0-190 XREFS 534 LOC {1 0.0 1 0.910898475 1 0.910898475 1 0.910898475} PREDS {{259 0 0-199 {}}} SUCCS {{259 0 0-201 {}}} CYCLES {}} +set a(0-201) {NAME MAC:exs TYPE SIGNEXTEND PAR 0-190 XREFS 535 LOC {1 0.0 1 0.910898475 1 0.910898475 1 0.910898475} PREDS {{259 0 0-200 {}}} SUCCS {{259 0 0-202 {}}} CYCLES {}} +set a(0-202) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(8,2) AREA_SCORE 5.84 QUANTITY 1 NAME MAC:and TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-190 XREFS 536 LOC {1 0.0 1 0.910898475 1 0.910898475 1 0.9273052062638539 1 0.9273052062638539} PREDS {{262 0 0-224 {}} {259 0 0-201 {}}} SUCCS {{258 0 0-216 {}} {256 0 0-224 {}}} CYCLES {}} +set a(0-203) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt) TYPE READSLICE PAR 0-190 XREFS 537 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-197 {}}} SUCCS {{258 0 0-208 {}}} CYCLES {}} +set a(0-204) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#1 TYPE READSLICE PAR 0-190 XREFS 538 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-197 {}}} SUCCS {{258 0 0-208 {}}} CYCLES {}} +set a(0-205) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#2 TYPE READSLICE PAR 0-190 XREFS 539 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-197 {}}} SUCCS {{258 0 0-208 {}}} CYCLES {}} +set a(0-206) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#3 TYPE READSLICE PAR 0-190 XREFS 540 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-197 {}}} SUCCS {{258 0 0-208 {}}} CYCLES {}} +set a(0-207) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#4 TYPE READSLICE PAR 0-190 XREFS 541 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-197 {}}} SUCCS {{259 0 0-208 {}}} CYCLES {}} +set a(0-208) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(8,3,8) AREA_SCORE 38.71 QUANTITY 2 NAME MAC:mux TYPE MUX DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-190 XREFS 542 LOC {1 0.016406775 1 0.667109025 1 0.667109025 1 0.7611039625 1 0.7611039625} PREDS {{258 0 0-196 {}} {258 0 0-206 {}} {258 0 0-205 {}} {258 0 0-204 {}} {258 0 0-203 {}} {259 0 0-207 {}}} SUCCS {{258 0 0-215 {}}} CYCLES {}} +set a(0-209) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt) TYPE READSLICE PAR 0-190 XREFS 543 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-198 {}}} SUCCS {{258 0 0-214 {}}} CYCLES {}} +set a(0-210) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#1 TYPE READSLICE PAR 0-190 XREFS 544 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-198 {}}} SUCCS {{258 0 0-214 {}}} CYCLES {}} +set a(0-211) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#2 TYPE READSLICE PAR 0-190 XREFS 545 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-198 {}}} SUCCS {{258 0 0-214 {}}} CYCLES {}} +set a(0-212) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#3 TYPE READSLICE PAR 0-190 XREFS 546 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-198 {}}} SUCCS {{258 0 0-214 {}}} CYCLES {}} +set a(0-213) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#4 TYPE READSLICE PAR 0-190 XREFS 547 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-198 {}}} SUCCS {{259 0 0-214 {}}} CYCLES {}} +set a(0-214) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(8,3,8) AREA_SCORE 38.71 QUANTITY 2 NAME MAC:mux#3 TYPE MUX DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-190 XREFS 548 LOC {1 0.016406775 1 0.667109025 1 0.667109025 1 0.7611039625 1 0.7611039625} PREDS {{258 0 0-196 {}} {258 0 0-212 {}} {258 0 0-211 {}} {258 0 0-210 {}} {258 0 0-209 {}} {259 0 0-213 {}}} SUCCS {{259 0 0-215 {}}} CYCLES {}} +set a(0-215) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-190 XREFS 549 LOC {1 0.110401775 1 0.761104025 1 0.761104025 1 0.9273051907433434 1 0.9273051907433434} PREDS {{258 0 0-208 {}} {259 0 0-214 {}}} SUCCS {{259 0 0-216 {}}} CYCLES {}} +set a(0-216) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 1 NAME MAC:acc#3 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-190 XREFS 550 LOC {1 0.276603 1 0.92730525 1 0.92730525 1 0.9999999527684257 1 0.9999999527684257} PREDS {{258 0 0-202 {}} {259 0 0-215 {}}} SUCCS {{258 0 0-223 {}} {258 0 0-224 {}}} CYCLES {}} +set a(0-217) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,2,1,3) AREA_SCORE 4.00 QUANTITY 1 NAME MAC:acc#4 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-190 XREFS 551 LOC {1 0.016406775 1 0.898700525 1 0.898700525 1 0.9464762270241717 1 0.9464762270241717} PREDS {{258 0 0-196 {}}} SUCCS {{259 0 0-218 {}} {258 0 0-225 {}}} CYCLES {}} +set a(0-218) {NAME MAC:asn#3 TYPE ASSIGN PAR 0-190 XREFS 552 LOC {1 0.06418252499999999 1 0.946476275 1 0.946476275 1 0.946476275} PREDS {{259 0 0-217 {}}} SUCCS {{259 0 0-219 {}}} CYCLES {}} +set a(0-219) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,3,0,4) AREA_SCORE 5.30 QUANTITY 1 NAME MAC:acc TYPE ACCU DELAY {0.86 ns} LIBRARY_DELAY {0.86 ns} PAR 0-190 XREFS 553 LOC {1 0.06418252499999999 1 0.946476275 1 0.946476275 1 0.9999999399089293 1 0.9999999399089293} PREDS {{259 0 0-218 {}}} SUCCS {{259 0 0-220 {}}} CYCLES {}} +set a(0-220) {NAME MAC:slc TYPE READSLICE PAR 0-190 XREFS 554 LOC {1 0.11770625 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-219 {}}} SUCCS {{259 0 0-221 {}}} CYCLES {}} +set a(0-221) {NAME MAC:not TYPE NOT PAR 0-190 XREFS 555 LOC {1 0.11770625 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-220 {}}} SUCCS {{259 0 0-222 {}} {258 0 0-226 {}}} CYCLES {}} +set a(0-222) {NAME MAC:select#1 TYPE SELECT PAR 0-190 XREFS 556 LOC {1 0.11770625 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-221 {}}} SUCCS {{131 0 0-223 {}}} CYCLES {}} +set a(0-223) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(3,8) AREA_SCORE 0.00 QUANTITY 1 NAME io_write(output:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-190 XREFS 557 LOC {1 1.0 1 1.0 1 1.0 2 0.0 1 0.9999} PREDS {{260 0 0-223 {}} {258 0 0-216 {}} {131 0 0-222 {}}} SUCCS {{260 0 0-223 {}}} CYCLES {}} +set a(0-224) {NAME MAC:asn(acc.lpi) TYPE ASSIGN PAR 0-190 XREFS 558 LOC {1 0.34929774999999996 1 1.0 1 1.0 2 0.910898475} PREDS {{260 0 0-224 {}} {256 0 0-202 {}} {258 0 0-216 {}}} SUCCS {{262 0 0-202 {}} {260 0 0-224 {}}} CYCLES {}} +set a(0-225) {NAME MAC:asn(i#1.lpi) TYPE ASSIGN PAR 0-190 XREFS 559 LOC {1 0.06418252499999999 1 0.946476275 1 0.946476275 2 0.6507022499999999} PREDS {{260 0 0-225 {}} {256 0 0-196 {}} {258 0 0-217 {}}} SUCCS {{262 0 0-196 {}} {260 0 0-225 {}}} CYCLES {}} +set a(0-226) {NAME MAC:asn(exit:MAC.lpi) TYPE ASSIGN PAR 0-190 XREFS 560 LOC {1 0.11770625 1 1.0 1 1.0 2 0.6507022499999999} PREDS {{260 0 0-226 {}} {256 0 0-191 {}} {256 0 0-193 {}} {256 0 0-199 {}} {258 0 0-221 {}}} SUCCS {{262 0 0-191 {}} {262 0 0-193 {}} {262 0 0-199 {}} {260 0 0-226 {}}} CYCLES {}} +set a(0-190) {CHI {0-191 0-192 0-193 0-194 0-195 0-196 0-197 0-198 0-199 0-200 0-201 0-202 0-203 0-204 0-205 0-206 0-207 0-208 0-209 0-210 0-211 0-212 0-213 0-214 0-215 0-216 0-217 0-218 0-219 0-220 0-221 0-222 0-223 0-224 0-225 0-226} ITERATIONS Infinite LATENCY 5 RESET_LATENCY 0 CSTEPS 2 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 5 %_SHARING_ALLOC {20.0 %} PIPELINED Yes INITIATION 1 STAGES 2.0 CYCLES_IN 5 TOTAL_CYCLES_IN 5 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 5 NAME main TYPE LOOP DELAY {120.00 ns} PAR {} XREFS 561 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}} +set a(0-190-TOTALCYCLES) {5} +set a(0-190-QMOD) {mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(3,2) 0-196 mgc_ioport.mgc_in_wire(1,40) 0-197 mgc_ioport.mgc_in_wire(2,40) 0-198 mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(8,2) 0-202 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(8,3,8) {0-208 0-214} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(8,0,8,0,8) 0-215 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) 0-216 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,1,3) 0-217 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,4) 0-219 mgc_ioport.mgc_out_stdreg(3,8) 0-223} +set a(0-190-PROC_NAME) {core} +set a(0-190-HIER_NAME) {/dot_product/core} +set a(TOP) {0-190} + |