diff options
Diffstat (limited to 'student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sta.rpt')
| -rw-r--r-- | student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sta.rpt | 558 |
1 files changed, 558 insertions, 0 deletions
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sta.rpt b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sta.rpt new file mode 100644 index 0000000..b364c36 --- /dev/null +++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sta.rpt @@ -0,0 +1,558 @@ +TimeQuest Timing Analyzer report for ise_proj +Tue Mar 01 16:05:15 2016 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Timing Closure Recommendations + 7. Slow 1200mV 85C Model Setup Summary + 8. Slow 1200mV 85C Model Hold Summary + 9. Slow 1200mV 85C Model Recovery Summary + 10. Slow 1200mV 85C Model Removal Summary + 11. Slow 1200mV 85C Model Minimum Pulse Width Summary + 12. Slow 1200mV 85C Model Datasheet Report + 13. Slow 1200mV 85C Model Metastability Report + 14. Slow 1200mV 0C Model Fmax Summary + 15. Slow 1200mV 0C Model Setup Summary + 16. Slow 1200mV 0C Model Hold Summary + 17. Slow 1200mV 0C Model Recovery Summary + 18. Slow 1200mV 0C Model Removal Summary + 19. Slow 1200mV 0C Model Minimum Pulse Width Summary + 20. Slow 1200mV 0C Model Datasheet Report + 21. Slow 1200mV 0C Model Metastability Report + 22. Fast 1200mV 0C Model Setup Summary + 23. Fast 1200mV 0C Model Hold Summary + 24. Fast 1200mV 0C Model Recovery Summary + 25. Fast 1200mV 0C Model Removal Summary + 26. Fast 1200mV 0C Model Minimum Pulse Width Summary + 27. Fast 1200mV 0C Model Datasheet Report + 28. Fast 1200mV 0C Model Metastability Report + 29. Multicorner Timing Analysis Summary + 30. Board Trace Model Assignments + 31. Input Transition Times + 32. Slow Corner Signal Integrity Metrics + 33. Fast Corner Signal Integrity Metrics + 34. Clock Transfers + 35. Report TCCS + 36. Report RSKM + 37. Unconstrained Paths + 38. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+--------------------------------------------------------------------+ +; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version ; +; Revision Name ; ise_proj ; +; Device Family ; Cyclone III ; +; Device Name ; EP3C16F484C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++--------------------+--------------------------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; < 0.1% ; +; Processors 5-8 ; 0.0% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Datasheet Report ; +------------------------------------------ +Nothing to report. + + +---------------------------------------------- +; Slow 1200mV 85C Model Metastability Report ; +---------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Datasheet Report ; +----------------------------------------- +Nothing to report. + + +--------------------------------------------- +; Slow 1200mV 0C Model Metastability Report ; +--------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Datasheet Report ; +----------------------------------------- +Nothing to report. + + +--------------------------------------------- +; Fast 1200mV 0C Model Metastability Report ; +--------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; VGA_CLK ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_SYNC ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_BLANK ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_VS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_HS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0_D[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0_D[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0_D[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0_D[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0_D[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0_D[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0_D[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_B[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_B[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_B[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_B[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_G[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_G[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_G[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_G[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_R[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_R[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_R[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_R[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; PS2_MSDAT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; PS2_MSCLK ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; CLOCK_50_2 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; BUTTON[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; BUTTON[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; BUTTON[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow Corner Signal Integrity Metrics ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; VGA_CLK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.08e-06 V ; 2.36 V ; -0.0113 V ; 0.122 V ; 0.022 V ; 4.5e-10 s ; 4.45e-10 s ; Yes ; Yes ; 2.32 V ; 1.08e-06 V ; 2.36 V ; -0.0113 V ; 0.122 V ; 0.022 V ; 4.5e-10 s ; 4.45e-10 s ; Yes ; Yes ; +; VGA_SYNC ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.08e-06 V ; 2.36 V ; -0.0113 V ; 0.122 V ; 0.022 V ; 4.5e-10 s ; 4.45e-10 s ; Yes ; Yes ; 2.32 V ; 1.08e-06 V ; 2.36 V ; -0.0113 V ; 0.122 V ; 0.022 V ; 4.5e-10 s ; 4.45e-10 s ; Yes ; Yes ; +; VGA_BLANK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.08e-06 V ; 2.36 V ; -0.0113 V ; 0.122 V ; 0.022 V ; 4.5e-10 s ; 4.45e-10 s ; Yes ; Yes ; 2.32 V ; 1.08e-06 V ; 2.36 V ; -0.0113 V ; 0.122 V ; 0.022 V ; 4.5e-10 s ; 4.45e-10 s ; Yes ; Yes ; +; VGA_VS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_HS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; HEX0_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; LEDG[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.08 V ; -0.00513 V ; 0.274 V ; 0.267 V ; 5.67e-09 s ; 4.62e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.08 V ; -0.00513 V ; 0.274 V ; 0.267 V ; 5.67e-09 s ; 4.62e-09 s ; No ; Yes ; +; LEDG[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_B[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_B[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_B[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_B[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_G[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_G[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_G[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_G[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_R[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_R[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_R[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_R[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.02e-06 V ; 3.14 V ; -0.0402 V ; 0.146 V ; 0.156 V ; 4.62e-10 s ; 4.36e-10 s ; Yes ; Yes ; 3.08 V ; 1.02e-06 V ; 3.14 V ; -0.0402 V ; 0.146 V ; 0.156 V ; 4.62e-10 s ; 4.36e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast Corner Signal Integrity Metrics ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; VGA_CLK ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.11e-08 V ; 2.73 V ; -0.0566 V ; 0.191 V ; 0.12 V ; 2.69e-10 s ; 2.76e-10 s ; Yes ; Yes ; 2.62 V ; 4.11e-08 V ; 2.73 V ; -0.0566 V ; 0.191 V ; 0.12 V ; 2.69e-10 s ; 2.76e-10 s ; Yes ; Yes ; +; VGA_SYNC ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.11e-08 V ; 2.73 V ; -0.0566 V ; 0.191 V ; 0.12 V ; 2.69e-10 s ; 2.76e-10 s ; Yes ; Yes ; 2.62 V ; 4.11e-08 V ; 2.73 V ; -0.0566 V ; 0.191 V ; 0.12 V ; 2.69e-10 s ; 2.76e-10 s ; Yes ; Yes ; +; VGA_BLANK ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.11e-08 V ; 2.73 V ; -0.0566 V ; 0.191 V ; 0.12 V ; 2.69e-10 s ; 2.76e-10 s ; Yes ; Yes ; 2.62 V ; 4.11e-08 V ; 2.73 V ; -0.0566 V ; 0.191 V ; 0.12 V ; 2.69e-10 s ; 2.76e-10 s ; Yes ; Yes ; +; VGA_VS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_HS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; HEX0_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; LEDG[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.346 V ; 4.12e-09 s ; 3.34e-09 s ; No ; Yes ; 3.46 V ; 1.29e-07 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.346 V ; 4.12e-09 s ; 3.34e-09 s ; No ; Yes ; +; LEDG[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_B[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_B[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_B[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_B[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_G[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_G[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_G[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_G[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_R[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_R[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_R[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_R[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.52e-08 V ; 3.58 V ; -0.064 V ; 0.234 V ; 0.085 V ; 2.93e-10 s ; 3.07e-10 s ; Yes ; Yes ; 3.46 V ; 6.52e-08 V ; 3.58 V ; -0.064 V ; 0.234 V ; 0.085 V ; 2.93e-10 s ; 3.07e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 0 ; 0 ; +; Unconstrained Input Port Paths ; 0 ; 0 ; +; Unconstrained Output Ports ; 0 ; 0 ; +; Unconstrained Output Port Paths ; 0 ; 0 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version + Info: Processing started: Tue Mar 01 16:05:13 2016 +Info: Command: quartus_sta ise_proj -c ise_proj +Info: qsta_default_script.tcl version: #1 +Warning (20013): Ignored assignments for entity "DE0_TOP" -- entity does not exist in design + Warning (20014): Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_TOP -section_id "Root Region" was ignored + Warning (20014): Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_TOP -section_id "Root Region" was ignored + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_TOP -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_TOP -section_id Top was ignored +Warning (20013): Ignored assignments for entity "DE0_VGA" -- entity does not exist in design + Warning (20014): Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_VGA -section_id "Root Region" was ignored + Warning (20014): Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_VGA -section_id "Root Region" was ignored + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_VGA -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_VGA -section_id Top was ignored +Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. +Info (21077): Core supply voltage is 1.2V +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'ise_proj.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332101): Design is fully constrained for setup requirements +Info (332101): Design is fully constrained for hold requirements +Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 54 warnings + Info: Peak virtual memory: 480 megabytes + Info: Processing ended: Tue Mar 01 16:05:15 2016 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:01 + + |