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Diffstat (limited to 'student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.rpt')
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diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.rpt new file mode 100644 index 0000000..187778f --- /dev/null +++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.rpt @@ -0,0 +1,2506 @@ +Analysis & Synthesis report for DE0_D5M +Mon Mar 17 10:02:21 2014 +Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis RAM Summary + 9. Analysis & Synthesis IP Cores Summary + 10. State Machine - |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST + 11. Registers Removed During Synthesis + 12. Removed Registers Triggering Further Register Optimizations + 13. General Register Statistics + 14. Inverted Register Statistics + 15. Multiplexer Restructuring Statistics (Restructuring Performed) + 16. Source assignments for DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2 + 17. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component + 18. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated + 19. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p + 20. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p + 21. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram + 22. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp + 23. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp + 24. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp + 25. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 + 26. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp + 27. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp + 28. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp + 29. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 + 30. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component + 31. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated + 32. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p + 33. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p + 34. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram + 35. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp + 36. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp + 37. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp + 38. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 + 39. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp + 40. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp + 41. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp + 42. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 + 43. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component + 44. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated + 45. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p + 46. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p + 47. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram + 48. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp + 49. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp + 50. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp + 51. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 + 52. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp + 53. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp + 54. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp + 55. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 + 56. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component + 57. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated + 58. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p + 59. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p + 60. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram + 61. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp + 62. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp + 63. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp + 64. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 + 65. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp + 66. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp + 67. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp + 68. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 + 69. Parameter Settings for User Entity Instance: DE0_D5M:inst|VGA_Controller:u1 + 70. Parameter Settings for User Entity Instance: DE0_D5M:inst|CCD_Capture:u3 + 71. Parameter Settings for User Entity Instance: DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component + 72. Parameter Settings for User Entity Instance: DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component + 73. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7 + 74. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1 + 75. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1 + 76. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1 + 77. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component + 78. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component + 79. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component + 80. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component + 81. Parameter Settings for User Entity Instance: DE0_D5M:inst|I2C_CCD_Config:u8 + 82. altshift_taps Parameter Settings by Entity Instance + 83. altpll Parameter Settings by Entity Instance + 84. dcfifo Parameter Settings by Entity Instance + 85. Port Connectivity Checks: "DE0_D5M:inst|I2C_CCD_Config:u8" + 86. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2" + 87. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1" + 88. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2" + 89. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1" + 90. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1" + 91. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1" + 92. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7" + 93. Port Connectivity Checks: "DE0_D5M:inst|SEG7_LUT_8:u5" + 94. Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0" + 95. Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4" + 96. Port Connectivity Checks: "DE0_D5M:inst|CCD_Capture:u3" + 97. Port Connectivity Checks: "DE0_D5M:inst|VGA_Controller:u1" + 98. Elapsed Time Per Partition + 99. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Mon Mar 17 10:02:21 2014 ; +; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ; +; Revision Name ; DE0_D5M ; +; Top-level Entity Name ; TOP_CAMERA ; +; Family ; Cyclone III ; +; Total logic elements ; 1,569 ; +; Total combinational functions ; 1,198 ; +; Dedicated logic registers ; 1,030 ; +; Total registers ; 1030 ; +; Total pins ; 141 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 53,200 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 1 ; ++------------------------------------+---------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP3C16F484C6 ; ; +; Top-level entity name ; TOP_CAMERA ; DE0_D5M ; +; Family name ; Cyclone III ; Cyclone IV GX ; +; Use smart compilation ; On ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Synthesis Seed ; 1 ; 1 ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; < 0.1% ; +; Processors 5-8 ; 0.0% ; ++----------------------------+-------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++-------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++-------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------+---------+ +; Sdram_Control_4Port/Sdram_Params.h ; yes ; User Unspecified File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_Params.h ; ; +; Sdram_Control_4Port/command.v ; yes ; User Verilog HDL File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/command.v ; ; +; Sdram_Control_4Port/control_interface.v ; yes ; User Verilog HDL File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/control_interface.v ; ; +; Sdram_Control_4Port/sdr_data_path.v ; yes ; User Verilog HDL File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/sdr_data_path.v ; ; +; Sdram_Control_4Port/Sdram_Control_4Port.v ; yes ; User Verilog HDL File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_Control_4Port.v ; ; +; Sdram_Control_4Port/Sdram_FIFO.v ; yes ; User Wizard-Generated File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v ; ; +; V/VGA_Param.h ; yes ; User Unspecified File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/VGA_Param.h ; ; +; V/CCD_Capture.v ; yes ; User Verilog HDL File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/CCD_Capture.v ; ; +; V/I2C_CCD_Config.v ; yes ; User Verilog HDL File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/I2C_CCD_Config.v ; ; +; V/I2C_Controller.v ; yes ; User Verilog HDL File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/I2C_Controller.v ; ; +; V/Line_Buffer.v ; yes ; User Wizard-Generated File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/Line_Buffer.v ; ; +; V/RAW2RGB.v ; yes ; User Verilog HDL File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/RAW2RGB.v ; ; +; V/Reset_Delay.v ; yes ; User Verilog HDL File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/Reset_Delay.v ; ; +; V/sdram_pll.v ; yes ; User Wizard-Generated File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/sdram_pll.v ; ; +; V/SEG7_LUT.v ; yes ; User Verilog HDL File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/SEG7_LUT.v ; ; +; V/SEG7_LUT_8.v ; yes ; User Verilog HDL File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/SEG7_LUT_8.v ; ; +; V/VGA_Controller.v ; yes ; User Verilog HDL File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/VGA_Controller.v ; ; +; DE0_D5M.v ; yes ; User Verilog HDL File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.v ; ; +; TOP_CAMERA.bdf ; yes ; User Block Diagram/Schematic File ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/TOP_CAMERA.bdf ; ; +; altshift_taps.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altshift_taps.tdf ; ; +; altdpram.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altdpram.inc ; ; +; lpm_counter.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_counter.inc ; ; +; lpm_compare.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_compare.inc ; ; +; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_constant.inc ; ; +; db/shift_taps_rnn.tdf ; yes ; Auto-Generated Megafunction ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/shift_taps_rnn.tdf ; ; +; db/altsyncram_lp81.tdf ; yes ; Auto-Generated Megafunction ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/altsyncram_lp81.tdf ; ; +; db/cntr_cuf.tdf ; yes ; Auto-Generated Megafunction ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/cntr_cuf.tdf ; ; +; db/cmpr_vgc.tdf ; yes ; Auto-Generated Megafunction ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/cmpr_vgc.tdf ; ; +; altpll.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altpll.tdf ; ; +; aglobal131.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc ; ; +; stratix_pll.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/stratix_pll.inc ; ; +; stratixii_pll.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/stratixii_pll.inc ; ; +; cycloneii_pll.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc ; ; +; db/altpll_9ee2.tdf ; yes ; Auto-Generated Megafunction ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/altpll_9ee2.tdf ; ; +; dcfifo.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/dcfifo.tdf ; ; +; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ; +; a_graycounter.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/a_graycounter.inc ; ; +; a_fefifo.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/a_fefifo.inc ; ; +; a_gray2bin.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/a_gray2bin.inc ; ; +; dffpipe.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/dffpipe.inc ; ; +; alt_sync_fifo.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/alt_sync_fifo.inc ; ; +; altsyncram_fifo.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altsyncram_fifo.inc ; ; +; db/dcfifo_v5o1.tdf ; yes ; Auto-Generated Megafunction ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/dcfifo_v5o1.tdf ; ; +; db/a_gray2bin_tgb.tdf ; yes ; Auto-Generated Megafunction ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/a_gray2bin_tgb.tdf ; ; +; db/a_graycounter_s57.tdf ; yes ; Auto-Generated Megafunction ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/a_graycounter_s57.tdf ; ; +; db/a_graycounter_ojc.tdf ; yes ; Auto-Generated Megafunction ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/a_graycounter_ojc.tdf ; ; +; db/altsyncram_de51.tdf ; yes ; Auto-Generated Megafunction ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/altsyncram_de51.tdf ; ; +; db/dffpipe_oe9.tdf ; yes ; Auto-Generated Megafunction ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/dffpipe_oe9.tdf ; ; +; db/alt_synch_pipe_qld.tdf ; yes ; Auto-Generated Megafunction ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/alt_synch_pipe_qld.tdf ; ; +; db/dffpipe_pe9.tdf ; yes ; Auto-Generated Megafunction ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/dffpipe_pe9.tdf ; ; +; db/alt_synch_pipe_rld.tdf ; yes ; Auto-Generated Megafunction ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/alt_synch_pipe_rld.tdf ; ; +; db/dffpipe_qe9.tdf ; yes ; Auto-Generated Megafunction ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/dffpipe_qe9.tdf ; ; +; db/cmpr_e66.tdf ; yes ; Auto-Generated Megafunction ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/cmpr_e66.tdf ; ; ++-------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------+---------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------------------------------------------------------------------------------------+ +; Resource ; Usage ; ++---------------------------------------------+-------------------------------------------------------------------------------------+ +; Estimated Total logic elements ; 1,569 ; +; ; ; +; Total combinational functions ; 1198 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 544 ; +; -- 3 input functions ; 261 ; +; -- <=2 input functions ; 393 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 886 ; +; -- arithmetic mode ; 312 ; +; ; ; +; Total registers ; 1030 ; +; -- Dedicated logic registers ; 1030 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 141 ; +; Total memory bits ; 53200 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 1 ; +; -- PLLs ; 1 ; +; ; ; +; Maximum fan-out node ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ; +; Maximum fan-out ; 547 ; +; Total fan-out ; 8862 ; +; Average fan-out ; 3.37 ; ++---------------------------------------------+-------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++-----------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++-----------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; |TOP_CAMERA ; 1198 (2) ; 1030 (0) ; 53200 ; 0 ; 0 ; 0 ; 141 ; 0 ; |TOP_CAMERA ; work ; +; |DE0_D5M:inst| ; 1196 (1) ; 1030 (15) ; 53200 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst ; work ; +; |CCD_Capture:u3| ; 66 (66) ; 58 (58) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|CCD_Capture:u3 ; work ; +; |I2C_CCD_Config:u8| ; 237 (168) ; 132 (94) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8 ; work ; +; |I2C_Controller:u0| ; 69 (69) ; 38 (38) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0 ; work ; +; |RAW2RGB:u4| ; 84 (68) ; 66 (55) ; 30672 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4 ; work ; +; |Line_Buffer:u0| ; 16 (0) ; 11 (0) ; 30672 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0 ; work ; +; |altshift_taps:altshift_taps_component| ; 16 (0) ; 11 (0) ; 30672 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component ; work ; +; |shift_taps_rnn:auto_generated| ; 16 (0) ; 11 (0) ; 30672 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated ; work ; +; |altsyncram_lp81:altsyncram2| ; 0 (0) ; 0 (0) ; 30672 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2 ; work ; +; |cntr_cuf:cntr1| ; 16 (13) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1 ; work ; +; |cmpr_vgc:cmpr4| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4 ; work ; +; |Reset_Delay:u2| ; 50 (50) ; 35 (35) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Reset_Delay:u2 ; work ; +; |SEG7_LUT_8:u5| ; 28 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5 ; work ; +; |SEG7_LUT:u0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u0 ; work ; +; |SEG7_LUT:u1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u1 ; work ; +; |SEG7_LUT:u2| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u2 ; work ; +; |SEG7_LUT:u3| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u3 ; work ; +; |Sdram_Control_4Port:u7| ; 668 (212) ; 697 (130) ; 22528 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7 ; work ; +; |Sdram_FIFO:read_fifo1| ; 82 (0) ; 116 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1 ; work ; +; |dcfifo:dcfifo_component| ; 82 (0) ; 116 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ; work ; +; |dcfifo_v5o1:auto_generated| ; 82 (15) ; 116 (30) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ; work ; +; |a_gray2bin_tgb:wrptr_g_gray2bin| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin ; work ; +; |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin ; work ; +; |a_graycounter_ojc:wrptr_g1p| ; 19 (19) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ; work ; +; |a_graycounter_s57:rdptr_g1p| ; 19 (19) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ; work ; +; |alt_synch_pipe_qld:rs_dgwp| ; 0 (0) ; 20 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ; work ; +; |dffpipe_pe9:dffpipe13| ; 0 (0) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work ; +; |alt_synch_pipe_rld:ws_dgrp| ; 0 (0) ; 20 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ; work ; +; |dffpipe_qe9:dffpipe16| ; 0 (0) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work ; +; |altsyncram_de51:fifo_ram| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ; work ; +; |cmpr_e66:rdempty_eq_comp| ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp ; work ; +; |cmpr_e66:wrfull_eq_comp| ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp ; work ; +; |dffpipe_oe9:ws_brp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ; work ; +; |dffpipe_oe9:ws_bwp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ; work ; +; |Sdram_FIFO:read_fifo2| ; 82 (0) ; 116 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2 ; work ; +; |dcfifo:dcfifo_component| ; 82 (0) ; 116 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ; work ; +; |dcfifo_v5o1:auto_generated| ; 82 (15) ; 116 (30) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ; work ; +; |a_gray2bin_tgb:wrptr_g_gray2bin| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin ; work ; +; |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin ; work ; +; |a_graycounter_ojc:wrptr_g1p| ; 19 (19) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ; work ; +; |a_graycounter_s57:rdptr_g1p| ; 19 (19) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ; work ; +; |alt_synch_pipe_qld:rs_dgwp| ; 0 (0) ; 20 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ; work ; +; |dffpipe_pe9:dffpipe13| ; 0 (0) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work ; +; |alt_synch_pipe_rld:ws_dgrp| ; 0 (0) ; 20 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ; work ; +; |dffpipe_qe9:dffpipe16| ; 0 (0) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work ; +; |altsyncram_de51:fifo_ram| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ; work ; +; |cmpr_e66:rdempty_eq_comp| ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp ; work ; +; |cmpr_e66:wrfull_eq_comp| ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp ; work ; +; |dffpipe_oe9:ws_brp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ; work ; +; |dffpipe_oe9:ws_bwp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ; work ; +; |Sdram_FIFO:write_fifo1| ; 84 (0) ; 116 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1 ; work ; +; |dcfifo:dcfifo_component| ; 84 (0) ; 116 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ; work ; +; |dcfifo_v5o1:auto_generated| ; 84 (15) ; 116 (30) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ; work ; +; |a_gray2bin_tgb:rdptr_g_gray2bin| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin ; work ; +; |a_gray2bin_tgb:rs_dgwp_gray2bin| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin ; work ; +; |a_graycounter_ojc:wrptr_g1p| ; 19 (19) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ; work ; +; |a_graycounter_s57:rdptr_g1p| ; 20 (20) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ; work ; +; |alt_synch_pipe_qld:rs_dgwp| ; 0 (0) ; 20 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ; work ; +; |dffpipe_pe9:dffpipe13| ; 0 (0) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work ; +; |alt_synch_pipe_rld:ws_dgrp| ; 0 (0) ; 20 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ; work ; +; |dffpipe_qe9:dffpipe16| ; 0 (0) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work ; +; |altsyncram_de51:fifo_ram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ; work ; +; |cmpr_e66:rdempty_eq_comp| ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp ; work ; +; |cmpr_e66:wrfull_eq_comp| ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp ; work ; +; |dffpipe_oe9:rs_brp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ; work ; +; |dffpipe_oe9:rs_bwp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ; work ; +; |Sdram_FIFO:write_fifo2| ; 84 (0) ; 116 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2 ; work ; +; |dcfifo:dcfifo_component| ; 84 (0) ; 116 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ; work ; +; |dcfifo_v5o1:auto_generated| ; 84 (15) ; 116 (30) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ; work ; +; |a_gray2bin_tgb:rdptr_g_gray2bin| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin ; work ; +; |a_gray2bin_tgb:rs_dgwp_gray2bin| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin ; work ; +; |a_graycounter_ojc:wrptr_g1p| ; 19 (19) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ; work ; +; |a_graycounter_s57:rdptr_g1p| ; 20 (20) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ; work ; +; |alt_synch_pipe_qld:rs_dgwp| ; 0 (0) ; 20 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ; work ; +; |dffpipe_pe9:dffpipe13| ; 0 (0) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work ; +; |alt_synch_pipe_rld:ws_dgrp| ; 0 (0) ; 20 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ; work ; +; |dffpipe_qe9:dffpipe16| ; 0 (0) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work ; +; |altsyncram_de51:fifo_ram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ; work ; +; |cmpr_e66:rdempty_eq_comp| ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp ; work ; +; |cmpr_e66:wrfull_eq_comp| ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp ; work ; +; |dffpipe_oe9:rs_brp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ; work ; +; |dffpipe_oe9:rs_bwp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ; work ; +; |command:command1| ; 60 (60) ; 48 (48) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1 ; work ; +; |control_interface:control1| ; 64 (64) ; 55 (55) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1 ; work ; +; |VGA_Controller:u1| ; 62 (62) ; 27 (27) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|VGA_Controller:u1 ; work ; +; |sdram_pll:u6| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6 ; work ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component ; work ; +; |altpll_9ee2:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated ; work ; ++-----------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis RAM Summary ; ++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ +; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; ++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1278 ; 24 ; 1278 ; 24 ; 30672 ; None ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512 ; 16 ; 512 ; 16 ; 8192 ; None ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512 ; 16 ; 512 ; 16 ; 8192 ; None ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512 ; 16 ; 512 ; 16 ; 8192 ; None ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512 ; 16 ; 512 ; 16 ; 8192 ; None ; ++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------+----------------------------+---------+--------------+--------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+ +; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; ++--------+----------------------------+---------+--------------+--------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+ +; Altera ; Shift register (RAM-based) ; N/A ; N/A ; N/A ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0 ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/Line_Buffer.v ; +; Altera ; ALTPLL ; N/A ; N/A ; N/A ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6 ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/sdram_pll.v ; +; Altera ; FIFO ; N/A ; N/A ; N/A ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1 ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v ; +; Altera ; FIFO ; N/A ; N/A ; N/A ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2 ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v ; +; Altera ; FIFO ; N/A ; N/A ; N/A ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1 ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v ; +; Altera ; FIFO ; N/A ; N/A ; N/A ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2 ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v ; ++--------+----------------------------+---------+--------------+--------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+ + + +Encoding Type: One-Hot ++----------------------------------------------------------------------+ +; State Machine - |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST ; ++----------------+----------------+----------------+-------------------+ +; Name ; mSetup_ST.0000 ; mSetup_ST.0010 ; mSetup_ST.0001 ; ++----------------+----------------+----------------+-------------------+ +; mSetup_ST.0000 ; 0 ; 0 ; 0 ; +; mSetup_ST.0001 ; 1 ; 0 ; 1 ; +; mSetup_ST.0010 ; 1 ; 1 ; 0 ; ++----------------+----------------+----------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+ +; Register name ; Reason for Removal ; ++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+ +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[8] ; Stuck at VCC due to stuck port data_in ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[0..7] ; Stuck at GND due to stuck port data_in ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_LENGTH[8] ; Stuck at VCC due to stuck port data_in ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_LENGTH[0..7] ; Stuck at GND due to stuck port data_in ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_LENGTH[8] ; Stuck at VCC due to stuck port data_in ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_LENGTH[0..7] ; Stuck at GND due to stuck port data_in ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_LENGTH[8] ; Stuck at VCC due to stuck port data_in ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_LENGTH[0..7] ; Stuck at GND due to stuck port data_in ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[0..5,10,15] ; Lost fanout ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CKE ; Stuck at VCC due to stuck port data_in ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|CKE ; Stuck at VCC due to stuck port data_in ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[31] ; Stuck at VCC due to stuck port data_in ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[30] ; Stuck at GND due to stuck port data_in ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[27..29] ; Stuck at VCC due to stuck port data_in ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[26] ; Stuck at GND due to stuck port data_in ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[25] ; Stuck at VCC due to stuck port data_in ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[24] ; Stuck at GND due to stuck port data_in ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[31] ; Stuck at VCC due to stuck port data_in ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[30] ; Stuck at GND due to stuck port data_in ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[27..29] ; Stuck at VCC due to stuck port data_in ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[26] ; Stuck at GND due to stuck port data_in ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[25] ; Stuck at VCC due to stuck port data_in ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[24] ; Stuck at GND due to stuck port data_in ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[9] ; Lost fanout ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[9] ; Lost fanout ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[9] ; Lost fanout ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[9] ; Lost fanout ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[9] ; Lost fanout ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[9] ; Lost fanout ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[9] ; Lost fanout ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[9] ; Lost fanout ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[0..6] ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[7] ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[0..6] ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[7] ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[0..6] ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[7] ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[0..6] ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[7] ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[0..6] ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7] ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[0..6] ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7] ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[0..6] ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7] ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[1,2] ; Merged with DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[7] ; Stuck at GND due to stuck port data_in ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[7] ; Stuck at GND due to stuck port data_in ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[7] ; Stuck at GND due to stuck port data_in ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[7] ; Stuck at GND due to stuck port data_in ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7] ; Stuck at GND due to stuck port data_in ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7] ; Stuck at GND due to stuck port data_in ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7] ; Stuck at GND due to stuck port data_in ; +; DE0_D5M:inst|rClk[1] ; Lost fanout ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[8] ; Stuck at VCC due to stuck port data_in ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST~9 ; Lost fanout ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST~10 ; Lost fanout ; +; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[16..31] ; Lost fanout ; +; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[10..15] ; Lost fanout ; +; Total Number of Removed Registers = 154 ; ; ++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Removed Registers Triggering Further Register Optimizations ; ++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+ +; Register name ; Reason for Removal ; Registers Removed due to This Register ; ++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+ +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[8] ; Stuck at VCC ; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7], ; +; ; due to stuck port data_in ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7], ; +; ; ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7], ; +; ; ; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[8] ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CKE ; Stuck at VCC ; DE0_D5M:inst|Sdram_Control_4Port:u7|CKE ; +; ; due to stuck port data_in ; ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[31] ; Stuck at VCC ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[31] ; +; ; due to stuck port data_in ; ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[30] ; Stuck at GND ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[30] ; +; ; due to stuck port data_in ; ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[29] ; Stuck at VCC ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[29] ; +; ; due to stuck port data_in ; ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[28] ; Stuck at VCC ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[28] ; +; ; due to stuck port data_in ; ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[27] ; Stuck at VCC ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[27] ; +; ; due to stuck port data_in ; ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[26] ; Stuck at GND ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[26] ; +; ; due to stuck port data_in ; ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[25] ; Stuck at VCC ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[25] ; +; ; due to stuck port data_in ; ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[24] ; Stuck at GND ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[24] ; +; ; due to stuck port data_in ; ; ++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 1030 ; +; Number of registers using Synchronous Clear ; 129 ; +; Number of registers using Synchronous Load ; 81 ; +; Number of registers using Asynchronous Clear ; 723 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 393 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Inverted Register Statistics ; ++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +; Inverted Register ; Fan out ; ++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5] ; 12 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[4] ; 13 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3] ; 22 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[2] ; 19 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[1] ; 17 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[0] ; 20 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|END ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; 4 ; +; Total number of inverted registers = 30 ; ; ++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------+ +; 4:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|mCCD_G[3] ; +; 4:1 ; 20 bits ; 40 LEs ; 40 LEs ; 0 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|mCCD_R[9] ; +; 3:1 ; 11 bits ; 22 LEs ; 22 LEs ; 0 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9] ; +; 3:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[8] ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2] ; +; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; +; 4:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|CCD_Capture:u3|X_Cont[12] ; +; 4:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|CCD_Capture:u3|Y_Cont[5] ; +; 4:1 ; 15 bits ; 30 LEs ; 15 LEs ; 15 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; +; 4:1 ; 15 bits ; 30 LEs ; 15 LEs ; 15 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; +; 4:1 ; 15 bits ; 30 LEs ; 15 LEs ; 15 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; +; 4:1 ; 15 bits ; 30 LEs ; 15 LEs ; 15 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; +; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0] ; +; 5:1 ; 15 bits ; 45 LEs ; 30 LEs ; 15 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; +; 64:1 ; 5 bits ; 210 LEs ; 60 LEs ; 150 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[15] ; +; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0] ; +; 7:1 ; 3 bits ; 12 LEs ; 9 LEs ; 3 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0] ; +; 7:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1] ; +; 7:1 ; 10 bits ; 40 LEs ; 20 LEs ; 20 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9] ; +; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3] ; +; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|Mux12 ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2 ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ; ++---------------------------------+-------+------+----------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+----------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+----------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ; ++---------------------------------------+-------+------+-------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------------+-------+------+-------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; +; REMOVE_DUPLICATE_REGISTERS ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; +; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2 ; - ; - ; +; POWER_UP_LEVEL ; LOW ; - ; wrptr_g ; ++---------------------------------------+-------+------+-------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ; ++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+ +; POWER_UP_LEVEL ; HIGH ; - ; counter5a0 ; +; POWER_UP_LEVEL ; HIGH ; - ; parity6 ; ++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ; ++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+ +; POWER_UP_LEVEL ; HIGH ; - ; counter8a0 ; +; POWER_UP_LEVEL ; HIGH ; - ; parity9 ; ++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ; ++---------------------------------+-------+------+----------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+----------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+----------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ; ++---------------------------------------+-------+------+-------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------------+-------+------+-------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; +; REMOVE_DUPLICATE_REGISTERS ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; +; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2 ; - ; - ; +; POWER_UP_LEVEL ; LOW ; - ; wrptr_g ; ++---------------------------------------+-------+------+-------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ; ++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+ +; POWER_UP_LEVEL ; HIGH ; - ; counter5a0 ; +; POWER_UP_LEVEL ; HIGH ; - ; parity6 ; ++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ; ++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+ +; POWER_UP_LEVEL ; HIGH ; - ; counter8a0 ; +; POWER_UP_LEVEL ; HIGH ; - ; parity9 ; ++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ; ++---------------------------------+-------+------+---------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+---------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+---------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ; ++---------------------------------------+-------+------+------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------------+-------+------+------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; +; REMOVE_DUPLICATE_REGISTERS ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; +; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2 ; - ; - ; +; POWER_UP_LEVEL ; LOW ; - ; wrptr_g ; ++---------------------------------------+-------+------+------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+ +; POWER_UP_LEVEL ; HIGH ; - ; counter5a0 ; +; POWER_UP_LEVEL ; HIGH ; - ; parity6 ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+ +; POWER_UP_LEVEL ; HIGH ; - ; counter8a0 ; +; POWER_UP_LEVEL ; HIGH ; - ; parity9 ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ; ++---------------------------------+-------+------+---------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+---------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+---------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ; ++---------------------------------------+-------+------+------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------------+-------+------+------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; +; REMOVE_DUPLICATE_REGISTERS ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; +; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2 ; - ; - ; +; POWER_UP_LEVEL ; LOW ; - ; wrptr_g ; ++---------------------------------------+-------+------+------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+ +; POWER_UP_LEVEL ; HIGH ; - ; counter5a0 ; +; POWER_UP_LEVEL ; HIGH ; - ; parity6 ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+ +; POWER_UP_LEVEL ; HIGH ; - ; counter8a0 ; +; POWER_UP_LEVEL ; HIGH ; - ; parity9 ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: DE0_D5M:inst|VGA_Controller:u1 ; ++----------------+-------+----------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------+ +; H_SYNC_CYC ; 96 ; Signed Integer ; +; H_SYNC_BACK ; 48 ; Signed Integer ; +; H_SYNC_ACT ; 640 ; Signed Integer ; +; H_SYNC_FRONT ; 16 ; Signed Integer ; +; H_SYNC_TOTAL ; 800 ; Signed Integer ; +; V_SYNC_CYC ; 2 ; Signed Integer ; +; V_SYNC_BACK ; 33 ; Signed Integer ; +; V_SYNC_ACT ; 480 ; Signed Integer ; +; V_SYNC_FRONT ; 10 ; Signed Integer ; +; V_SYNC_TOTAL ; 525 ; Signed Integer ; +; X_START ; 144 ; Signed Integer ; +; Y_START ; 35 ; Signed Integer ; ++----------------+-------+----------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: DE0_D5M:inst|CCD_Capture:u3 ; ++----------------+-------+-------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------------+ +; COLUMN_WIDTH ; 1280 ; Signed Integer ; ++----------------+-------+-------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component ; ++----------------+----------------+-----------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+----------------+-----------------------------------------------------------------------------------------+ +; WIDTH_BYTEENA ; 1 ; Untyped ; +; NUMBER_OF_TAPS ; 2 ; Signed Integer ; +; TAP_DISTANCE ; 1280 ; Signed Integer ; +; WIDTH ; 12 ; Signed Integer ; +; POWER_UP_STATE ; CLEARED ; Untyped ; +; CBXI_PARAMETER ; shift_taps_rnn ; Untyped ; ++----------------+----------------+-----------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component ; ++-------------------------------+-------------------+--------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------------+-------------------+--------------------------------------------+ +; OPERATION_MODE ; NORMAL ; Untyped ; +; PLL_TYPE ; AUTO ; Untyped ; +; LPM_HINT ; UNUSED ; Untyped ; +; QUALIFY_CONF_DONE ; OFF ; Untyped ; +; COMPENSATE_CLOCK ; CLK0 ; Untyped ; +; SCAN_CHAIN ; LONG ; Untyped ; +; PRIMARY_CLOCK ; INCLK0 ; Untyped ; +; INCLK0_INPUT_FREQUENCY ; 20000 ; Signed Integer ; +; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; +; GATE_LOCK_SIGNAL ; NO ; Untyped ; +; GATE_LOCK_COUNTER ; 0 ; Untyped ; +; LOCK_HIGH ; 1 ; Untyped ; +; LOCK_LOW ; 1 ; Untyped ; +; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; +; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; +; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; +; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; +; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; +; SKIP_VCO ; OFF ; Untyped ; +; SWITCH_OVER_COUNTER ; 0 ; Untyped ; +; SWITCH_OVER_TYPE ; AUTO ; Untyped ; +; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; +; BANDWIDTH ; 0 ; Untyped ; +; BANDWIDTH_TYPE ; AUTO ; Untyped ; +; SPREAD_FREQUENCY ; 0 ; Untyped ; +; DOWN_SPREAD ; 0 ; Untyped ; +; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; +; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; +; CLK9_MULTIPLY_BY ; 0 ; Untyped ; +; CLK8_MULTIPLY_BY ; 0 ; Untyped ; +; CLK7_MULTIPLY_BY ; 0 ; Untyped ; +; CLK6_MULTIPLY_BY ; 0 ; Untyped ; +; CLK5_MULTIPLY_BY ; 1 ; Untyped ; +; CLK4_MULTIPLY_BY ; 1 ; Untyped ; +; CLK3_MULTIPLY_BY ; 1 ; Untyped ; +; CLK2_MULTIPLY_BY ; 1 ; Untyped ; +; CLK1_MULTIPLY_BY ; 5 ; Signed Integer ; +; CLK0_MULTIPLY_BY ; 5 ; Signed Integer ; +; CLK9_DIVIDE_BY ; 0 ; Untyped ; +; CLK8_DIVIDE_BY ; 0 ; Untyped ; +; CLK7_DIVIDE_BY ; 0 ; Untyped ; +; CLK6_DIVIDE_BY ; 0 ; Untyped ; +; CLK5_DIVIDE_BY ; 1 ; Untyped ; +; CLK4_DIVIDE_BY ; 1 ; Untyped ; +; CLK3_DIVIDE_BY ; 1 ; Untyped ; +; CLK2_DIVIDE_BY ; 1 ; Untyped ; +; CLK1_DIVIDE_BY ; 2 ; Signed Integer ; +; CLK0_DIVIDE_BY ; 2 ; Signed Integer ; +; CLK9_PHASE_SHIFT ; 0 ; Untyped ; +; CLK8_PHASE_SHIFT ; 0 ; Untyped ; +; CLK7_PHASE_SHIFT ; 0 ; Untyped ; +; CLK6_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_PHASE_SHIFT ; 0 ; Untyped ; +; CLK4_PHASE_SHIFT ; 0 ; Untyped ; +; CLK3_PHASE_SHIFT ; 0 ; Untyped ; +; CLK2_PHASE_SHIFT ; 0 ; Untyped ; +; CLK1_PHASE_SHIFT ; -2600 ; Untyped ; +; CLK0_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_TIME_DELAY ; 0 ; Untyped ; +; CLK4_TIME_DELAY ; 0 ; Untyped ; +; CLK3_TIME_DELAY ; 0 ; Untyped ; +; CLK2_TIME_DELAY ; 0 ; Untyped ; +; CLK1_TIME_DELAY ; 0 ; Untyped ; +; CLK0_TIME_DELAY ; 0 ; Untyped ; +; CLK9_DUTY_CYCLE ; 50 ; Untyped ; +; CLK8_DUTY_CYCLE ; 50 ; Untyped ; +; CLK7_DUTY_CYCLE ; 50 ; Untyped ; +; CLK6_DUTY_CYCLE ; 50 ; Untyped ; +; CLK5_DUTY_CYCLE ; 50 ; Untyped ; +; CLK4_DUTY_CYCLE ; 50 ; Untyped ; +; CLK3_DUTY_CYCLE ; 50 ; Untyped ; +; CLK2_DUTY_CYCLE ; 50 ; Untyped ; +; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; LOCK_WINDOW_UI ; 0.05 ; Untyped ; +; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; +; DPA_MULTIPLY_BY ; 0 ; Untyped ; +; DPA_DIVIDE_BY ; 1 ; Untyped ; +; DPA_DIVIDER ; 0 ; Untyped ; +; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; +; VCO_MULTIPLY_BY ; 0 ; Untyped ; +; VCO_DIVIDE_BY ; 0 ; Untyped ; +; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; +; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; +; VCO_MIN ; 0 ; Untyped ; +; VCO_MAX ; 0 ; Untyped ; +; VCO_CENTER ; 0 ; Untyped ; +; PFD_MIN ; 0 ; Untyped ; +; PFD_MAX ; 0 ; Untyped ; +; M_INITIAL ; 0 ; Untyped ; +; M ; 0 ; Untyped ; +; N ; 1 ; Untyped ; +; M2 ; 1 ; Untyped ; +; N2 ; 1 ; Untyped ; +; SS ; 1 ; Untyped ; +; C0_HIGH ; 0 ; Untyped ; +; C1_HIGH ; 0 ; Untyped ; +; C2_HIGH ; 0 ; Untyped ; +; C3_HIGH ; 0 ; Untyped ; +; C4_HIGH ; 0 ; Untyped ; +; C5_HIGH ; 0 ; Untyped ; +; C6_HIGH ; 0 ; Untyped ; +; C7_HIGH ; 0 ; Untyped ; +; C8_HIGH ; 0 ; Untyped ; +; C9_HIGH ; 0 ; Untyped ; +; C0_LOW ; 0 ; Untyped ; +; C1_LOW ; 0 ; Untyped ; +; C2_LOW ; 0 ; Untyped ; +; C3_LOW ; 0 ; Untyped ; +; C4_LOW ; 0 ; Untyped ; +; C5_LOW ; 0 ; Untyped ; +; C6_LOW ; 0 ; Untyped ; +; C7_LOW ; 0 ; Untyped ; +; C8_LOW ; 0 ; Untyped ; +; C9_LOW ; 0 ; Untyped ; +; C0_INITIAL ; 0 ; Untyped ; +; C1_INITIAL ; 0 ; Untyped ; +; C2_INITIAL ; 0 ; Untyped ; +; C3_INITIAL ; 0 ; Untyped ; +; C4_INITIAL ; 0 ; Untyped ; +; C5_INITIAL ; 0 ; Untyped ; +; C6_INITIAL ; 0 ; Untyped ; +; C7_INITIAL ; 0 ; Untyped ; +; C8_INITIAL ; 0 ; Untyped ; +; C9_INITIAL ; 0 ; Untyped ; +; C0_MODE ; BYPASS ; Untyped ; +; C1_MODE ; BYPASS ; Untyped ; +; C2_MODE ; BYPASS ; Untyped ; +; C3_MODE ; BYPASS ; Untyped ; +; C4_MODE ; BYPASS ; Untyped ; +; C5_MODE ; BYPASS ; Untyped ; +; C6_MODE ; BYPASS ; Untyped ; +; C7_MODE ; BYPASS ; Untyped ; +; C8_MODE ; BYPASS ; Untyped ; +; C9_MODE ; BYPASS ; Untyped ; +; C0_PH ; 0 ; Untyped ; +; C1_PH ; 0 ; Untyped ; +; C2_PH ; 0 ; Untyped ; +; C3_PH ; 0 ; Untyped ; +; C4_PH ; 0 ; Untyped ; +; C5_PH ; 0 ; Untyped ; +; C6_PH ; 0 ; Untyped ; +; C7_PH ; 0 ; Untyped ; +; C8_PH ; 0 ; Untyped ; +; C9_PH ; 0 ; Untyped ; +; L0_HIGH ; 1 ; Untyped ; +; L1_HIGH ; 1 ; Untyped ; +; G0_HIGH ; 1 ; Untyped ; +; G1_HIGH ; 1 ; Untyped ; +; G2_HIGH ; 1 ; Untyped ; +; G3_HIGH ; 1 ; Untyped ; +; E0_HIGH ; 1 ; Untyped ; +; E1_HIGH ; 1 ; Untyped ; +; E2_HIGH ; 1 ; Untyped ; +; E3_HIGH ; 1 ; Untyped ; +; L0_LOW ; 1 ; Untyped ; +; L1_LOW ; 1 ; Untyped ; +; G0_LOW ; 1 ; Untyped ; +; G1_LOW ; 1 ; Untyped ; +; G2_LOW ; 1 ; Untyped ; +; G3_LOW ; 1 ; Untyped ; +; E0_LOW ; 1 ; Untyped ; +; E1_LOW ; 1 ; Untyped ; +; E2_LOW ; 1 ; Untyped ; +; E3_LOW ; 1 ; Untyped ; +; L0_INITIAL ; 1 ; Untyped ; +; L1_INITIAL ; 1 ; Untyped ; +; G0_INITIAL ; 1 ; Untyped ; +; G1_INITIAL ; 1 ; Untyped ; +; G2_INITIAL ; 1 ; Untyped ; +; G3_INITIAL ; 1 ; Untyped ; +; E0_INITIAL ; 1 ; Untyped ; +; E1_INITIAL ; 1 ; Untyped ; +; E2_INITIAL ; 1 ; Untyped ; +; E3_INITIAL ; 1 ; Untyped ; +; L0_MODE ; BYPASS ; Untyped ; +; L1_MODE ; BYPASS ; Untyped ; +; G0_MODE ; BYPASS ; Untyped ; +; G1_MODE ; BYPASS ; Untyped ; +; G2_MODE ; BYPASS ; Untyped ; +; G3_MODE ; BYPASS ; Untyped ; +; E0_MODE ; BYPASS ; Untyped ; +; E1_MODE ; BYPASS ; Untyped ; +; E2_MODE ; BYPASS ; Untyped ; +; E3_MODE ; BYPASS ; Untyped ; +; L0_PH ; 0 ; Untyped ; +; L1_PH ; 0 ; Untyped ; +; G0_PH ; 0 ; Untyped ; +; G1_PH ; 0 ; Untyped ; +; G2_PH ; 0 ; Untyped ; +; G3_PH ; 0 ; Untyped ; +; E0_PH ; 0 ; Untyped ; +; E1_PH ; 0 ; Untyped ; +; E2_PH ; 0 ; Untyped ; +; E3_PH ; 0 ; Untyped ; +; M_PH ; 0 ; Untyped ; +; C1_USE_CASC_IN ; OFF ; Untyped ; +; C2_USE_CASC_IN ; OFF ; Untyped ; +; C3_USE_CASC_IN ; OFF ; Untyped ; +; C4_USE_CASC_IN ; OFF ; Untyped ; +; C5_USE_CASC_IN ; OFF ; Untyped ; +; C6_USE_CASC_IN ; OFF ; Untyped ; +; C7_USE_CASC_IN ; OFF ; Untyped ; +; C8_USE_CASC_IN ; OFF ; Untyped ; +; C9_USE_CASC_IN ; OFF ; Untyped ; +; CLK0_COUNTER ; G0 ; Untyped ; +; CLK1_COUNTER ; G0 ; Untyped ; +; CLK2_COUNTER ; G0 ; Untyped ; +; CLK3_COUNTER ; G0 ; Untyped ; +; CLK4_COUNTER ; G0 ; Untyped ; +; CLK5_COUNTER ; G0 ; Untyped ; +; CLK6_COUNTER ; E0 ; Untyped ; +; CLK7_COUNTER ; E1 ; Untyped ; +; CLK8_COUNTER ; E2 ; Untyped ; +; CLK9_COUNTER ; E3 ; Untyped ; +; L0_TIME_DELAY ; 0 ; Untyped ; +; L1_TIME_DELAY ; 0 ; Untyped ; +; G0_TIME_DELAY ; 0 ; Untyped ; +; G1_TIME_DELAY ; 0 ; Untyped ; +; G2_TIME_DELAY ; 0 ; Untyped ; +; G3_TIME_DELAY ; 0 ; Untyped ; +; E0_TIME_DELAY ; 0 ; Untyped ; +; E1_TIME_DELAY ; 0 ; Untyped ; +; E2_TIME_DELAY ; 0 ; Untyped ; +; E3_TIME_DELAY ; 0 ; Untyped ; +; M_TIME_DELAY ; 0 ; Untyped ; +; N_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_COUNTER ; E3 ; Untyped ; +; EXTCLK2_COUNTER ; E2 ; Untyped ; +; EXTCLK1_COUNTER ; E1 ; Untyped ; +; EXTCLK0_COUNTER ; E0 ; Untyped ; +; ENABLE0_COUNTER ; L0 ; Untyped ; +; ENABLE1_COUNTER ; L0 ; Untyped ; +; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; +; LOOP_FILTER_R ; 1.000000 ; Untyped ; +; LOOP_FILTER_C ; 5 ; Untyped ; +; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; +; VCO_POST_SCALE ; 0 ; Untyped ; +; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK0 ; PORT_USED ; Untyped ; +; PORT_CLK1 ; PORT_USED ; Untyped ; +; PORT_CLK2 ; PORT_UNUSED ; Untyped ; +; PORT_CLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLK4 ; PORT_UNUSED ; Untyped ; +; PORT_CLK5 ; PORT_UNUSED ; Untyped ; +; PORT_CLK6 ; PORT_UNUSED ; Untyped ; +; PORT_CLK7 ; PORT_UNUSED ; Untyped ; +; PORT_CLK8 ; PORT_UNUSED ; Untyped ; +; PORT_CLK9 ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; +; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; +; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; +; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; +; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_INCLK0 ; PORT_USED ; Untyped ; +; PORT_FBIN ; PORT_UNUSED ; Untyped ; +; PORT_PLLENA ; PORT_UNUSED ; Untyped ; +; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; +; PORT_ARESET ; PORT_UNUSED ; Untyped ; +; PORT_PFDENA ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; +; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; +; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; +; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; +; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_LOCKED ; PORT_UNUSED ; Untyped ; +; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; +; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; +; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; +; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; +; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; +; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; M_TEST_SOURCE ; 5 ; Untyped ; +; C0_TEST_SOURCE ; 5 ; Untyped ; +; C1_TEST_SOURCE ; 5 ; Untyped ; +; C2_TEST_SOURCE ; 5 ; Untyped ; +; C3_TEST_SOURCE ; 5 ; Untyped ; +; C4_TEST_SOURCE ; 5 ; Untyped ; +; C5_TEST_SOURCE ; 5 ; Untyped ; +; C6_TEST_SOURCE ; 5 ; Untyped ; +; C7_TEST_SOURCE ; 5 ; Untyped ; +; C8_TEST_SOURCE ; 5 ; Untyped ; +; C9_TEST_SOURCE ; 5 ; Untyped ; +; CBXI_PARAMETER ; altpll_9ee2 ; Untyped ; +; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; +; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; +; WIDTH_CLOCK ; 5 ; Signed Integer ; +; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; +; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; +; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++-------------------------------+-------------------+--------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7 ; ++----------------+-------+---------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+---------------------------------------------------------+ +; INIT_PER ; 24000 ; Signed Integer ; +; REF_PER ; 1024 ; Signed Integer ; +; SC_CL ; 3 ; Signed Integer ; +; SC_RCD ; 3 ; Signed Integer ; +; SC_RRD ; 7 ; Signed Integer ; +; SC_PM ; 1 ; Signed Integer ; +; SC_BL ; 1 ; Signed Integer ; +; SDR_BL ; 111 ; Unsigned Binary ; +; SDR_BT ; 0 ; Unsigned Binary ; +; SDR_CL ; 011 ; Unsigned Binary ; ++----------------+-------+---------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1 ; ++----------------+-------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------+ +; INIT_PER ; 24000 ; Signed Integer ; +; REF_PER ; 1024 ; Signed Integer ; +; SC_CL ; 3 ; Signed Integer ; +; SC_RCD ; 3 ; Signed Integer ; +; SC_RRD ; 7 ; Signed Integer ; +; SC_PM ; 1 ; Signed Integer ; +; SC_BL ; 1 ; Signed Integer ; +; SDR_BL ; 111 ; Unsigned Binary ; +; SDR_BT ; 0 ; Unsigned Binary ; +; SDR_CL ; 011 ; Unsigned Binary ; ++----------------+-------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1 ; ++----------------+-------+--------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------------------------------------+ +; INIT_PER ; 24000 ; Signed Integer ; +; REF_PER ; 1024 ; Signed Integer ; +; SC_CL ; 3 ; Signed Integer ; +; SC_RCD ; 3 ; Signed Integer ; +; SC_RRD ; 7 ; Signed Integer ; +; SC_PM ; 1 ; Signed Integer ; +; SC_BL ; 1 ; Signed Integer ; +; SDR_BL ; 111 ; Unsigned Binary ; +; SDR_BT ; 0 ; Unsigned Binary ; +; SDR_CL ; 011 ; Unsigned Binary ; ++----------------+-------+--------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1 ; ++----------------+-------+----------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------+ +; INIT_PER ; 24000 ; Signed Integer ; +; REF_PER ; 1024 ; Signed Integer ; +; SC_CL ; 3 ; Signed Integer ; +; SC_RCD ; 3 ; Signed Integer ; +; SC_RRD ; 7 ; Signed Integer ; +; SC_PM ; 1 ; Signed Integer ; +; SC_BL ; 1 ; Signed Integer ; +; SDR_BL ; 111 ; Unsigned Binary ; +; SDR_BT ; 0 ; Unsigned Binary ; +; SDR_CL ; 011 ; Unsigned Binary ; ++----------------+-------+----------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ; ++-------------------------+-------------+-----------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+-------------+-----------------------------------------------------------------------------------------+ +; WIDTH_BYTEENA ; 1 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_NUMWORDS ; 512 ; Signed Integer ; +; LPM_WIDTHU ; 9 ; Signed Integer ; +; LPM_SHOWAHEAD ; OFF ; Untyped ; +; UNDERFLOW_CHECKING ; ON ; Untyped ; +; OVERFLOW_CHECKING ; ON ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; DELAY_RDUSEDW ; 1 ; Untyped ; +; DELAY_WRUSEDW ; 1 ; Untyped ; +; RDSYNC_DELAYPIPE ; 3 ; Untyped ; +; WRSYNC_DELAYPIPE ; 3 ; Untyped ; +; CLOCKS_ARE_SYNCHRONIZED ; FALSE ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; ADD_USEDW_MSB_BIT ; OFF ; Untyped ; +; WRITE_ACLR_SYNCH ; OFF ; Untyped ; +; READ_ACLR_SYNCH ; OFF ; Untyped ; +; CBXI_PARAMETER ; dcfifo_v5o1 ; Untyped ; ++-------------------------+-------------+-----------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ; ++-------------------------+-------------+-----------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+-------------+-----------------------------------------------------------------------------------------+ +; WIDTH_BYTEENA ; 1 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_NUMWORDS ; 512 ; Signed Integer ; +; LPM_WIDTHU ; 9 ; Signed Integer ; +; LPM_SHOWAHEAD ; OFF ; Untyped ; +; UNDERFLOW_CHECKING ; ON ; Untyped ; +; OVERFLOW_CHECKING ; ON ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; DELAY_RDUSEDW ; 1 ; Untyped ; +; DELAY_WRUSEDW ; 1 ; Untyped ; +; RDSYNC_DELAYPIPE ; 3 ; Untyped ; +; WRSYNC_DELAYPIPE ; 3 ; Untyped ; +; CLOCKS_ARE_SYNCHRONIZED ; FALSE ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; ADD_USEDW_MSB_BIT ; OFF ; Untyped ; +; WRITE_ACLR_SYNCH ; OFF ; Untyped ; +; READ_ACLR_SYNCH ; OFF ; Untyped ; +; CBXI_PARAMETER ; dcfifo_v5o1 ; Untyped ; ++-------------------------+-------------+-----------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ; ++-------------------------+-------------+----------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+-------------+----------------------------------------------------------------------------------------+ +; WIDTH_BYTEENA ; 1 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_NUMWORDS ; 512 ; Signed Integer ; +; LPM_WIDTHU ; 9 ; Signed Integer ; +; LPM_SHOWAHEAD ; OFF ; Untyped ; +; UNDERFLOW_CHECKING ; ON ; Untyped ; +; OVERFLOW_CHECKING ; ON ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; DELAY_RDUSEDW ; 1 ; Untyped ; +; DELAY_WRUSEDW ; 1 ; Untyped ; +; RDSYNC_DELAYPIPE ; 3 ; Untyped ; +; WRSYNC_DELAYPIPE ; 3 ; Untyped ; +; CLOCKS_ARE_SYNCHRONIZED ; FALSE ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; ADD_USEDW_MSB_BIT ; OFF ; Untyped ; +; WRITE_ACLR_SYNCH ; OFF ; Untyped ; +; READ_ACLR_SYNCH ; OFF ; Untyped ; +; CBXI_PARAMETER ; dcfifo_v5o1 ; Untyped ; ++-------------------------+-------------+----------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ; ++-------------------------+-------------+----------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+-------------+----------------------------------------------------------------------------------------+ +; WIDTH_BYTEENA ; 1 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_NUMWORDS ; 512 ; Signed Integer ; +; LPM_WIDTHU ; 9 ; Signed Integer ; +; LPM_SHOWAHEAD ; OFF ; Untyped ; +; UNDERFLOW_CHECKING ; ON ; Untyped ; +; OVERFLOW_CHECKING ; ON ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; DELAY_RDUSEDW ; 1 ; Untyped ; +; DELAY_WRUSEDW ; 1 ; Untyped ; +; RDSYNC_DELAYPIPE ; 3 ; Untyped ; +; WRSYNC_DELAYPIPE ; 3 ; Untyped ; +; CLOCKS_ARE_SYNCHRONIZED ; FALSE ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; ADD_USEDW_MSB_BIT ; OFF ; Untyped ; +; WRITE_ACLR_SYNCH ; OFF ; Untyped ; +; READ_ACLR_SYNCH ; OFF ; Untyped ; +; CBXI_PARAMETER ; dcfifo_v5o1 ; Untyped ; ++-------------------------+-------------+----------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: DE0_D5M:inst|I2C_CCD_Config:u8 ; ++-----------------------+------------------+----------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------------+------------------+----------------------------------+ +; default_exposure ; 0000011111000000 ; Unsigned Binary ; +; exposure_change_value ; 0000000011001000 ; Unsigned Binary ; +; CLK_Freq ; 50000000 ; Signed Integer ; +; I2C_Freq ; 20000 ; Signed Integer ; +; LUT_SIZE ; 25 ; Signed Integer ; ++-----------------------+------------------+----------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------+ +; altshift_taps Parameter Settings by Entity Instance ; ++----------------------------+------------------------------------------------------------------------------+ +; Name ; Value ; ++----------------------------+------------------------------------------------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component ; +; -- NUMBER_OF_TAPS ; 2 ; +; -- TAP_DISTANCE ; 1280 ; +; -- WIDTH ; 12 ; ++----------------------------+------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------+ +; altpll Parameter Settings by Entity Instance ; ++-------------------------------+---------------------------------------------------+ +; Name ; Value ; ++-------------------------------+---------------------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component ; +; -- OPERATION_MODE ; NORMAL ; +; -- PLL_TYPE ; AUTO ; +; -- PRIMARY_CLOCK ; INCLK0 ; +; -- INCLK0_INPUT_FREQUENCY ; 20000 ; +; -- INCLK1_INPUT_FREQUENCY ; 0 ; +; -- VCO_MULTIPLY_BY ; 0 ; +; -- VCO_DIVIDE_BY ; 0 ; ++-------------------------------+---------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------+ +; dcfifo Parameter Settings by Entity Instance ; ++----------------------------+------------------------------------------------------------------------------------+ +; Name ; Value ; ++----------------------------+------------------------------------------------------------------------------------+ +; Number of entity instances ; 4 ; +; Entity Instance ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ; +; -- FIFO Type ; Dual Clock ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_NUMWORDS ; 512 ; +; -- LPM_SHOWAHEAD ; OFF ; +; -- USE_EAB ; ON ; +; Entity Instance ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ; +; -- FIFO Type ; Dual Clock ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_NUMWORDS ; 512 ; +; -- LPM_SHOWAHEAD ; OFF ; +; -- USE_EAB ; ON ; +; Entity Instance ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ; +; -- FIFO Type ; Dual Clock ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_NUMWORDS ; 512 ; +; -- LPM_SHOWAHEAD ; OFF ; +; -- USE_EAB ; ON ; +; Entity Instance ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ; +; -- FIFO Type ; Dual Clock ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_NUMWORDS ; 512 ; +; -- LPM_SHOWAHEAD ; OFF ; +; -- USE_EAB ; ON ; ++----------------------------+------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "DE0_D5M:inst|I2C_CCD_Config:u8" ; ++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ +; iUART_CTRL ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; ++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2" ; ++---------+--------+----------+----------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+--------+----------+----------------------------------------------------------------------------------------------------------+ +; rdempty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; rdusedw ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; wrfull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ++---------+--------+----------+----------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1" ; ++---------+--------+----------+----------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+--------+----------+----------------------------------------------------------------------------------------------------------+ +; rdempty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; rdusedw ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; wrfull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ++---------+--------+----------+----------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2" ; ++---------+--------+----------+----------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+--------+----------+----------------------------------------------------------------------------------------------------------+ +; rdempty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; wrfull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; wrusedw ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ++---------+--------+----------+----------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1" ; ++---------+--------+----------+----------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+--------+----------+----------------------------------------------------------------------------------------------------------+ +; rdempty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; wrfull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; wrusedw ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ++---------+--------+----------+----------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1" ; ++------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+--------+----------+-------------------------------------------------------------------------------------+ +; DM ; Input ; Info ; Stuck at GND ; +; DQM ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++------+--------+----------+-------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1" ; ++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ +; CMD ; Input ; Warning ; Input port expression (2 bits) is smaller than the input port (3 bits) it drives. Extra input bit(s) "CMD[2..2]" will be connected to GND. ; +; INIT_ACK ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; ++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7" ; ++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; RESET_N ; Input ; Info ; Stuck at VCC ; +; WR1_DATA[15] ; Input ; Info ; Stuck at GND ; +; WR1_ADDR ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (23 bits) it drives. The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; +; WR1_ADDR[22..0] ; Input ; Info ; Stuck at GND ; +; WR1_MAX_ADDR ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (23 bits) it drives. The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; +; WR1_MAX_ADDR[13..12] ; Input ; Info ; Stuck at VCC ; +; WR1_MAX_ADDR[22..19] ; Input ; Info ; Stuck at GND ; +; WR1_MAX_ADDR[17..16] ; Input ; Info ; Stuck at GND ; +; WR1_MAX_ADDR[11..0] ; Input ; Info ; Stuck at GND ; +; WR1_MAX_ADDR[18] ; Input ; Info ; Stuck at VCC ; +; WR1_MAX_ADDR[15] ; Input ; Info ; Stuck at VCC ; +; WR1_MAX_ADDR[14] ; Input ; Info ; Stuck at GND ; +; WR1_LENGTH[7..0] ; Input ; Info ; Stuck at GND ; +; WR1_LENGTH[8] ; Input ; Info ; Stuck at VCC ; +; WR2_DATA[15] ; Input ; Info ; Stuck at GND ; +; WR2_ADDR ; Input ; Warning ; Input port expression (22 bits) is smaller than the input port (23 bits) it drives. Extra input bit(s) "WR2_ADDR[22..22]" will be connected to GND. ; +; WR2_ADDR[19..0] ; Input ; Info ; Stuck at GND ; +; WR2_ADDR[22] ; Input ; Info ; Stuck at GND ; +; WR2_ADDR[21] ; Input ; Info ; Stuck at VCC ; +; WR2_MAX_ADDR ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (23 bits) it drives. The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; +; WR2_MAX_ADDR[13..12] ; Input ; Info ; Stuck at VCC ; +; WR2_MAX_ADDR[22..21] ; Input ; Info ; Stuck at GND ; +; WR2_MAX_ADDR[17..16] ; Input ; Info ; Stuck at GND ; +; WR2_MAX_ADDR[11..0] ; Input ; Info ; Stuck at GND ; +; WR2_MAX_ADDR[20] ; Input ; Info ; Stuck at VCC ; +; WR2_MAX_ADDR[19] ; Input ; Info ; Stuck at GND ; +; WR2_MAX_ADDR[18] ; Input ; Info ; Stuck at VCC ; +; WR2_MAX_ADDR[15] ; Input ; Info ; Stuck at VCC ; +; WR2_MAX_ADDR[14] ; Input ; Info ; Stuck at GND ; +; WR2_LENGTH[7..0] ; Input ; Info ; Stuck at GND ; +; WR2_LENGTH[8] ; Input ; Info ; Stuck at VCC ; +; RD1_DATA[15] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; RD1_ADDR ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (23 bits) it drives. The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; +; RD1_ADDR[22..0] ; Input ; Info ; Stuck at GND ; +; RD1_MAX_ADDR ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (23 bits) it drives. The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; +; RD1_MAX_ADDR[13..12] ; Input ; Info ; Stuck at VCC ; +; RD1_MAX_ADDR[22..19] ; Input ; Info ; Stuck at GND ; +; RD1_MAX_ADDR[17..16] ; Input ; Info ; Stuck at GND ; +; RD1_MAX_ADDR[11..0] ; Input ; Info ; Stuck at GND ; +; RD1_MAX_ADDR[18] ; Input ; Info ; Stuck at VCC ; +; RD1_MAX_ADDR[15] ; Input ; Info ; Stuck at VCC ; +; RD1_MAX_ADDR[14] ; Input ; Info ; Stuck at GND ; +; RD1_LENGTH[7..0] ; Input ; Info ; Stuck at GND ; +; RD1_LENGTH[8] ; Input ; Info ; Stuck at VCC ; +; RD2_DATA[15] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; RD2_ADDR ; Input ; Warning ; Input port expression (22 bits) is smaller than the input port (23 bits) it drives. Extra input bit(s) "RD2_ADDR[22..22]" will be connected to GND. ; +; RD2_ADDR[19..0] ; Input ; Info ; Stuck at GND ; +; RD2_ADDR[22] ; Input ; Info ; Stuck at GND ; +; RD2_ADDR[21] ; Input ; Info ; Stuck at VCC ; +; RD2_MAX_ADDR ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (23 bits) it drives. The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; +; RD2_MAX_ADDR[13..12] ; Input ; Info ; Stuck at VCC ; +; RD2_MAX_ADDR[22..21] ; Input ; Info ; Stuck at GND ; +; RD2_MAX_ADDR[17..16] ; Input ; Info ; Stuck at GND ; +; RD2_MAX_ADDR[11..0] ; Input ; Info ; Stuck at GND ; +; RD2_MAX_ADDR[20] ; Input ; Info ; Stuck at VCC ; +; RD2_MAX_ADDR[19] ; Input ; Info ; Stuck at GND ; +; RD2_MAX_ADDR[18] ; Input ; Info ; Stuck at VCC ; +; RD2_MAX_ADDR[15] ; Input ; Info ; Stuck at VCC ; +; RD2_MAX_ADDR[14] ; Input ; Info ; Stuck at GND ; +; RD2_LENGTH[7..0] ; Input ; Info ; Stuck at GND ; +; RD2_LENGTH[8] ; Input ; Info ; Stuck at VCC ; +; CS_N ; Output ; Warning ; Output or bidir port (2 bits) is wider than the port expression (1 bits) it drives; bit(s) "CS_N[1..1]" have no fanouts ; ++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------+ +; Port Connectivity Checks: "DE0_D5M:inst|SEG7_LUT_8:u5" ; ++-------+--------+----------+----------------------------+ +; Port ; Type ; Severity ; Details ; ++-------+--------+----------+----------------------------+ +; oSEG4 ; Output ; Info ; Explicitly unconnected ; +; oSEG5 ; Output ; Info ; Explicitly unconnected ; +; oSEG6 ; Output ; Info ; Explicitly unconnected ; +; oSEG7 ; Output ; Info ; Explicitly unconnected ; ++-------+--------+----------+----------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0" ; ++----------+--------+----------+----------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++----------+--------+----------+----------------------------------------------------------------------------------------------------------+ +; shiftout ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ++----------+--------+----------+----------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4" ; ++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; oRed[1..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; oGreen[1..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; oBlue[1..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; iX_Cont ; Input ; Warning ; Input port expression (16 bits) is wider than the input port (11 bits) it drives. The 5 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; +; iY_Cont ; Input ; Warning ; Input port expression (16 bits) is wider than the input port (11 bits) it drives. The 5 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; ++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "DE0_D5M:inst|CCD_Capture:u3" ; ++-----------------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-----------------+--------+----------+-------------------------------------------------------------------------------------+ +; oX_Cont[15..11] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; oY_Cont[15..11] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++-----------------+--------+----------+-------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "DE0_D5M:inst|VGA_Controller:u1" ; ++--------------+--------+----------+----------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------+--------+----------+----------------------------------------------------------------------------------------------------------+ +; oVGA_R[5..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; oVGA_G[5..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; oVGA_B[5..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; oVGA_SYNC ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; oVGA_BLANK ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; oVGA_CLOCK ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ++--------------+--------+----------+----------------------------------------------------------------------------------------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:02 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Analysis & Synthesis + Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version + Info: Processing started: Mon Mar 17 10:02:13 2014 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M +Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. +Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/command.v + Info (12023): Found entity 1: command +Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/control_interface.v + Info (12023): Found entity 1: control_interface +Warning (10229): Verilog HDL Expression warning at sdr_data_path.v(68): truncated literal to match 1 bits +Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdr_data_path.v + Info (12023): Found entity 1: sdr_data_path +Warning (10238): Verilog Module Declaration warning at Sdram_Control_4Port.v(90): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "Sdram_Control_4Port" +Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_control_4port.v + Info (12023): Found entity 1: Sdram_Control_4Port +Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_fifo.v + Info (12023): Found entity 1: Sdram_FIFO +Warning (12019): Can't analyze file -- file V/async_receiver.v is missing +Info (12021): Found 1 design units, including 1 entities, in source file v/ccd_capture.v + Info (12023): Found entity 1: CCD_Capture +Info (12021): Found 1 design units, including 1 entities, in source file v/i2c_ccd_config.v + Info (12023): Found entity 1: I2C_CCD_Config +Info (12021): Found 1 design units, including 1 entities, in source file v/i2c_controller.v + Info (12023): Found entity 1: I2C_Controller +Info (12021): Found 1 design units, including 1 entities, in source file v/line_buffer.v + Info (12023): Found entity 1: Line_Buffer +Info (12021): Found 1 design units, including 1 entities, in source file v/raw2rgb.v + Info (12023): Found entity 1: RAW2RGB +Info (12021): Found 1 design units, including 1 entities, in source file v/reset_delay.v + Info (12023): Found entity 1: Reset_Delay +Info (12021): Found 1 design units, including 1 entities, in source file v/sdram_pll.v + Info (12023): Found entity 1: sdram_pll +Info (12021): Found 1 design units, including 1 entities, in source file v/seg7_lut.v + Info (12023): Found entity 1: SEG7_LUT +Info (12021): Found 1 design units, including 1 entities, in source file v/seg7_lut_8.v + Info (12023): Found entity 1: SEG7_LUT_8 +Warning (12019): Can't analyze file -- file V/uart_crtl.v is missing +Info (12021): Found 1 design units, including 1 entities, in source file v/vga_controller.v + Info (12023): Found entity 1: VGA_Controller +Info (12021): Found 1 design units, including 1 entities, in source file de0_d5m.v + Info (12023): Found entity 1: DE0_D5M +Info (12021): Found 1 design units, including 1 entities, in source file top_camera.bdf + Info (12023): Found entity 1: TOP_CAMERA +Info (12127): Elaborating entity "TOP_CAMERA" for the top level hierarchy +Info (12128): Elaborating entity "DE0_D5M" for hierarchy "DE0_D5M:inst" +Warning (10230): Verilog HDL assignment warning at DE0_D5M.v(188): truncated value with size 16 to match size of target (10) +Warning (10230): Verilog HDL assignment warning at DE0_D5M.v(193): truncated value with size 32 to match size of target (2) +Warning (10034): Output port "GPIO_1_CLKOUT[1]" at DE0_D5M.v(122) has no driver +Info (12128): Elaborating entity "VGA_Controller" for hierarchy "DE0_D5M:inst|VGA_Controller:u1" +Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(47): truncated value with size 32 to match size of target (10) +Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(50): truncated value with size 32 to match size of target (10) +Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(53): truncated value with size 32 to match size of target (10) +Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(84): truncated value with size 32 to match size of target (12) +Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(110): truncated value with size 32 to match size of target (12) +Info (12128): Elaborating entity "Reset_Delay" for hierarchy "DE0_D5M:inst|Reset_Delay:u2" +Info (12128): Elaborating entity "CCD_Capture" for hierarchy "DE0_D5M:inst|CCD_Capture:u3" +Warning (10036): Verilog HDL or VHDL warning at CCD_Capture.v(162): object "ifval_fedge" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at CCD_Capture.v(163): object "y_cnt_d" assigned a value but never read +Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(123): truncated value with size 32 to match size of target (16) +Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(127): truncated value with size 32 to match size of target (16) +Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(183): truncated value with size 32 to match size of target (1) +Info (12128): Elaborating entity "RAW2RGB" for hierarchy "DE0_D5M:inst|RAW2RGB:u4" +Info (12128): Elaborating entity "Line_Buffer" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0" +Info (12128): Elaborating entity "altshift_taps" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component" +Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component" +Info (12133): Instantiated megafunction "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component" with the following parameter: + Info (12134): Parameter "lpm_type" = "altshift_taps" + Info (12134): Parameter "number_of_taps" = "2" + Info (12134): Parameter "tap_distance" = "1280" + Info (12134): Parameter "width" = "12" +Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_rnn.tdf + Info (12023): Found entity 1: shift_taps_rnn +Info (12128): Elaborating entity "shift_taps_rnn" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_lp81.tdf + Info (12023): Found entity 1: altsyncram_lp81 +Info (12128): Elaborating entity "altsyncram_lp81" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2" +Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_cuf.tdf + Info (12023): Found entity 1: cntr_cuf +Info (12128): Elaborating entity "cntr_cuf" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1" +Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_vgc.tdf + Info (12023): Found entity 1: cmpr_vgc +Info (12128): Elaborating entity "cmpr_vgc" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4" +Info (12128): Elaborating entity "SEG7_LUT_8" for hierarchy "DE0_D5M:inst|SEG7_LUT_8:u5" +Info (12128): Elaborating entity "SEG7_LUT" for hierarchy "DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u0" +Info (12128): Elaborating entity "sdram_pll" for hierarchy "DE0_D5M:inst|sdram_pll:u6" +Info (12128): Elaborating entity "altpll" for hierarchy "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component" +Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component" +Info (12133): Instantiated megafunction "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component" with the following parameter: + Info (12134): Parameter "bandwidth_type" = "AUTO" + Info (12134): Parameter "clk0_divide_by" = "2" + Info (12134): Parameter "clk0_duty_cycle" = "50" + Info (12134): Parameter "clk0_multiply_by" = "5" + Info (12134): Parameter "clk0_phase_shift" = "0" + Info (12134): Parameter "clk1_divide_by" = "2" + Info (12134): Parameter "clk1_duty_cycle" = "50" + Info (12134): Parameter "clk1_multiply_by" = "5" + Info (12134): Parameter "clk1_phase_shift" = "-2600" + Info (12134): Parameter "compensate_clock" = "CLK0" + Info (12134): Parameter "inclk0_input_frequency" = "20000" + Info (12134): Parameter "intended_device_family" = "Cyclone III" + Info (12134): Parameter "lpm_type" = "altpll" + Info (12134): Parameter "operation_mode" = "NORMAL" + Info (12134): Parameter "pll_type" = "AUTO" + Info (12134): Parameter "port_activeclock" = "PORT_UNUSED" + Info (12134): Parameter "port_areset" = "PORT_UNUSED" + Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED" + Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED" + Info (12134): Parameter "port_clkloss" = "PORT_UNUSED" + Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED" + Info (12134): Parameter "port_configupdate" = "PORT_UNUSED" + Info (12134): Parameter "port_fbin" = "PORT_UNUSED" + Info (12134): Parameter "port_inclk0" = "PORT_USED" + Info (12134): Parameter "port_inclk1" = "PORT_UNUSED" + Info (12134): Parameter "port_locked" = "PORT_UNUSED" + Info (12134): Parameter "port_pfdena" = "PORT_UNUSED" + Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED" + Info (12134): Parameter "port_phasedone" = "PORT_UNUSED" + Info (12134): Parameter "port_phasestep" = "PORT_UNUSED" + Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED" + Info (12134): Parameter "port_pllena" = "PORT_UNUSED" + Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED" + Info (12134): Parameter "port_scanclk" = "PORT_UNUSED" + Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED" + Info (12134): Parameter "port_scandata" = "PORT_UNUSED" + Info (12134): Parameter "port_scandataout" = "PORT_UNUSED" + Info (12134): Parameter "port_scandone" = "PORT_UNUSED" + Info (12134): Parameter "port_scanread" = "PORT_UNUSED" + Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED" + Info (12134): Parameter "port_clk0" = "PORT_USED" + Info (12134): Parameter "port_clk1" = "PORT_USED" + Info (12134): Parameter "port_clk2" = "PORT_UNUSED" + Info (12134): Parameter "port_clk3" = "PORT_UNUSED" + Info (12134): Parameter "port_clk4" = "PORT_UNUSED" + Info (12134): Parameter "port_clk5" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena0" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena1" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena2" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena3" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena4" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena5" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk0" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk1" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk2" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk3" = "PORT_UNUSED" + Info (12134): Parameter "width_clock" = "5" +Info (12021): Found 1 design units, including 1 entities, in source file db/altpll_9ee2.tdf + Info (12023): Found entity 1: altpll_9ee2 +Info (12128): Elaborating entity "altpll_9ee2" for hierarchy "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated" +Info (12128): Elaborating entity "Sdram_Control_4Port" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7" +Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(385): truncated value with size 32 to match size of target (10) +Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(431): truncated value with size 32 to match size of target (23) +Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(432): truncated value with size 32 to match size of target (23) +Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(433): truncated value with size 32 to match size of target (23) +Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(434): truncated value with size 32 to match size of target (23) +Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rWR1_MAX_ADDR", which holds its previous value in one or more paths through the always construct +Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rWR2_MAX_ADDR", which holds its previous value in one or more paths through the always construct +Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rRD1_MAX_ADDR", which holds its previous value in one or more paths through the always construct +Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rRD2_MAX_ADDR", which holds its previous value in one or more paths through the always construct +Info (10041): Inferred latch for "rRD2_MAX_ADDR[0]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[1]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[2]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[3]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[4]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[5]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[6]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[7]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[8]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[9]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[10]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[11]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[12]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[13]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[14]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[15]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[16]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[17]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[18]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[19]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[20]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[21]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD2_MAX_ADDR[22]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[0]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[1]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[2]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[3]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[4]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[5]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[6]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[7]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[8]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[9]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[10]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[11]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[12]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[13]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[14]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[15]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[16]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[17]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[18]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[19]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[20]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[21]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rRD1_MAX_ADDR[22]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[0]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[1]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[2]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[3]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[4]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[5]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[6]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[7]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[8]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[9]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[10]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[11]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[12]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[13]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[14]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[15]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[16]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[17]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[18]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[19]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[20]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[21]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR2_MAX_ADDR[22]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[0]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[1]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[2]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[3]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[4]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[5]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[6]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[7]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[8]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[9]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[10]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[11]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[12]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[13]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[14]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[15]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[16]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[17]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[18]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[19]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[20]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[21]" at Sdram_Control_4Port.v(423) +Info (10041): Inferred latch for "rWR1_MAX_ADDR[22]" at Sdram_Control_4Port.v(423) +Info (12128): Elaborating entity "control_interface" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1" +Warning (10230): Verilog HDL assignment warning at control_interface.v(162): truncated value with size 32 to match size of target (16) +Warning (10230): Verilog HDL assignment warning at control_interface.v(167): truncated value with size 32 to match size of target (16) +Warning (10230): Verilog HDL assignment warning at control_interface.v(192): truncated value with size 32 to match size of target (16) +Info (12128): Elaborating entity "command" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1" +Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe_shift", which holds its previous value in one or more paths through the always construct +Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe1", which holds its previous value in one or more paths through the always construct +Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe2", which holds its previous value in one or more paths through the always construct +Info (12128): Elaborating entity "sdr_data_path" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1" +Warning (10230): Verilog HDL assignment warning at sdr_data_path.v(68): truncated value with size 32 to match size of target (2) +Info (12128): Elaborating entity "Sdram_FIFO" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1" +Warning (272007): Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2 +Warning (272007): Device family Cyclone III does not have M4K blocks -- using available memory blocks +Info (12128): Elaborating entity "dcfifo" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component" +Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component" +Info (12133): Instantiated megafunction "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component" with the following parameter: + Info (12134): Parameter "add_ram_output_register" = "OFF" + Info (12134): Parameter "clocks_are_synchronized" = "FALSE" + Info (12134): Parameter "intended_device_family" = "Cyclone" + Info (12134): Parameter "lpm_hint" = "RAM_BLOCK_TYPE=M4K" + Info (12134): Parameter "lpm_numwords" = "512" + Info (12134): Parameter "lpm_showahead" = "OFF" + Info (12134): Parameter "lpm_type" = "dcfifo" + Info (12134): Parameter "lpm_width" = "16" + Info (12134): Parameter "lpm_widthu" = "9" + Info (12134): Parameter "overflow_checking" = "ON" + Info (12134): Parameter "underflow_checking" = "ON" + Info (12134): Parameter "use_eab" = "ON" +Warning (287001): Assertion warning: Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2 +Warning (287001): Assertion warning: Device family Cyclone III does not have M4K blocks -- using available memory blocks +Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_v5o1.tdf + Info (12023): Found entity 1: dcfifo_v5o1 +Info (12128): Elaborating entity "dcfifo_v5o1" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated" +Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_tgb.tdf + Info (12023): Found entity 1: a_gray2bin_tgb +Info (12128): Elaborating entity "a_gray2bin_tgb" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin" +Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_s57.tdf + Info (12023): Found entity 1: a_graycounter_s57 +Info (12128): Elaborating entity "a_graycounter_s57" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p" +Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_ojc.tdf + Info (12023): Found entity 1: a_graycounter_ojc +Info (12128): Elaborating entity "a_graycounter_ojc" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_de51.tdf + Info (12023): Found entity 1: altsyncram_de51 +Info (12128): Elaborating entity "altsyncram_de51" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram" +Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf + Info (12023): Found entity 1: dffpipe_oe9 +Info (12128): Elaborating entity "dffpipe_oe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp" +Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_qld.tdf + Info (12023): Found entity 1: alt_synch_pipe_qld +Info (12128): Elaborating entity "alt_synch_pipe_qld" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp" +Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf + Info (12023): Found entity 1: dffpipe_pe9 +Info (12128): Elaborating entity "dffpipe_pe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13" +Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_rld.tdf + Info (12023): Found entity 1: alt_synch_pipe_rld +Info (12128): Elaborating entity "alt_synch_pipe_rld" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp" +Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf + Info (12023): Found entity 1: dffpipe_qe9 +Info (12128): Elaborating entity "dffpipe_qe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16" +Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_e66.tdf + Info (12023): Found entity 1: cmpr_e66 +Info (12128): Elaborating entity "cmpr_e66" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp" +Info (12128): Elaborating entity "I2C_CCD_Config" for hierarchy "DE0_D5M:inst|I2C_CCD_Config:u8" +Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(126): truncated value with size 32 to match size of target (1) +Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(127): truncated value with size 32 to match size of target (1) +Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(160): truncated value with size 32 to match size of target (25) +Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(165): truncated value with size 32 to match size of target (1) +Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(190): truncated value with size 32 to match size of target (16) +Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(240): truncated value with size 32 to match size of target (6) +Info (12128): Elaborating entity "I2C_Controller" for hierarchy "DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0" +Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(70): truncated value with size 32 to match size of target (1) +Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(69): truncated value with size 32 to match size of target (1) +Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(82): truncated value with size 32 to match size of target (7) +Warning (14284): Synthesized away the following node(s): + Warning (14285): Synthesized away the following RAM node(s): + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]" + Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]" +Warning (12241): 10 hierarchies have connectivity warnings - see the Connectivity Checks report folder +Warning (13034): The following nodes have both tri-state and non-tri-state drivers + Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_1[20]" and its non-tri-state driver. + Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_1[14]" and its non-tri-state driver. +Warning (13039): The following bidir pins have no drivers + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver + Warning (13040): Bidir "GPIO_1" has no driver +Warning (13032): The following tri-state nodes are fed by constants + Warning (13033): The pin "GPIO_1[15]" is fed by VCC +Info (13000): Registers with preset signals will power-up high +Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back +Warning (13009): TRI or OPNDRN buffers permanently enabled + Warning (13010): Node "GPIO_1~synth" + Warning (13010): Node "GPIO_1~synth" + Warning (13010): Node "GPIO_1~synth" +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "DRAM_CKE" is stuck at VCC + Warning (13410): Pin "GPIO_1_CLKOUT[1]" is stuck at GND +Info (286030): Timing-Driven Synthesis is running +Info (17049): 41 registers lost all their fanouts during netlist optimizations. +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL +Warning (21074): Design contains 8 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "GPIO_1_CLKIN[1]" + Warning (15610): No output dependent on input pin "SW[9]" + Warning (15610): No output dependent on input pin "SW[8]" + Warning (15610): No output dependent on input pin "SW[7]" + Warning (15610): No output dependent on input pin "SW[6]" + Warning (15610): No output dependent on input pin "SW[5]" + Warning (15610): No output dependent on input pin "SW[4]" + Warning (15610): No output dependent on input pin "SW[3]" +Info (21057): Implemented 1806 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 16 input pins + Info (21059): Implemented 77 output pins + Info (21060): Implemented 48 bidirectional pins + Info (21061): Implemented 1596 logic cells + Info (21064): Implemented 68 RAM segments + Info (21065): Implemented 1 PLLs +Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 119 warnings + Info: Peak virtual memory: 534 megabytes + Info: Processing ended: Mon Mar 17 10:02:21 2014 + Info: Elapsed time: 00:00:08 + Info: Total CPU time (on all processors): 00:00:06 + + |