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Diffstat (limited to 'student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf')
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1 files changed, 132 insertions, 0 deletions
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf new file mode 100644 index 0000000..ffc210e --- /dev/null +++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf @@ -0,0 +1,132 @@ +--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" lpm_direction="UP" lpm_modulus=798 lpm_port_updown="PORT_UNUSED" lpm_width=10 clk_en clock q +--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneiii_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); +FUNCTION cmpr_ugc (dataa[9..0], datab[9..0]) +RETURNS ( aeb); + +--synthesis_resources = lut 10 reg 10 +SUBDESIGN cntr_1tf +( + clk_en : input; + clock : input; + q[9..0] : output; +) +VARIABLE + counter_comb_bita0 : cycloneiii_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita1 : cycloneiii_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita2 : cycloneiii_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita3 : cycloneiii_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita4 : cycloneiii_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita5 : cycloneiii_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita6 : cycloneiii_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita7 : cycloneiii_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita8 : cycloneiii_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita9 : cycloneiii_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_reg_bit[9..0] : dffeas; + cmpr4 : cmpr_ugc; + aclr_actual : WIRE; + cnt_en : NODE; + compare_result : WIRE; + cout_actual : WIRE; + data[9..0] : NODE; + external_cin : WIRE; + modulus_bus[9..0] : WIRE; + modulus_trigger : WIRE; + s_val[9..0] : WIRE; + safe_q[9..0] : WIRE; + sclr : NODE; + sload : NODE; + sset : NODE; + time_to_clear : WIRE; + updown_dir : WIRE; + +BEGIN + counter_comb_bita[9..0].cin = ( counter_comb_bita[8..0].cout, external_cin); + counter_comb_bita[9..0].dataa = ( counter_reg_bit[9..0].q); + counter_comb_bita[9..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); + counter_comb_bita[9..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1"); + counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & ((sload & data[]) # (((! sload) & modulus_bus[]) & (! updown_dir)))))); + counter_reg_bit[].clk = clock; + counter_reg_bit[].clrn = (! aclr_actual); + counter_reg_bit[].d = ( counter_comb_bita[9..0].combout); + counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); + counter_reg_bit[].sload = (((sclr # sset) # sload) # modulus_trigger); + cmpr4.dataa[] = safe_q[]; + cmpr4.datab[] = modulus_bus[]; + aclr_actual = B"0"; + cnt_en = VCC; + compare_result = cmpr4.aeb; + cout_actual = (counter_comb_bita[9].cout # (time_to_clear & updown_dir)); + data[] = GND; + external_cin = B"1"; + modulus_bus[] = B"1100011101"; + modulus_trigger = cout_actual; + q[] = safe_q[]; + s_val[] = B"1111111111"; + safe_q[] = counter_reg_bit[].q; + sclr = GND; + sload = GND; + sset = GND; + time_to_clear = compare_result; + updown_dir = B"1"; +END; +--VALID FILE |