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Diffstat (limited to 'student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf')
| -rw-r--r-- | student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf new file mode 100644 index 0000000..39eb4d9 --- /dev/null +++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf @@ -0,0 +1,50 @@ +--altshift_taps CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" NUMBER_OF_TAPS=5 TAP_DISTANCE=800 WIDTH=30 clken clock shiftin taps CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" +--VERSION_BEGIN 13.0 cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altshift_taps 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION altsyncram_vp81 (address_a[9..0], address_b[9..0], clock0, clocken0, data_a[149..0], wren_a) +RETURNS ( q_b[149..0]); +FUNCTION cntr_1tf (clk_en, clock) +RETURNS ( q[9..0]); + +--synthesis_resources = lut 10 M9K 17 reg 10 +SUBDESIGN shift_taps_lpm +( + clken : input; + clock : input; + shiftin[29..0] : input; + shiftout[29..0] : output; + taps[149..0] : output; +) +VARIABLE + altsyncram2 : altsyncram_vp81; + cntr1 : cntr_1tf; + +BEGIN + altsyncram2.address_a[] = cntr1.q[]; + altsyncram2.address_b[] = cntr1.q[]; + altsyncram2.clock0 = clock; + altsyncram2.clocken0 = clken; + altsyncram2.data_a[] = ( altsyncram2.q_b[119..0], shiftin[]); + altsyncram2.wren_a = B"1"; + cntr1.clk_en = clken; + cntr1.clock = clock; + shiftout[29..0] = altsyncram2.q_b[149..120]; + taps[] = altsyncram2.q_b[]; +END; +--VALID FILE |