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Analysis & Synthesis report for ise_proj
Tue Mar 01 16:05:05 2016
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. General Register Statistics
9. Elapsed Time Per Partition
10. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+--------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Mar 01 16:05:05 2016 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
; Revision Name ; ise_proj ;
; Top-level Entity Name ; ise_proj ;
; Family ; Cyclone III ;
; Total logic elements ; 0 ;
; Total combinational functions ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 51 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+--------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP3C16F484C6 ; ;
; Top-level entity name ; ise_proj ; ise_proj ;
; Family name ; Cyclone III ; Cyclone IV GX ;
; Power-Up Don't Care ; Off ; On ;
; Optimization Technique ; Speed ; Balanced ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processors 2-8 ; 0.0% ;
+----------------------------+-------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------------+----------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------------------+----------------------------------------------------------------------------------------+---------+
; ise_proj.bdf ; yes ; Auto-Found Block Diagram/Schematic File ; C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf ; ;
+----------------------------------+-----------------+------------------------------------------+----------------------------------------------------------------------------------------+---------+
+--------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+----------------+
; Resource ; Usage ;
+---------------------------------------------+----------------+
; ; ;
; Total combinational functions ; 0 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 3 input functions ; 0 ;
; -- <=2 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 0 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; -- Dedicated logic registers ; 0 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 51 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Maximum fan-out node ; VGA_CLK~output ;
; Maximum fan-out ; 1 ;
; Total fan-out ; 51 ;
; Average fan-out ; 0.50 ;
+---------------------------------------------+----------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |ise_proj ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 51 ; 0 ; |ise_proj ; work ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:00 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
Info: Processing started: Tue Mar 01 16:05:04 2016
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ise_proj -c ise_proj
Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
Info (12021): Found 7 design units, including 7 entities, in source file /catapult c/dot_product/dot_product/rtl_mgc_ioport_v2001.v
Info (12023): Found entity 1: mgc_out_reg_pos
Info (12023): Found entity 2: mgc_out_reg_neg
Info (12023): Found entity 3: mgc_out_reg
Info (12023): Found entity 4: mgc_out_buf_wait
Info (12023): Found entity 5: mgc_out_fifo_wait
Info (12023): Found entity 6: mgc_out_fifo_wait_core
Info (12023): Found entity 7: mgc_pipe
Info (12021): Found 20 design units, including 20 entities, in source file /catapult c/dot_product/dot_product/rtl_mgc_ioport.v
Info (12023): Found entity 1: mgc_in_wire
Info (12023): Found entity 2: mgc_in_wire_en
Info (12023): Found entity 3: mgc_in_wire_wait
Info (12023): Found entity 4: mgc_chan_in
Info (12023): Found entity 5: mgc_out_stdreg
Info (12023): Found entity 6: mgc_out_stdreg_en
Info (12023): Found entity 7: mgc_out_stdreg_wait
Info (12023): Found entity 8: mgc_out_prereg_en
Info (12023): Found entity 9: mgc_inout_stdreg_en
Info (12023): Found entity 10: hid_tribuf
Info (12023): Found entity 11: mgc_inout_stdreg_wait
Info (12023): Found entity 12: mgc_inout_buf_wait
Info (12023): Found entity 13: mgc_inout_fifo_wait
Info (12023): Found entity 14: mgc_io_sync
Info (12023): Found entity 15: mgc_bsync_rdy
Info (12023): Found entity 16: mgc_bsync_vld
Info (12023): Found entity 17: mgc_bsync_rv
Info (12023): Found entity 18: mgc_sync
Info (12023): Found entity 19: funccall_inout
Info (12023): Found entity 20: modulario_en_in
Info (12021): Found 3 design units, including 3 entities, in source file /catapult c/dot_product/dot_product/rtl.v
Info (12023): Found entity 1: dot_product_core_fsm
Info (12023): Found entity 2: dot_product_core
Info (12023): Found entity 3: dot_product
Warning (12125): Using design file ise_proj.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info (12023): Found entity 1: ise_proj
Info (12127): Elaborating entity "ise_proj" for the top level hierarchy
Warning (275002): No superset bus at connection
Warning (275043): Pin "VGA_CLK" is missing source
Warning (275043): Pin "VGA_SYNC" is missing source
Warning (275043): Pin "VGA_BLANK" is missing source
Warning (275043): Pin "VGA_VS" is missing source
Warning (275043): Pin "VGA_HS" is missing source
Warning (275043): Pin "HEX0_D[6..0]" is missing source
Warning (275043): Pin "VGA_B[3..0]" is missing source
Warning (275043): Pin "VGA_G[3..0]" is missing source
Warning (275043): Pin "VGA_R[3..0]" is missing source
Warning (275009): Pin "PS2_MSDAT" not connected
Warning (275009): Pin "PS2_MSCLK" not connected
Warning (275009): Pin "CLOCK_50" not connected
Warning (275009): Pin "CLOCK_50_2" not connected
Warning (275009): Pin "BUTTON" not connected
Warning (275009): Pin "SW" not connected
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "VGA_CLK" is stuck at GND
Warning (13410): Pin "VGA_SYNC" is stuck at GND
Warning (13410): Pin "VGA_BLANK" is stuck at GND
Warning (13410): Pin "VGA_VS" is stuck at GND
Warning (13410): Pin "VGA_HS" is stuck at GND
Warning (13410): Pin "HEX0_D[6]" is stuck at GND
Warning (13410): Pin "HEX0_D[5]" is stuck at GND
Warning (13410): Pin "HEX0_D[4]" is stuck at GND
Warning (13410): Pin "HEX0_D[3]" is stuck at GND
Warning (13410): Pin "HEX0_D[2]" is stuck at GND
Warning (13410): Pin "HEX0_D[1]" is stuck at GND
Warning (13410): Pin "HEX0_D[0]" is stuck at GND
Warning (13410): Pin "LEDG[9]" is stuck at GND
Warning (13410): Pin "LEDG[8]" is stuck at GND
Warning (13410): Pin "LEDG[7]" is stuck at GND
Warning (13410): Pin "LEDG[6]" is stuck at GND
Warning (13410): Pin "LEDG[5]" is stuck at GND
Warning (13410): Pin "LEDG[4]" is stuck at GND
Warning (13410): Pin "LEDG[3]" is stuck at GND
Warning (13410): Pin "LEDG[2]" is stuck at GND
Warning (13410): Pin "LEDG[1]" is stuck at GND
Warning (13410): Pin "LEDG[0]" is stuck at GND
Warning (13410): Pin "VGA_B[3]" is stuck at GND
Warning (13410): Pin "VGA_B[2]" is stuck at GND
Warning (13410): Pin "VGA_B[1]" is stuck at GND
Warning (13410): Pin "VGA_B[0]" is stuck at GND
Warning (13410): Pin "VGA_G[3]" is stuck at GND
Warning (13410): Pin "VGA_G[2]" is stuck at GND
Warning (13410): Pin "VGA_G[1]" is stuck at GND
Warning (13410): Pin "VGA_G[0]" is stuck at GND
Warning (13410): Pin "VGA_R[3]" is stuck at GND
Warning (13410): Pin "VGA_R[2]" is stuck at GND
Warning (13410): Pin "VGA_R[1]" is stuck at GND
Warning (13410): Pin "VGA_R[0]" is stuck at GND
Warning (20013): Ignored assignments for entity "DE0_TOP" -- entity does not exist in design
Warning (20014): Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_TOP -section_id "Root Region" was ignored
Warning (20014): Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_TOP -section_id "Root Region" was ignored
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_TOP -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_TOP -section_id Top was ignored
Warning (20013): Ignored assignments for entity "DE0_VGA" -- entity does not exist in design
Warning (20014): Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_VGA -section_id "Root Region" was ignored
Warning (20014): Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_VGA -section_id "Root Region" was ignored
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_VGA -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_VGA -section_id Top was ignored
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 17 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "PS2_MSDAT"
Warning (15610): No output dependent on input pin "PS2_MSCLK"
Warning (15610): No output dependent on input pin "CLOCK_50"
Warning (15610): No output dependent on input pin "CLOCK_50_2"
Warning (15610): No output dependent on input pin "BUTTON[2]"
Warning (15610): No output dependent on input pin "BUTTON[1]"
Warning (15610): No output dependent on input pin "BUTTON[0]"
Warning (15610): No output dependent on input pin "SW[9]"
Warning (15610): No output dependent on input pin "SW[8]"
Warning (15610): No output dependent on input pin "SW[7]"
Warning (15610): No output dependent on input pin "SW[6]"
Warning (15610): No output dependent on input pin "SW[5]"
Warning (15610): No output dependent on input pin "SW[4]"
Warning (15610): No output dependent on input pin "SW[3]"
Warning (15610): No output dependent on input pin "SW[2]"
Warning (15610): No output dependent on input pin "SW[1]"
Warning (15610): No output dependent on input pin "SW[0]"
Info (21057): Implemented 51 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 17 input pins
Info (21059): Implemented 34 output pins
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 120 warnings
Info: Peak virtual memory: 448 megabytes
Info: Processing ended: Tue Mar 01 16:05:05 2016
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
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