Adding ARM Assembly files

20 files changed, 1859 insertions, 0 deletions

diff --git a/ARM_assembly/CT4TA.s b/ARM_assembly/CT4TA.s
new file mode 100644
index 0000000..264d2f3
--- /dev/null
+++ b/ARM_assembly/CT4TA.s
@@ -0,0 +1,6 @@
+		MOV		R2, #0
+		ADDS		R3, R1, R1
+		MOVVS	R2, #1
+		MOV		R0, R1, LSL #30
+		ADDS		R1, R3, R1, ASR #2
+		MOVVS	R2, #1
diff --git a/ARM_assembly/CT7TA.s b/ARM_assembly/CT7TA.s
new file mode 100644
index 0000000..5522782
--- /dev/null
+++ b/ARM_assembly/CT7TA.s
@@ -0,0 +1,67 @@
+MSORT	STMED	R13!, {R4-R7, LR}
+		SUB		R3, R1, R0
+		CMP		R3, #4
+		LDMEDLS	R13!, {R4-R7, PC}
+		
+		MOV		R3, R3, LSR #3
+		MOV		R3, R3, LSL #2
+		ADD		R3, R3, R0
+		
+		MOV		R4, R0
+		MOV		R5, R1
+		MOV		R6, R3
+		MOV		R7, R2
+		
+		MOV		R1, R6
+		
+		BL		MSORT
+		
+		MOV		R2, R7
+		MOV		R1, R5
+		MOV		R0, R6
+		
+		BL		MSORT
+		
+		MOV		R0, R4
+		MOV		R1, R6
+		MOV		R2, R5
+		MOV		R3, R7
+		BL		MERGE
+		LDMED	R13!, {R4-R7, PC}
+		
+MERGE
+		STMED	R13!, {R4-R7, R14}
+		MOV		R4, R3
+		MOV		R5, R3
+		MOV		R3, R2
+		MOV		R2, R1
+		
+MLOOP	CMP		R0, R1
+		LDRHS	R7, [R2]
+		BHS		M2SEL
+		CMP		R2, R3
+		LDRHS	R6, [R0]
+		BHS		M1SEL
+		LDR		R6, [R0]
+		LDR		R7, [R2]
+		CMP		R6, R7
+		BLO		M1SEL
+		
+M2SEL	ADDHS	R2, R2, #4
+		STRHS	R7, [R5],#4
+		
+MEND		CMP		R0, R1
+		CMPEQ	R2, R3
+		BNE		MLOOP
+		
+CLOOP	LDR		R6, [R5, #-4]!
+		STR		R6, [R2, #-4]!
+		CMP		R4, R5
+		BNE		CLOOP
+		MOV		R0, R2
+		MOV		R1, R3
+		LDMED	R13!, {R4-R7, PC}
+		
+M1SEL	ADD		R0, R0, #4
+		STR		R6, [R5],#4
+		B		MEND
diff --git a/ARM_assembly/MultProject/CCode.c b/ARM_assembly/MultProject/CCode.c
new file mode 100644
index 0000000..3657c68
--- /dev/null
+++ b/ARM_assembly/MultProject/CCode.c
@@ -0,0 +1,27 @@
+#include <stdio.h>
+
+void SMULT64X64(num0, num1, result0, result1) {
+
+	previousBit = 0;
+	result0 = num0;
+
+	for(int i = 0; i < 64; i++) {
+		currentBit = num0 & 1;
+
+		if(currentBit == 0 && previousBit == 1) {
+			result1 += num1;
+		} else if(currentBit == 1 && previousBit == 0) {
+			result1 -= num1;
+		}
+
+		result1 >> 1;
+		result0 >rrc> 1;
+		previousBit = currentBit;
+	}
+	printf("%d %d", result1, result0);
+}
+
+int main() {
+	SMULT64X64(2, 3, 0, 0);
+	return 0;
+}
diff --git a/ARM_assembly/MultProject/Mult32x32.s b/ARM_assembly/MultProject/Mult32x32.s
new file mode 100644
index 0000000..03a06ca
--- /dev/null
+++ b/ARM_assembly/MultProject/Mult32x32.s
@@ -0,0 +1,23 @@
+		;INITIALISATION
+		
+		MOV		R0, #12
+		MOV		R1, #4
+		MOV		R2, R0
+		MOV		R3, #0
+		MOV		R5, #0
+		MOV		R6, #32
+		
+		;CODE
+		
+MULT		AND		R4, R2, #1 ;movs LSB
+		
+		CMP		R4, R5 ;Compares current and prev bit
+		ADDLO	R3, R3, R1 ;adds if 0 1
+		SUBHI	R3, R3, R1 ;sub if 1 0
+		MOV		R5, R4
+		
+		MOVS		R3, R3, ASR #1
+		MOV		R2, R2, RRX
+		
+		SUBS		R6, R6, #1
+		BNE		MULT
diff --git a/ARM_assembly/MultProject/README.txt b/ARM_assembly/MultProject/README.txt
new file mode 100644
index 0000000..906697b
--- /dev/null
+++ b/ARM_assembly/MultProject/README.txt
@@ -0,0 +1,21 @@
+testbench-opt1.s

+

+Testbench for opt1 code with test data. 

+To test your code:

+(1) Paste your solution (subroutine SMUL64X64) into VisUAL after the testbench code. 

+(2) Run the code.

+(3) On successful termination of all tests R0 = 123

+

+Otherwise:

+R0 = -1 (data out error in one of the tests, R5 contains test number)

+R0 = -2 (your code works OK but changes R4-R12 which is not allowed)

+

+If your code fully passes this testbench it will fully pass my "correctness" mark. In this case you pass the pseudo-code mark as well and obtain at least 50% for the project mark.

+

+If your code partially passes this testbench (e.g. it stops at negative numbers) you will still get some part of the code mark. In this case your pseudo-code description will be separately marked.

+

+

+

+test64x64.py (NOT NEEDED FOR NORMAL TESTING)

+Python script (runs under Python 2.7) in case you want to generate NEW test data for the testbench. Will not normally be needed.

+

diff --git a/ARM_assembly/MultProject/SudoCode.txt b/ARM_assembly/MultProject/SudoCode.txt
new file mode 100644
index 0000000..a4dc6ad
--- /dev/null
+++ b/ARM_assembly/MultProject/SudoCode.txt
@@ -0,0 +1,22 @@
+Sudo code for SMULT64X64:
+
+let result be split into result0 and result1 where they correspond to the 64 LSBs and MSBs of result respectively.
+
+void SMULT64X64(num0, num1, result) {
+
+	previousBit = 0;
+	result0 = num0;
+
+	for(int i = 0; i < 64; i++) {
+		currentBit = num0 & 1;
+
+		if(currentBit == 0 && previousBit == 1) {
+			result1 += num1;
+		} else if(currentBit == 1 && previousBit == 0) {
+			result1 -= num1;
+		}
+
+		result = result >> 1;
+		previousBit = currentBit;
+	}
+}
diff --git a/ARM_assembly/MultProject/opt1-code-ymh15.s b/ARM_assembly/MultProject/opt1-code-ymh15.s
new file mode 100644
index 0000000..e55df5d
--- /dev/null
+++ b/ARM_assembly/MultProject/opt1-code-ymh15.s
@@ -0,0 +1,920 @@
+INA		DCD		0x4, 0x0
+INB		DCD		-2, -1
+OUT		FILL		4*4
+		
+		LDR		R0, =INA
+		LDR		R1, =INB
+		LDR		R2, =OUT
+		BL		SMUL64X64
+		END
+		
+SMUL64X64	STMED	R13!, {R0, R1, R4-R12, LR}
+		LDR		R3, [R0]
+		LDR		R4, [R0, #4]
+		LDR		R7, [R1]
+		LDR		R8, [R1, #4]
+		MOV		R5, #0
+		MOV		R6, #0
+		MVN		R1, R7
+		ADDS		R1, R1, #1
+		MVN		R11, R8
+		ADC		R11, R11, #0
+		MOV		R10, #0
+		AND		R9, R3, #1 ;1
+		CMP		R9, R10
+		BEQ		CONT1
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT1	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;2
+		CMP		R9, R10
+		BEQ		CONT2
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT2	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;3
+		CMP		R9, R10
+		BEQ		CONT3
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT3	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;4
+		CMP		R9, R10
+		BEQ		CONT4
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT4	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;5
+		CMP		R9, R10
+		BEQ		CONT5
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT5	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;6
+		CMP		R9, R10
+		BEQ		CONT6
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT6	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;7
+		CMP		R9, R10
+		BEQ		CONT7
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT7	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;8
+		CMP		R9, R10
+		BEQ		CONT8
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT8	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;9
+		CMP		R9, R10
+		BEQ		CONT9
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT9	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;10
+		CMP		R9, R10
+		BEQ		CONT10
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT10	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;11
+		CMP		R9, R10
+		BEQ		CONT11
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT11	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;12
+		CMP		R9, R10
+		BEQ		CONT12
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT12	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;13
+		CMP		R9, R10
+		BEQ		CONT13
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT13	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;14
+		CMP		R9, R10
+		BEQ		CONT14
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT14	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;15
+		CMP		R9, R10
+		BEQ		CONT15
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT15	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;16
+		CMP		R9, R10
+		BEQ		CONT16
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT16	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;17
+		CMP		R9, R10
+		BEQ		CONT17
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT17	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;18
+		CMP		R9, R10
+		BEQ		CONT18
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT18	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;19
+		CMP		R9, R10
+		BEQ		CONT19
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT19	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;20
+		CMP		R9, R10
+		BEQ		CONT20
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT20	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;21
+		CMP		R9, R10
+		BEQ		CONT21
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT21	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;22
+		CMP		R9, R10
+		BEQ		CONT22
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT22	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;23
+		CMP		R9, R10
+		BEQ		CONT23
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT23	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;24
+		CMP		R9, R10
+		BEQ		CONT24
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT24	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;25
+		CMP		R9, R10
+		BEQ		CONT25
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT25	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;26
+		CMP		R9, R10
+		BEQ		CONT26
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT26	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;27
+		CMP		R9, R10
+		BEQ		CONT27
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT27	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;28
+		CMP		R9, R10
+		BEQ		CONT28
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT28	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;29
+		CMP		R9, R10
+		BEQ		CONT29
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT29	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;30
+		CMP		R9, R10
+		BEQ		CONT30
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT30	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;31
+		CMP		R9, R10
+		BEQ		CONT31
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT31	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;32
+		CMP		R9, R10
+		BEQ		CONT32
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT32	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;33
+		CMP		R9, R10
+		BEQ		CONT33
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT33	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;34
+		CMP		R9, R10
+		BEQ		CONT34
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT34	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;35
+		CMP		R9, R10
+		BEQ		CONT35
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT35	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;36
+		CMP		R9, R10
+		BEQ		CONT36
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT36	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;37
+		CMP		R9, R10
+		BEQ		CONT37
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT37	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;38
+		CMP		R9, R10
+		BEQ		CONT38
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT38	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;39
+		CMP		R9, R10
+		BEQ		CONT39
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT39	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;40
+		CMP		R9, R10
+		BEQ		CONT40
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT40	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;41
+		CMP		R9, R10
+		BEQ		CONT41
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT41	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;42
+		CMP		R9, R10
+		BEQ		CONT42
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT42	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;43
+		CMP		R9, R10
+		BEQ		CONT43
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT43	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;44
+		CMP		R9, R10
+		BEQ		CONT44
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT44	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;45
+		CMP		R9, R10
+		BEQ		CONT45
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT45	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;46
+		CMP		R9, R10
+		BEQ		CONT46
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT46	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;47
+		CMP		R9, R10
+		BEQ		CONT47
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT47	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;48
+		CMP		R9, R10
+		BEQ		CONT48
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT48	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;49
+		CMP		R9, R10
+		BEQ		CONT49
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT49	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;50
+		CMP		R9, R10
+		BEQ		CONT50
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT50	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;51
+		CMP		R9, R10
+		BEQ		CONT51
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT51	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;52
+		CMP		R9, R10
+		BEQ		CONT52
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT52	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;53
+		CMP		R9, R10
+		BEQ		CONT53
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT53	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;54
+		CMP		R9, R10
+		BEQ		CONT54
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT54	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;55
+		CMP		R9, R10
+		BEQ		CONT55
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT55	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;56
+		CMP		R9, R10
+		BEQ		CONT56
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT56	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;57
+		CMP		R9, R10
+		BEQ		CONT57
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT57	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;58
+		CMP		R9, R10
+		BEQ		CONT58
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT58	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;59
+		CMP		R9, R10
+		BEQ		CONT59
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT59	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;60
+		CMP		R9, R10
+		BEQ		CONT60
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT60	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;61
+		CMP		R9, R10
+		BEQ		CONT61
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT61	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;62
+		CMP		R9, R10
+		BEQ		CONT62
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT62	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;63
+		CMP		R9, R10
+		BEQ		CONT63
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT63	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;64
+		CMP		R9, R10
+		BEQ		CONT64
+		MOVHI	R0, R1
+		MOVHI	R12, R11
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT64	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		STMIA	R2, {R3-R6}
+		LDMED	R13!, {R0, R1, R4-R12, PC}
diff --git a/ARM_assembly/MultProject/opt1-doc-ymh15 b/ARM_assembly/MultProject/opt1-doc-ymh15
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/ARM_assembly/MultProject/opt1-doc-ymh15
diff --git a/ARM_assembly/MultProject/opt1-doc-ymh15.desktop b/ARM_assembly/MultProject/opt1-doc-ymh15.desktop
new file mode 100755
index 0000000..567b399
--- /dev/null
+++ b/ARM_assembly/MultProject/opt1-doc-ymh15.desktop
@@ -0,0 +1,5 @@
+[Desktop Entry]
+Icon=application-vnd.google-apps.document
+Name=opt1-doc-ymh15
+Type=Link
+URL=https://docs.google.com/document/d/1dkUvhujhrCIKXQKKnY9NqCAqWs-bDfJtq4I8S1WELAQ/edit?usp=drivesdk
diff --git a/ARM_assembly/MultProject/test.s b/ARM_assembly/MultProject/test.s
new file mode 100644
index 0000000..fec5a93
--- /dev/null
+++ b/ARM_assembly/MultProject/test.s
@@ -0,0 +1,172 @@
+		LDR		R0, =INA
+		LDR		R1, =INB
+		LDR		R2, =OUTAxB
+		BL		SMUL64X64
+		END
+		
+INA		DCD		0x33333333,0x33
+INB		DCD		0x44444444,0x44
+OUTAxB	FILL		4*4
+		;		OUTAxB7		DCD		0XFE3F09B0,0X2829D69,0X913A81B,0X20BD7902
+		
+SMUL64X64	STMED	R13!, {R0, R4-R12, LR}
+		LDR		R3, [R0]
+		LDR		R4, [R0, #4]
+		LDR		R7, [R1]
+		LDR		R8, [R1, #4]
+		MOV		R10, #0
+		MOV		R11, #7
+		AND		R9, R3, #1 ;1
+		CMP		R9, R10
+		BEQ		CONT1
+		MVNHI	R0, R7
+		ADDHI	R0, R0, #1
+		MVNHI	R12, R8
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT1	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+MULT		AND		R9, R3, #1 ;2
+		CMP		R9, R10
+		BEQ		CONT2
+		MVNHI	R0, R7
+		ADDHI	R0, R0, #1
+		MVNHI	R12, R8
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT2	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;3
+		CMP		R9, R10
+		BEQ		CONT3
+		MVNHI	R0, R7
+		ADDHI	R0, R0, #1
+		MVNHI	R12, R8
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT3	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;4
+		CMP		R9, R10
+		BEQ		CONT4
+		MVNHI	R0, R7
+		ADDHI	R0, R0, #1
+		MVNHI	R12, R8
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT4	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;5
+		CMP		R9, R10
+		BEQ		CONT5
+		MVNHI	R0, R7
+		ADDHI	R0, R0, #1
+		MVNHI	R12, R8
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT5	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;6
+		CMP		R9, R10
+		BEQ		CONT6
+		MVNHI	R0, R7
+		ADDHI	R0, R0, #1
+		MVNHI	R12, R8
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT6	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;7
+		CMP		R9, R10
+		BEQ		CONT7
+		MVNHI	R0, R7
+		ADDHI	R0, R0, #1
+		MVNHI	R12, R8
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT7	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;8
+		CMP		R9, R10
+		BEQ		CONT8
+		MVNHI	R0, R7
+		ADDHI	R0, R0, #1
+		MVNHI	R12, R8
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT8	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;9
+		CMP		R9, R10
+		BEQ		CONT9
+		MVNHI	R0, R7
+		ADDHI	R0, R0, #1
+		MVNHI	R12, R8
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT9	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;10
+		CMP		R9, R10
+		BEQ		CONT10
+		MVNHI	R0, R7
+		ADDHI	R0, R0, #1
+		MVNHI	R12, R8
+		MOVLO	R0, R7
+		MOVLO	R12, R8
+		ADDS		R5, R5, R0
+		ADC		R6, R6, R12
+CONT10	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		SUBS		R11, R11, #1
+		BNE		MULT
+		STMIA	R2, {R3-R6}
+		LDMED	R13!, {R0, R4-R12, PC}
diff --git a/ARM_assembly/MultProject/test2.s b/ARM_assembly/MultProject/test2.s
new file mode 100644
index 0000000..8cdd69a
--- /dev/null
+++ b/ARM_assembly/MultProject/test2.s
@@ -0,0 +1,174 @@
+AIN		DCD		0X7FFFFFFF,0X0
+BIN		DCD		0X7FFFFFFF,0X0
+		;		DCD		0X1,0X3FFFFFFF,0X0,0X0
+OUT		FILL		4*4
+		
+		LDR		R0, =AIN
+		LDR		R1, =BIN
+		LDR		R2, =OUT
+		BL		SMUL64X64
+		END
+		
+SMUL64X64	STMED	R13!, {R4-R12, LR}
+		LDR		R3, [R0]
+		LDR		R4, [R0, #4]
+		MOV		R5, #0
+		MOV		R6, #0
+		LDR		R7, [R1]
+		LDR		R8, [R1, #4]
+		MOV		R10, #0
+		MOV		R11, #7
+		AND		R9, R3, #1 ;1
+		CMP		R9, R10
+		BHI		SU1
+		BLO		AD1
+		B		CONT1
+SU1		SUBS		R5, R5, R7
+		SBC		R6, R6, R8
+		B		CONT1
+AD1		ADDS		R5, R5, R7
+		ADC		R6, R6, R8
+CONT1	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+MULT		AND		R9, R3, #1 ;2
+		CMP		R9, R10
+		BHI		SU2
+		BLO		AD2
+		B		CONT2
+SU2		SUBS		R5, R5, R7
+		SBC		R6, R6, R8
+		B		CONT2
+AD2		ADDS		R5, R5, R7
+		ADC		R6, R6, R8
+CONT2	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;3
+		CMP		R9, R10
+		BHI		SU3
+		BLO		AD3
+		B		CONT3
+SU3		SUBS		R5, R5, R7
+		SBC		R6, R6, R8
+		B		CONT3
+AD3		ADDS		R5, R5, R7
+		ADC		R6, R6, R8
+CONT3	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;4
+		CMP		R9, R10
+		BHI		SU4
+		BLO		AD4
+		B		CONT4
+SU4		SUBS		R5, R5, R7
+		SBC		R6, R6, R8
+		B		CONT4
+AD4		ADDS		R5, R5, R7
+		ADC		R6, R6, R8
+CONT4	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;5
+		CMP		R9, R10
+		BHI		SU5
+		BLO		AD5
+		B		CONT5
+SU5		SUBS		R5, R5, R7
+		SBC		R6, R6, R8
+		B		CONT5
+AD5		ADDS		R5, R5, R7
+		ADC		R6, R6, R8
+CONT5	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;6
+		CMP		R9, R10
+		BHI		SU6
+		BLO		AD6
+		B		CONT6
+SU6		SUBS		R5, R5, R7
+		SBC		R6, R6, R8
+		B		CONT6
+AD6		ADDS		R5, R5, R7
+		ADC		R6, R6, R8
+CONT6	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;7
+		CMP		R9, R10
+		BHI		SU7
+		BLO		AD7
+		B		CONT7
+SU7		SUBS		R5, R5, R7
+		SBC		R6, R6, R8
+		B		CONT7
+AD7		ADDS		R5, R5, R7
+		ADC		R6, R6, R8
+CONT7	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;8
+		CMP		R9, R10
+		BHI		SU8
+		BLO		AD8
+		B		CONT8
+SU8		SUBS		R5, R5, R7
+		SBC		R6, R6, R8
+		B		CONT8
+AD8		ADDS		R5, R5, R7
+		ADC		R6, R6, R8
+CONT8	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;9
+		CMP		R9, R10
+		BHI		SU9
+		BLO		AD9
+		B		CONT9
+SU9		SUBS		R5, R5, R7
+		SBC		R6, R6, R8
+		B		CONT9
+AD9		ADDS		R5, R5, R7
+		ADC		R6, R6, R8
+CONT9	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		AND		R9, R3, #1 ;10
+		CMP		R9, R10
+		BHI		SU10
+		BLO		AD10
+		B		CONT10
+SU10		SUBS		R5, R5, R7
+		SBC		R6, R6, R8
+		B		CONT10
+AD10		ADDS		R5, R5, R7
+		ADC		R6, R6, R8
+CONT10	MOVS		R6, R6, ASR #1
+		MOVS		R5, R5, RRX
+		MOVS		R4, R4, RRX
+		MOVS		R3, R3, RRX
+		MOV		R10, R9
+		SUBS		R11, R11, #1
+		BNE		MULT
+		STMIA	R2, {R3-R6}
+		LDMED	R13!, {R4-R12, PC}
diff --git a/ARM_assembly/MultProject/test64x64.py b/ARM_assembly/MultProject/test64x64.py
new file mode 100644
index 0000000..86d02dd
--- /dev/null
+++ b/ARM_assembly/MultProject/test64x64.py
@@ -0,0 +1,65 @@
+#-------------------------------------------------------------------------------

+# Name:        module1

+# Purpose:

+#

+# Author:      tomcl

+#

+# Created:     11/12/2015

+# Copyright:   (c) tomcl 2015

+# Licence:     <your licence>

+#-------------------------------------------------------------------------------

+

+import random

+

+def rand64():

+    bits = random.getrandbits(64) # 64 random bits, us unsigned

+    if bits >= (1<<63):   # convert from unsigned to signed representation

+        return bits - (1<<64)

+    else:

+        return bits

+

+def twosComp(x,width=128): # comvert from signed int to two's comp representation

+                           # choose large default width, when extracting lower bits

+                           # too large a value of width does not matter

+    if x < 0:

+        return (1 << width) + x

+    else:

+        return x

+

+def pw(x):

+    return "0X%X" % (x % (1<<32))

+

+def pw0(x):

+    return pw(twosComp(x))

+

+def pw1(x):

+    return pw (twosComp(x) >> 32)

+

+def pw2(x):

+    return pw (twosComp(x) >> 64)

+

+def pw3(x):

+    return pw (twosComp(x) >> 96)

+

+def makeData(name, num, dat, s=""):

+    return ("%s%s%d DCD %s\n"% (("\n ; " + s + "\n" if s else ""), name, num, ",".join(dat)))

+

+def genTest(num, a,b, s):

+    p = a*b # this is the correct 128 bit product of a and b

+    s = makeData("INA",num, [pw0(a), pw1(a)], s)

+    s += makeData("INB", num, [pw0(b),pw1(b)])

+    s += makeData("OUTAxB", num, [pw0(p),pw1(p),pw2(p),pw3(p)])

+    return s

+

+def makeTestData():

+    s = genTest(0, 0x200000030, 0x50000007000, "Test 0: simple diagnostic")

+    s += genTest(1,0x7FFFFFFF, 0x7FFFFFFF, "Test 1: carries" )

+    s += genTest(2, 0, 0, "Test 2: all zeros")

+    s += genTest(3, -1, -1, "Test 3: both negative")

+    s += genTest(4, -1, 1, "Test 4: A negative")

+    s += genTest(5, 1, -1, "Test 5: B negative")

+    s += genTest(6, rand64(), rand64(), "Test 6: Random bits")

+    s += genTest(7, rand64(), rand64(), "Test 7: Random bits")

+    return s

+

+print makeTestData()

diff --git a/ARM_assembly/MultProject/testbench-opt1.s b/ARM_assembly/MultProject/testbench-opt1.s
new file mode 100644
index 0000000..6940a78
--- /dev/null
+++ b/ARM_assembly/MultProject/testbench-opt1.s
@@ -0,0 +1,140 @@
+				;		Test 0: simple diagnostic
+INA0				DCD		0X30,0X2
+INB0				DCD		0X7000,0X500
+OUTAxB0			DCD		0X150000,0X1D000,0XA00,0X0
+				
+				;		Test 1: carries
+INA1				DCD		0X7FFFFFFF,0X0
+INB1				DCD		0X7FFFFFFF,0X0
+OUTAxB1			DCD		0X1,0X3FFFFFFF,0X0,0X0
+				
+				;		Test 2: all zeros
+INA2				DCD		0X0,0X0
+INB2				DCD		0X0,0X0
+OUTAxB2			DCD		0X0,0X0,0X0,0X0
+				
+				;		Test 3: both negative
+INA3				DCD		0XFFFFFFFF,0XFFFFFFFF
+INB3				DCD		0XFFFFFFFF,0XFFFFFFFF
+OUTAxB3			DCD		0X1,0X0,0X0,0X0
+				
+				;		Test 4: A negative
+INA4				DCD		0XFFFFFFFF,0XFFFFFFFF
+INB4				DCD		0X1,0X0
+OUTAxB4			DCD		0XFFFFFFFF,0XFFFFFFFF,0XFFFFFFFF,0XFFFFFFFF
+				
+				;		Test 5: B negative
+INA5				DCD		0X1,0X0
+INB5				DCD		0XFFFFFFFF,0XFFFFFFFF
+OUTAxB5			DCD		0XFFFFFFFF,0XFFFFFFFF,0XFFFFFFFF,0XFFFFFFFF
+				
+				;		Test 6: Random bits
+INA6				DCD		0X802A5B62,0XE705271E
+INB6				DCD		0XB7353E54,0X2E4456B5
+OUTAxB6			DCD		0X4951B828,0XAEC6916E,0XDF0A0C3D,0XFB7C41EF
+				
+				;		Test 7: Random bits
+INA7				DCD		0X73F1A0B6,0X9B6FDBB8
+INB7				DCD		0X3D1AA608,0XACA790C3
+OUTAxB7			DCD		0XFE3F09B0,0X2829D69,0X913A81B,0X20BD7902
+OUTVEC			FILL		4*4
+REGVEC			FILL		8*4
+STACKSAVE			FILL		4
+IN_TEMP			FILL		4*4
+				
+				;
+LAST_TEST			EQU		7
+				MOV		R5, #0 ; test number
+				;		Loop to test code with different data
+TLOOP
+				BL		DODATATEST
+				ADD		R5, R5, #1
+				CMP		R5, #LAST_TEST
+				BLE		TLOOP
+				;
+				;
+SUCCESS			MOV		R0, #123  ; 123 (0x7B) in R0 indicates successful completion of all tests
+				END
+				
+				
+DODATATEST		STMED	R13!, {R12,R14}
+				LDR		R12, =INA0
+				ADD		R12, R12, R5, LSL #5 ; get offset to correct data
+				MOV		R0, R12 ; pointer to INA & INB
+				LDR		R1, =IN_TEMP
+				BL		COPY4W
+				MOV		R0, R1      ; now R0 points to INA and INB copy
+				ADD		R1, R0, #2*4 ; pointer to INB copy
+				LDR		R2, =OUTVEC
+				BL		SMUL_SHIELD
+				ADD		R0, R12, #4*4 ; pointer to correct output
+				LDR		R1, =OUTVEC ; pointer to actual 128 bit output
+				MOV		R2, #4 ; length of vectors in words
+				BL		VECTOREQ ; sets EQ cond if the two vectors are equal
+				LDMEDEQ	R13!, {R12,PC} ; return
+				;
+DATA_ERROR
+				MOV		R0, #-1
+				;		we get here if we have found an error in the test
+				;		R5 is the number of the test that failed
+				;		R0 = -1 as error indication
+				END
+				
+				
+SMUL_SHIELD         ;         protect testbench registers ans stack from rogue SMUL behaviour
+				;		check whether SMUL changes R4-R12
+				STMED	R13!, {R4-R12, R14} ; save
+				LDR		R3, =STACKSAVE
+				STR		R13, [R3] ; save SP in case this gets corrupted
+				LDR		R12, =INA6 ; the next 16 words of data are random
+				AND		R3, R5, #1 ; extract LS bit of R5 which will change from test to test
+				ADD		R12, R12, R3, LSL #2  ; add it onto R3 to make data in registers vary
+				LDMIA	R12, {R4-R11}
+				BL		SMUL64X64
+				LDR		R0, =REGVEC
+				STMIA	R0, {R4-R11}
+				MOV		R1, R12
+				MOV		R2, #8
+				BL		VECTOREQ
+				BNE		REG_ERROR
+				LDR		R3, =STACKSAVE
+				LDR		R3, [R3]
+				MOV		R0, R13
+				CMP		R3, R0
+				LDMEDEQ	R13!, {R4-R12,R15} ; restore and return if no stack error
+				
+				
+STACK_ERROR         ;        We get here if SMUL64X64 does not correctly restore the SP to its
+				;		old value on exit (for example by using different push and pop register sets)
+				MOV		R0, #-3
+				LDMED	R13!, {R4-R12}
+				END
+				
+				
+				
+				
+REG_ERROR			;         we get here if the test code changes registers R4-R12, which is not allowed
+				MOV		R0, #-2
+				LDMED	R13!, {R4-R12}
+				END
+				
+				
+				;		return EQ if vectors of R2 words with LSWs at addresses R0 and R1 are equal
+VECTOREQ		STMED	R13!, {R0,R1,R2,R4,R5,R14}
+VLOOP			LDR		R5, [R0], #4
+				LDR		R4, [R1], #4
+				CMP		R5, R4
+				LDMEDNE	R13!, {R0, R1,R2,R4,R5,PC} ; return with NE if the vectors do not match
+				SUBS		R2, R2, #1
+				BNE		VLOOP
+				LDMED	R13!, {R0,R1,R2,R4,R5,PC} ; return with EQ if vectors match
+				
+				
+				;		copy vector of 4 words from address R0 to address R1
+COPY4W			STMED	R13!, {R4-R7,R14}
+				LDMIA	R0, {R4-R7}
+				STMIA	R1, {R4-R7}
+				LDMED	R13!, {R4-R7, PC}
+				
+				
+				;;		add your SMUL64X64 code from here onwards
diff --git a/ARM_assembly/MultProject/testbench-opt1.zip b/ARM_assembly/MultProject/testbench-opt1.zip
new file mode 100644
index 0000000..c75a51e
--- /dev/null
+++ b/ARM_assembly/MultProject/testbench-opt1.zip
diff --git a/ARM_assembly/ct2.s b/ARM_assembly/ct2.s
new file mode 100644
index 0000000..7abc20f
--- /dev/null
+++ b/ARM_assembly/ct2.s
@@ -0,0 +1,10 @@
+		MOV		R0, #3
+		MOV		R1, #5
+		MOV R2, R0
+		MOV R0, R1
+		ADD		R1, R1, R1
+		ADD		R1, R1, R1
+		SUB		R1, R2, R1
+		ADD		R1, R1, R2
+		ADD		R1, R1, R2
+		RSB		R2, R0, #11
diff --git a/ARM_assembly/ct2shorter.s b/ARM_assembly/ct2shorter.s
new file mode 100644
index 0000000..8f44bde
--- /dev/null
+++ b/ARM_assembly/ct2shorter.s
@@ -0,0 +1,7 @@
+MOV		R2, R0
+MOV		R0, R1
+ADD		R1, R1, R1
+SUB		R1, R2, R1
+ADD		R1, R1, R1
+ADD		R1, R2, R1
+RSB		R2, R2, #11
\ No newline at end of file
diff --git a/ARM_assembly/ct3.s b/ARM_assembly/ct3.s
new file mode 100644
index 0000000..d1d6d29
--- /dev/null
+++ b/ARM_assembly/ct3.s
@@ -0,0 +1,14 @@
+		CMP		R1, #1
+		BEQ		LOOP3
+		MOV		R2, R1
+LOOP1	SUB		R2, R2, #2
+		MOV		R3, R2
+		MOV		R0, #0
+LOOP2	ADD		R0, R0, R1
+		SUB		R3, R3, #1
+		CMP		R3, #0
+		BNE		LOOP2
+		MOV		R1, R0
+		CMP		R2, #1
+		BNE		LOOP1
+LOOP3	MOV		R0, R1
diff --git a/ARM_assembly/ct4.s b/ARM_assembly/ct4.s
new file mode 100644
index 0000000..16f1612
--- /dev/null
+++ b/ARM_assembly/ct4.s
@@ -0,0 +1,155 @@
+		;4.1
+		
+		;		MOV		R0, #0xFFFFFFFF
+		;		MOV		R1, #0xFFFFFFFF
+		;		MOV		R2, #0x0000008B
+		;
+		;		ADDS		R0, R0, #1
+		;		BCS		CARRY1
+		;		B		EXIT
+		;CARRY1	ADCS		R1, R1, #0
+		;		BCS		CARRY2
+		;		B		EXIT
+		;CARRY2	ADC		R2, R2, #0
+		;EXIT
+		
+		;4.2
+		
+		;		MOV		R0, #0x00000000
+		;		MOV		R1, #0x00000000
+		;		MOV		R2, #0x0000008B
+		;
+		;		SUBS		R0, R0, #1
+		;		BCC		NCAR1
+		;		B		EXIT
+		;NCAR1	SBCS		R1, R1, #0
+		;		BCC		NCAR2
+		;		B		EXIT
+		;NCAR2	SBC		R2, R2, #0
+		;
+		;EXIT
+		
+		;4.3
+		
+		;MOV		R2, #0xFFFFFFFF
+		;MOV		R3, R2
+		;MOV		R4, R2
+		;MOV		R5, R4
+		;MOV		R11, #0xFFFFFFFF
+		;ADDS	R11, R11, #1
+		;
+		;ADDS	R0, R2, R4
+		;ADCS	R1, R3, R5
+		;MOVCS	R6, #1
+		;MOVCC	R6, #0
+		
+		;4.4
+		
+		;MOV		R0, #-254
+		;MOV		R1, #254
+		;
+		;ADDS	R2, R1, R0
+		;MOVVS	R3, #1
+		;MOVVC	R3, #0
+		;MOVCS	R4, #1
+		;MOVCC	R4, #0
+		
+		;4.5
+		
+		;		MOV		R0, #0xFFFFFFFF
+		;		MOV		R1, #0xBFFFFFFF
+		;		MOV		R2, #1
+		;		MOV		R6, #7
+		;
+		;MULT	ADDS		R3, R3, R0
+		;		ADCS		R4, R4, R1
+		;		ADCS		R5, R5, R2
+		;		SUB		R6, R6, #1
+		;		CMP		R6, #0
+		;		BNE		MULT
+		
+		;4.6
+		
+		;MOV		R0, #0xFB
+		;MOV		R0, R0, LSL #22
+		;MOVS	R1, R0, LSL #1
+		;BPL		POS
+		;
+		;MVN		R2, R0
+		;MVN		R3, R1
+		;ADD		R2, R2, #1
+		;B		EXIT
+		;POS		MOV		R2, R0
+		;MOV		R3, R1
+		;EXIT
+		
+		;4.7
+		
+		;MOV		R0, #0xFFFFFFFF
+		;MOV		R1, #0xFF
+		;
+		;MOVS	R2, R0, LSL #1
+		;MOV		R3, R1, LSL #1
+		;ADDCS	R3, R3, #1
+		
+		;4.8
+		
+		;MOV		R0, #0xFFFFFFFF
+		;MOV		R1, #0xFFFFFFFF
+		;MOV		R2, #0xFF
+		;
+		;MOVS	R5, R2, RRX
+		;MOVS	R4, R1, RRX
+		;MOVS	R3, R0, RRX
+		
+		;4.9
+		
+		;MOV		R0, #0xA8000000
+		;MOV		R1, #0
+		;MOV		R5, #5
+		;
+		;MOV		R3, R1, LSL #5
+		;MOV		R2, R0, LSL #5
+		;LOOP	MOVS		R0, R0, LSL #1
+		;MOV		R4, #0
+		;MOVCS	R4, #1
+		;SUBS	R5, R5, #1
+		;MOV		R4, R4, LSL R5
+		;ADD		R3, R4, R3
+		;BNE		LOOP
+		
+		;4.10
+		
+		;		MOV		R0, #0xA3
+		;		MOV		R2, #10
+		;		MOV		R0, R0, LSL #22
+		;LOOP	MOVS		R0, R0, LSL #1
+		;		MOVCS	R3, #1
+		;		MOVCC	R3, #0
+		;		MOV		R1, R1, LSL #1
+		;		ADD		R1, R3, R1
+		;		SUBS		R2, R2, #1
+		;		BNE		LOOP
+		
+		
+		
+		
+		
+		
+		
+		
+		
+		
+		
+		
+		
+		
+		
+		
+		
+		
+		
+		
+		
+		
+		
diff --git a/ARM_assembly/ct5.s b/ARM_assembly/ct5.s
new file mode 100644
index 0000000..6a713a8
--- /dev/null
+++ b/ARM_assembly/ct5.s
@@ -0,0 +1,5 @@
+		CMP		R0, #15
+		ADR		R1, DATA
+		LDRLS	R1, [R1, R0, LSL #2]
+		MOVHI	R1, #0
+DATA		DCD		85, 86, 89, 90, 101, 102, 105, 106, 149, 150, 153, 154, 165, 166, 169, 170
diff --git a/ARM_assembly/ct6TA.s b/ARM_assembly/ct6TA.s
new file mode 100644
index 0000000..aa6bb37
--- /dev/null
+++ b/ARM_assembly/ct6TA.s
@@ -0,0 +1,26 @@
+		ADR		R1, INWAVE
+		ADR		R2, OUTWAVE
+		ADD		R12, R1, #56
+		MOV		R0, #0
+LOOP		LDR		R3, [R1], #4
+		LDR		R4, [R1]
+		LDR		R5, [R1, #4]
+		ADDS		R3, R3, R4
+		MOVVS	R0, #1
+		ADDS		R3, R3, R5
+		MOVVS	R0, #1
+		MVNS		R4, R4
+		ADDPL	R4, R4, #1
+		MOVPL	R10, #1
+		ADDMI	R5, R5, #-1
+		MVNSMI	R5, R5
+		CMPMI	R4, R5
+		MOVS		R10, R10
+		CMPNE	R4, R5
+		MOVMI	R0, #0
+		STR		R3, [R2], #4
+		LDR		R6, [R2, #-4]
+		CMP		R1, R12
+		BNE		LOOP
+INWAVE	DCD		500,1000,500,700, 2000, 4000, 3000, 11000, 50, 300, 400, 800,750,300,100000,1000
+OUTWAVE	FILL		14*4