diff options
Diffstat (limited to 'Sobel/Sobel Quartus/db/prev_cmp_sobel.qmsg')
| -rw-r--r-- | Sobel/Sobel Quartus/db/prev_cmp_sobel.qmsg | 156 |
1 files changed, 156 insertions, 0 deletions
diff --git a/Sobel/Sobel Quartus/db/prev_cmp_sobel.qmsg b/Sobel/Sobel Quartus/db/prev_cmp_sobel.qmsg new file mode 100644 index 0000000..29e061f --- /dev/null +++ b/Sobel/Sobel Quartus/db/prev_cmp_sobel.qmsg @@ -0,0 +1,156 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1457454100457 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457454100462 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:21:39 2016 " "Processing started: Tue Mar 08 16:21:39 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457454100462 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1457454100462 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sobel -c sobel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sobel -c sobel" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1457454100462 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1457454102791 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "//icnas3.cc.ic.ac.uk/mg3115/eie1 fpga/sobel filter catapult/sobel/sobel.v12/rtl_mgc_ioport.v 20 20 " "Found 20 design units, including 20 entities, in source file //icnas3.cc.ic.ac.uk/mg3115/eie1 fpga/sobel filter catapult/sobel/sobel.v12/rtl_mgc_ioport.v" { { "Info" "ISGN_ENTITY_NAME" "1 mgc_in_wire " "Found entity 1: mgc_in_wire" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 13 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "2 mgc_in_wire_en " "Found entity 2: mgc_in_wire_en" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "3 mgc_in_wire_wait " "Found entity 3: mgc_in_wire_wait" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 49 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "4 mgc_chan_in " "Found entity 4: mgc_chan_in" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 72 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "5 mgc_out_stdreg " "Found entity 5: mgc_out_stdreg" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 109 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "6 mgc_out_stdreg_en " "Found entity 6: mgc_out_stdreg_en" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 125 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "7 mgc_out_stdreg_wait " "Found entity 7: mgc_out_stdreg_wait" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 145 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "8 mgc_out_prereg_en " "Found entity 8: mgc_out_prereg_en" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 169 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "9 mgc_inout_stdreg_en " "Found entity 9: mgc_inout_stdreg_en" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 191 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "10 hid_tribuf " "Found entity 10: hid_tribuf" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 217 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "11 mgc_inout_stdreg_wait " "Found entity 11: mgc_inout_stdreg_wait" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 229 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "12 mgc_inout_buf_wait " "Found entity 12: mgc_inout_buf_wait" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 269 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "13 mgc_inout_fifo_wait " "Found entity 13: mgc_inout_fifo_wait" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 339 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "14 mgc_io_sync " "Found entity 14: mgc_io_sync" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 419 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "15 mgc_bsync_rdy " "Found entity 15: mgc_bsync_rdy" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 428 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "16 mgc_bsync_vld " "Found entity 16: mgc_bsync_vld" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 443 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "17 mgc_bsync_rv " "Found entity 17: mgc_bsync_rv" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 458 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "18 mgc_sync " "Found entity 18: mgc_sync" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 479 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "19 funccall_inout " "Found entity 19: funccall_inout" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 498 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "20 modulario_en_in " "Found entity 20: modulario_en_in" { } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 526 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} +{ "Warning" "WSGN_SEARCH_FILE" "sobel.v 2 2 " "Using design file sobel.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sobel_core " "Found entity 1: sobel_core" { } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 16 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454106833 ""} { "Info" "ISGN_ENTITY_NAME" "2 sobel " "Found entity 2: sobel" { } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1573 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454106833 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1457454106833 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "sobel " "Elaborating entity \"sobel\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1457454106866 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire mgc_in_wire:vin_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"mgc_in_wire:vin_rsc_mgc_in_wire\"" { } { { "sobel.v" "vin_rsc_mgc_in_wire" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1593 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454107431 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_out_stdreg mgc_out_stdreg:vout_rsc_mgc_out_stdreg " "Elaborating entity \"mgc_out_stdreg\" for hierarchy \"mgc_out_stdreg:vout_rsc_mgc_out_stdreg\"" { } { { "sobel.v" "vout_rsc_mgc_out_stdreg" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1598 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454107609 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sobel_core sobel_core:sobel_core_inst " "Elaborating entity \"sobel_core\" for hierarchy \"sobel_core:sobel_core_inst\"" { } { { "sobel.v" "sobel_core_inst" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1605 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454107701 ""} +{ "Info" "ILPMS_INFERENCING_SUMMARY" "9 " "Inferred 9 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult0\"" { } { { "sobel.v" "Mult0" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult1\"" { } { { "sobel.v" "Mult1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult7 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult7\"" { } { { "sobel.v" "Mult7" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult5 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult5\"" { } { { "sobel.v" "Mult5" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult2 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult2\"" { } { { "sobel.v" "Mult2" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult3 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult3\"" { } { { "sobel.v" "Mult3" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult6 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult6\"" { } { { "sobel.v" "Mult6" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult4 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult4\"" { } { { "sobel.v" "Mult4" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult8 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult8\"" { } { { "sobel.v" "Mult8" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 784 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1457454109046 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\"" { } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109318 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 2 " "Parameter \"LPM_WIDTHA\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 9 " "Parameter \"LPM_WIDTHB\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 11 " "Parameter \"LPM_WIDTHP\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 11 " "Parameter \"LPM_WIDTHR\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454109325 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult0\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109548 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\"" { } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109693 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult0\|altshift:external_latency_ffs sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109848 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\"" { } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109920 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 3 " "Parameter \"LPM_WIDTHA\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 6 " "Parameter \"LPM_WIDTHB\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 9 " "Parameter \"LPM_WIDTHP\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 9 " "Parameter \"LPM_WIDTHR\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454109922 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult1\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109944 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult1\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\"" { } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109960 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult1\|altshift:external_latency_ffs sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109977 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\"" { } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 2 " "Parameter \"LPM_WIDTHA\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 13 " "Parameter \"LPM_WIDTHB\" = \"13\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 15 " "Parameter \"LPM_WIDTHP\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 15 " "Parameter \"LPM_WIDTHR\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 6 " "Parameter \"MAXIMIZE_SPEED\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454110056 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult7\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110090 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult7\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\"" { } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110113 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult7\|altshift:external_latency_ffs sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110133 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\"" { } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 9 " "Parameter \"LPM_WIDTHB\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 13 " "Parameter \"LPM_WIDTHP\" = \"13\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 13 " "Parameter \"LPM_WIDTHR\" = \"13\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454110207 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult5\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110255 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult5\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\"" { } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110280 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult5\|altshift:external_latency_ffs sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110312 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" { } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 2 " "Parameter \"LPM_WIDTHA\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 14 " "Parameter \"LPM_WIDTHB\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 16 " "Parameter \"LPM_WIDTHP\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 16 " "Parameter \"LPM_WIDTHR\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454110367 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110399 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" { } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110432 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult2\|altshift:external_latency_ffs sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110466 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult3 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult3\"" { } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult3 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 5 " "Parameter \"LPM_WIDTHB\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 9 " "Parameter \"LPM_WIDTHP\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 9 " "Parameter \"LPM_WIDTHR\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454110541 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult3\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult3 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult3\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult3\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110584 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult3\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult3 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult3\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult3\"" { } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110603 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\"" { } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 3 " "Parameter \"LPM_WIDTHA\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 7 " "Parameter \"LPM_WIDTHB\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 10 " "Parameter \"LPM_WIDTHP\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 10 " "Parameter \"LPM_WIDTHR\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454110696 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult6\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110756 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult6\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\"" { } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110815 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult6\|altshift:external_latency_ffs sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110848 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult4 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult4\"" { } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult4 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult4\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 7 " "Parameter \"LPM_WIDTHB\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 11 " "Parameter \"LPM_WIDTHP\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 11 " "Parameter \"LPM_WIDTHR\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454110915 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult4\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult4 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult4\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult4\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110956 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult4\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult4 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult4\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult4\"" { } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110985 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1457454112691 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1457454114662 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454114662 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "2188 " "Implemented 2188 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "93 " "Implemented 93 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1457454115182 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1457454115182 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2065 " "Implemented 2065 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1457454115182 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1457454115182 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "499 " "Peak virtual memory: 499 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457454115376 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:21:55 2016 " "Processing ended: Tue Mar 08 16:21:55 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457454115376 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Elapsed time: 00:00:16" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457454115376 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457454115376 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1457454115376 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1457454119614 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457454119629 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:21:57 2016 " "Processing started: Tue Mar 08 16:21:57 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457454119629 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1457454119629 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off sobel -c sobel " "Command: quartus_fit --read_settings_files=off --write_settings_files=off sobel -c sobel" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1457454119634 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1457454119714 ""} +{ "Info" "0" "" "Project = sobel" { } { } 0 0 "Project = sobel" 0 0 "Fitter" 0 0 1457454119714 ""} +{ "Info" "0" "" "Revision = sobel" { } { } 0 0 "Revision = sobel" 0 0 "Fitter" 0 0 1457454119715 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1457454121042 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "sobel EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"sobel\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1457454121441 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1457454121498 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1457454121499 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1457454121499 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1457454121600 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1457454121802 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1457454121802 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1457454121802 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1457454121802 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4364 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454121811 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4366 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454121811 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4368 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454121811 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4370 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454121811 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4372 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454121811 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1457454121811 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1457454121816 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "123 123 " "No exact pin location assignment(s) for 123 pins of 123 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[0\] " "Pin vout_rsc_z\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[0] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 107 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[1\] " "Pin vout_rsc_z\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[1] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 108 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[2\] " "Pin vout_rsc_z\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[2] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 109 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[3\] " "Pin vout_rsc_z\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[3] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 110 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[4\] " "Pin vout_rsc_z\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[4] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 111 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[5\] " "Pin vout_rsc_z\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[5] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 112 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[6\] " "Pin vout_rsc_z\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[6] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 113 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[7\] " "Pin vout_rsc_z\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[7] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 114 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[8\] " "Pin vout_rsc_z\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[8] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 115 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[9\] " "Pin vout_rsc_z\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[9] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 116 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[10\] " "Pin vout_rsc_z\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[10] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 117 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[11\] " "Pin vout_rsc_z\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[11] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 118 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[12\] " "Pin vout_rsc_z\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[12] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 119 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[13\] " "Pin vout_rsc_z\[13\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[13] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 120 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[14\] " "Pin vout_rsc_z\[14\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[14] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 121 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[15\] " "Pin vout_rsc_z\[15\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[15] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 122 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[16\] " "Pin vout_rsc_z\[16\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[16] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 123 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[17\] " "Pin vout_rsc_z\[17\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[17] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 124 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[18\] " "Pin vout_rsc_z\[18\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[18] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 125 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[19\] " "Pin vout_rsc_z\[19\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[19] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 126 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[20\] " "Pin vout_rsc_z\[20\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[20] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 127 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[21\] " "Pin vout_rsc_z\[21\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[21] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 128 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[22\] " "Pin vout_rsc_z\[22\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[22] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 129 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[23\] " "Pin vout_rsc_z\[23\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[23] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 130 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[24\] " "Pin vout_rsc_z\[24\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[24] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 131 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[25\] " "Pin vout_rsc_z\[25\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[25] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 132 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[26\] " "Pin vout_rsc_z\[26\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[26] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 133 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[27\] " "Pin vout_rsc_z\[27\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[27] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 134 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[28\] " "Pin vout_rsc_z\[28\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[28] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 135 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[29\] " "Pin vout_rsc_z\[29\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[29] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 136 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk " "Pin clk not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { clk } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1578 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 137 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "arst_n " "Pin arst_n not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { arst_n } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1580 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { arst_n } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 139 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "en " "Pin en not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { en } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1579 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 138 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[57\] " "Pin vin_rsc_z\[57\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[57] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[57] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 74 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[56\] " "Pin vin_rsc_z\[56\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[56] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[56] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 73 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[55\] " "Pin vin_rsc_z\[55\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[55] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[55] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 72 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[54\] " "Pin vin_rsc_z\[54\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[54] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[54] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 71 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[53\] " "Pin vin_rsc_z\[53\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[53] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[53] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 70 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[52\] " "Pin vin_rsc_z\[52\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[52] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[52] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 69 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[51\] " "Pin vin_rsc_z\[51\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[51] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[51] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 68 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[50\] " "Pin vin_rsc_z\[50\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[50] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[50] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 67 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[47\] " "Pin vin_rsc_z\[47\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[47] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[47] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 64 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[37\] " "Pin vin_rsc_z\[37\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[37] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[37] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 54 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[46\] " "Pin vin_rsc_z\[46\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[46] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[46] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 63 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[36\] " "Pin vin_rsc_z\[36\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[36] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[36] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 53 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[45\] " "Pin vin_rsc_z\[45\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[45] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[45] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 62 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[35\] " "Pin vin_rsc_z\[35\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[35] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[35] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 52 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[44\] " "Pin vin_rsc_z\[44\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[44] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[44] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 61 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[34\] " "Pin vin_rsc_z\[34\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[34] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[34] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 51 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[43\] " "Pin vin_rsc_z\[43\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[43] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[43] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 60 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[33\] " "Pin vin_rsc_z\[33\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[33] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 50 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[42\] " "Pin vin_rsc_z\[42\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[42] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[42] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 59 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[32\] " "Pin vin_rsc_z\[32\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[32] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 49 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[41\] " "Pin vin_rsc_z\[41\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[41] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[41] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 58 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[31\] " "Pin vin_rsc_z\[31\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[31] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 48 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[40\] " "Pin vin_rsc_z\[40\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[40] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[40] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 57 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[30\] " "Pin vin_rsc_z\[30\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[30] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 47 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[78\] " "Pin vin_rsc_z\[78\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[78] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[78] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 95 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[68\] " "Pin vin_rsc_z\[68\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[68] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[68] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 85 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[77\] " "Pin vin_rsc_z\[77\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[77] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[77] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 94 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[67\] " "Pin vin_rsc_z\[67\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[67] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[67] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 84 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[76\] " "Pin vin_rsc_z\[76\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[76] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[76] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 93 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[66\] " "Pin vin_rsc_z\[66\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[66] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[66] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 83 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[75\] " "Pin vin_rsc_z\[75\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[75] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[75] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 92 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[65\] " "Pin vin_rsc_z\[65\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[65] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[65] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 82 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[74\] " "Pin vin_rsc_z\[74\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[74] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[74] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 91 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[64\] " "Pin vin_rsc_z\[64\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[64] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[64] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 81 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[73\] " "Pin vin_rsc_z\[73\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[73] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[73] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 90 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[63\] " "Pin vin_rsc_z\[63\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[63] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[63] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 80 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[72\] " "Pin vin_rsc_z\[72\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[72] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[72] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 89 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[62\] " "Pin vin_rsc_z\[62\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[62] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[62] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 79 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[71\] " "Pin vin_rsc_z\[71\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[71] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[71] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 88 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[61\] " "Pin vin_rsc_z\[61\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[61] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[61] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 78 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[70\] " "Pin vin_rsc_z\[70\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[70] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[70] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 87 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[60\] " "Pin vin_rsc_z\[60\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[60] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[60] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 77 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[88\] " "Pin vin_rsc_z\[88\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[88] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[88] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 105 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[87\] " "Pin vin_rsc_z\[87\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[87] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[87] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 104 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[86\] " "Pin vin_rsc_z\[86\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[86] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[86] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 103 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[85\] " "Pin vin_rsc_z\[85\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[85] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[85] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 102 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[84\] " "Pin vin_rsc_z\[84\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[84] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[84] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 101 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[83\] " "Pin vin_rsc_z\[83\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[83] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[83] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 100 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[82\] " "Pin vin_rsc_z\[82\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[82] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[82] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 99 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[81\] " "Pin vin_rsc_z\[81\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[81] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[81] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 98 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[80\] " "Pin vin_rsc_z\[80\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[80] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[80] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 97 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[8\] " "Pin vin_rsc_z\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[8] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 25 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[7\] " "Pin vin_rsc_z\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[7] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 24 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[6\] " "Pin vin_rsc_z\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[6] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 23 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[5\] " "Pin vin_rsc_z\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[5] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 22 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[4\] " "Pin vin_rsc_z\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[4] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 21 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[3\] " "Pin vin_rsc_z\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[3] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 20 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[2\] " "Pin vin_rsc_z\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[2] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 19 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[1\] " "Pin vin_rsc_z\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[1] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 18 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[0\] " "Pin vin_rsc_z\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[0] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 17 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[28\] " "Pin vin_rsc_z\[28\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[28] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 45 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[18\] " "Pin vin_rsc_z\[18\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[18] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 35 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[27\] " "Pin vin_rsc_z\[27\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[27] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 44 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[17\] " "Pin vin_rsc_z\[17\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[17] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 34 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[26\] " "Pin vin_rsc_z\[26\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[26] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 43 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[16\] " "Pin vin_rsc_z\[16\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[16] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 33 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[25\] " "Pin vin_rsc_z\[25\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[25] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 42 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[15\] " "Pin vin_rsc_z\[15\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[15] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 32 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[24\] " "Pin vin_rsc_z\[24\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[24] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 41 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[14\] " "Pin vin_rsc_z\[14\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[14] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 31 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[23\] " "Pin vin_rsc_z\[23\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[23] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 40 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[13\] " "Pin vin_rsc_z\[13\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[13] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 30 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[22\] " "Pin vin_rsc_z\[22\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[22] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 39 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[12\] " "Pin vin_rsc_z\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[12] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 29 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[21\] " "Pin vin_rsc_z\[21\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[21] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 38 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[11\] " "Pin vin_rsc_z\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[11] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 28 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[20\] " "Pin vin_rsc_z\[20\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[20] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 37 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[10\] " "Pin vin_rsc_z\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[10] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 27 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[9\] " "Pin vin_rsc_z\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[9] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 26 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[29\] " "Pin vin_rsc_z\[29\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[29] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 46 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[19\] " "Pin vin_rsc_z\[19\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[19] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 36 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[79\] " "Pin vin_rsc_z\[79\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[79] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[79] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 96 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[69\] " "Pin vin_rsc_z\[69\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[69] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[69] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 86 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[89\] " "Pin vin_rsc_z\[89\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[89] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[89] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 106 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[59\] " "Pin vin_rsc_z\[59\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[59] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[59] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 76 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[58\] " "Pin vin_rsc_z\[58\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[58] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[58] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 75 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[49\] " "Pin vin_rsc_z\[49\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[49] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[49] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 66 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[39\] " "Pin vin_rsc_z\[39\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[39] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[39] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 56 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[48\] " "Pin vin_rsc_z\[48\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[48] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[48] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 65 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[38\] " "Pin vin_rsc_z\[38\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[38] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[38] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 55 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1457454122506 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "sobel.sdc " "Synopsys Design Constraints File file not found: 'sobel.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1457454123211 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1457454123214 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1457454123232 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1457454123235 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1457454123241 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN G2 (CLK0, DIFFCLK_0p)) " "Automatically promoted node clk~input (placed in PIN G2 (CLK0, DIFFCLK_0p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457454123323 ""} } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1578 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4267 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457454123323 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "arst_n~input (placed in PIN G1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node arst_n~input (placed in PIN G1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457454123326 ""} } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1580 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { arst_n~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4268 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457454123326 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1457454123973 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1457454123976 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1457454123979 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1457454123983 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1457454123987 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1457454123990 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1457454123993 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1457454123997 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1457454124047 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1457454124053 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1457454124053 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "121 unused 2.5V 91 30 0 " "Number of I/O pins in group: 121 (unused VREF, 2.5V VCCIO, 91 input, 30 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1457454124065 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1457454124065 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1457454124065 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 6 27 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 6 total pin(s) used -- 27 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 46 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 41 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 46 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 42 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 47 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1457454124070 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1457454124070 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454124156 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1457454125133 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454125463 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1457454125477 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1457454128060 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454128062 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1457454128891 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "3 " "Router estimated average interconnect usage is 3% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "15 X21_Y10 X30_Y19 " "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19" { } { { "loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 1 { 0 "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19"} { { 11 { 0 "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19"} 21 10 10 10 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1457454129768 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1457454129768 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454131138 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1457454131144 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1457454131144 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.87 " "Total time spent on timing analysis during the Fitter is 0.87 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1457454131183 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1457454131274 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1457454131732 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1457454131806 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1457454132115 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454132876 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/output_files/sobel.fit.smsg " "Generated suppressed messages file /EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/output_files/sobel.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1457454133803 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1146 " "Peak virtual memory: 1146 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457454135965 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:22:15 2016 " "Processing ended: Tue Mar 08 16:22:15 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457454135965 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Elapsed time: 00:00:18" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457454135965 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457454135965 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1457454135965 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1457454142874 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457454142879 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:22:22 2016 " "Processing started: Tue Mar 08 16:22:22 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457454142879 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1457454142879 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off sobel -c sobel " "Command: quartus_asm --read_settings_files=off --write_settings_files=off sobel -c sobel" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1457454142879 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1457454144620 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1457454144661 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "441 " "Peak virtual memory: 441 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457454145417 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:22:25 2016 " "Processing ended: Tue Mar 08 16:22:25 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457454145417 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457454145417 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457454145417 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1457454145417 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1457454146313 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1457454147871 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457454147881 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:22:26 2016 " "Processing started: Tue Mar 08 16:22:26 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457454147881 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1457454147881 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta sobel -c sobel " "Command: quartus_sta sobel -c sobel" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1457454147884 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1457454147941 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1457454149057 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1457454149060 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1457454149107 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1457454149108 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "sobel.sdc " "Synopsys Design Constraints File file not found: 'sobel.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1457454149748 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1457454149751 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1457454149764 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1457454149764 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1457454149784 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1457454149787 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1457454149805 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1457454149884 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1457454150090 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1457454150090 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -21.345 " "Worst-case setup slack is -21.345" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150125 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150125 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -21.345 -1510.709 clk " " -21.345 -1510.709 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150125 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454150125 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.516 " "Worst-case hold slack is 0.516" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150163 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150163 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.516 0.000 clk " " 0.516 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150163 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454150163 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1457454150196 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1457454150226 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150253 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150253 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -287.000 clk " " -3.000 -287.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150253 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454150253 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1457454150501 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1457454150526 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1457454151095 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151302 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1457454151423 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1457454151423 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -18.828 " "Worst-case setup slack is -18.828" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151479 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151479 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -18.828 -1326.336 clk " " -18.828 -1326.336 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151479 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454151479 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.466 " "Worst-case hold slack is 0.466" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151548 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151548 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.466 0.000 clk " " 0.466 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151548 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454151548 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1457454151583 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1457454151618 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -287.000 clk " " -3.000 -287.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151673 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454151673 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1457454152064 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152466 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1457454152469 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1457454152469 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -11.400 " "Worst-case setup slack is -11.400" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152492 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152492 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -11.400 -781.716 clk " " -11.400 -781.716 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152492 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454152492 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.268 " "Worst-case hold slack is 0.268" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152523 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152523 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.268 0.000 clk " " 0.268 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152523 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454152523 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1457454152550 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1457454152581 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152610 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152610 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -303.956 clk " " -3.000 -303.956 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152610 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454152610 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1457454153329 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1457454153339 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "522 " "Peak virtual memory: 522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457454153827 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:22:33 2016 " "Processing ended: Tue Mar 08 16:22:33 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457454153827 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457454153827 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457454153827 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1457454153827 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 8 s " "Quartus II Full Compilation was successful. 0 errors, 8 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1457454159451 ""} |