diff options
Diffstat (limited to 'Sobel/sobel.v1/rtl.rpt')
| -rw-r--r-- | Sobel/sobel.v1/rtl.rpt | 878 |
1 files changed, 878 insertions, 0 deletions
diff --git a/Sobel/sobel.v1/rtl.rpt b/Sobel/sobel.v1/rtl.rpt new file mode 100644 index 0000000..3bdb058 --- /dev/null +++ b/Sobel/sobel.v1/rtl.rpt @@ -0,0 +1,878 @@ +-- Catapult University Version: Report +-- ---------------------------- --------------------------------------------------- +-- Version: 2011a.126 Production Release +-- Build Date: Wed Aug 8 00:52:07 PDT 2012 + +-- Generated by: mg3115@EEWS104A-013 +-- Generated date: Tue Mar 08 13:49:49 +0000 2016 + +Solution Settings: sobel.v1 + Current state: extract + Project: Sobel + + Design Input Files Specified + $PROJECT_HOME/sobel.h + $MGC_HOME/shared/include/ac_int.h + $PROJECT_HOME/bmp_io.cpp + $PROJECT_HOME/bmp_io.h + $PROJECT_HOME/tb_blur.cpp + $MGC_HOME/shared/include/mc_testbench.h + $MGC_HOME/shared/include/mc_scverify.h + $MGC_HOME/shared/include/ac_int.h + $PROJECT_HOME/sobel.h + $PROJECT_HOME/bmp_io.h + $PROJECT_HOME/bmp_io.h + $PROJECT_HOME/shift_class.h + $PROJECT_HOME/sobel.cpp + $MGC_HOME/shared/include/ac_fixed.h + $MGC_HOME/shared/include/ac_int.h + $PROJECT_HOME/sobel.h + $PROJECT_HOME/shift_class.h + + Processes/Blocks in Design + Process Real Operation(s) count Latency Throughput Reset Length II Comments + ------------- ----------------------- ------- ---------- ------------ -- -------- + /sobel/core 105 307200 307200 0 1 + Design Total: 105 307200 307200 0 0 + + Bill Of Materials (Datapath) + Component Name Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign + --------------------------------------- ---------- --------------------------- ---------- ----- ---------- ----------- + [Lib: mgc_Altera-Cyclone-III-6_beh_psr] + mgc_add(10,0,10,0,10) 11.241 0.000 11.241 1.301 2 2 + mgc_add(10,1,10,1,11) 11.000 0.000 11.000 1.139 0 3 + mgc_add(11,0,10,1,12) 12.000 0.000 12.000 1.208 2 2 + mgc_add(11,1,11,1,12) 12.000 0.000 12.000 1.206 6 6 + mgc_add(12,0,11,0,13) 13.228 0.000 13.228 1.436 2 0 + mgc_add(12,0,11,1,12) 13.000 0.000 13.000 1.436 0 2 + mgc_add(12,1,12,1,13) 13.000 0.000 13.000 1.272 9 6 + mgc_add(13,0,12,1,13) 14.000 0.000 14.000 1.501 2 0 + mgc_add(19,0,2,1,19) 20.000 0.000 20.000 1.908 1 0 + mgc_add(2,0,2,0,3) 3.311 0.000 3.311 0.653 3 0 + mgc_add(3,0,2,0,4) 4.306 0.000 4.306 0.764 0 4 + mgc_add(3,0,3,0,4) 4.302 0.000 4.302 0.761 8 8 + mgc_add(4,0,4,0,5) 5.293 0.000 5.293 0.854 5 5 + mgc_add(4,1,3,0,5) 6.000 0.000 6.000 0.856 0 1 + mgc_add(5,0,5,0,5) 6.285 0.000 6.285 0.938 0 3 + mgc_add(5,0,5,1,7) 6.000 0.000 6.000 0.613 9 9 + mgc_add(5,1,4,1,6) 6.000 0.000 6.000 0.778 1 1 + mgc_add(6,0,5,1,8) 7.000 0.000 7.000 0.693 2 2 + mgc_add(6,0,6,0,6) 7.276 0.000 7.276 1.016 3 0 + mgc_add(7,1,6,0,8) 9.000 0.000 9.000 1.093 1 0 + mgc_add(8,0,7,0,8) 9.262 0.000 9.262 1.165 1 0 + mgc_add(9,0,8,1,10) 10.000 0.000 10.000 1.072 3 3 + mgc_and(19,2) 13.867 0.000 13.867 0.263 1 0 + mgc_mul(2,0,9,0,11) 330.250 2.000 10.250 3.044 3 3 + mgc_mul(3,0,6,0,9) 330.250 2.000 10.250 2.846 3 3 + mgc_not(1) 0.000 0.000 0.000 0.000 0 11 + mgc_not(10) 0.000 0.000 0.000 0.000 0 9 + mgc_not(3) 0.000 0.000 0.000 0.000 0 12 + mgc_or(1,2) 0.730 0.000 0.730 0.268 0 1 + mgc_or(10,2) 7.298 0.000 7.298 0.268 1 1 + mgc_or(5,2) 3.649 0.000 3.649 0.268 0 1 + mgc_or(6,2) 4.379 0.000 4.379 0.268 1 0 + mgc_reg_pos(1,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 2 + mgc_reg_pos(10,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 10 + mgc_reg_pos(4,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 1 + mgc_reg_pos(5,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 1 + mgc_reg_pos(9,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 1 + mgc_reg_pos(90,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 1 + [Lib: mgc_ioport] + mgc_in_wire(1,90) 0.000 0.000 0.000 0.000 1 1 + mgc_out_stdreg(2,30) 0.000 0.000 0.000 0.000 1 1 + + TOTAL AREA (After Assignment): 2455.620 12.000 536.000 + + Area Scores + Post-Scheduling Post-DP & FSM Post-Assignment + ----------------- --------------- --------------- --------------- + Total Area Score: 2531.9 2479.4 2455.6 + Total Reg: 0.0 0.0 0.0 + + DataPath: 2531.9 (100%) 2479.4 (100%) 2455.6 (100%) + MUX: 0.0 0.0 0.0 + FUNC: 2506.3 (99%) 2467.7 (100%) 2443.9 (100%) + LOGIC: 25.5 (1%) 11.7 (0%) 11.7 (0%) + BUFFER: 0.0 0.0 0.0 + MEM: 0.0 0.0 0.0 + ROM: 0.0 0.0 0.0 + REG: 0.0 0.0 0.0 + + + FSM: 0.0 0.0 0.0 + FSM-REG: 0.0 0.0 0.0 + FSM-COMB: 0.0 0.0 0.0 + + + Register-to-Variable Mappings + Register Size(bits) Gated Register CG Opt Done Variables + ------------------------------------ ---------- -------------- ----------- ----------------------------------------------------- + regs.regs(1).sva 90 Y regs.regs(1).sva + ACC1:slc(regs.regs(2))#10.itm 10 Y ACC1:slc(regs.regs(2))#10.itm + ACC1:slc(regs.regs(2))#11.itm 10 Y ACC1:slc(regs.regs(2))#11.itm + ACC1:slc(regs.regs(2))#12.itm 10 Y ACC1:slc(regs.regs(2))#12.itm + ACC1:slc(regs.regs(2))#13.itm 10 Y ACC1:slc(regs.regs(2))#13.itm + ACC1:slc(regs.regs(2))#14.itm 10 Y ACC1:slc(regs.regs(2))#14.itm + ACC1:slc(regs.regs(2))#15.itm 10 Y ACC1:slc(regs.regs(2))#15.itm + ACC1:slc(regs.regs(2))#16.itm 10 Y ACC1:slc(regs.regs(2))#16.itm + ACC1:slc(regs.regs(2))#9.itm 10 Y ACC1:slc(regs.regs(2))#9.itm + ACC1:slc(regs.regs(2)).itm 10 Y ACC1:slc(regs.regs(2)).itm + reg(vout:rsc:mgc_out_stdreg.d).tmp 10 Y reg(vout:rsc:mgc_out_stdreg.d).tmp + reg(vout:rsc:mgc_out_stdreg.d).tmp#4 9 Y reg(vout:rsc:mgc_out_stdreg.d).tmp#4 + reg(vout:rsc:mgc_out_stdreg.d).tmp#2 5 Y reg(vout:rsc:mgc_out_stdreg.d).tmp#2 + reg(vout:rsc:mgc_out_stdreg.d).tmp#1 4 Y reg(vout:rsc:mgc_out_stdreg.d).tmp#1 + reg(vout:rsc:mgc_out_stdreg.d).tmp#3 1 Y reg(vout:rsc:mgc_out_stdreg.d).tmp#3 + reg(vout:rsc:mgc_out_stdreg.d).tmp#5 1 Y reg(vout:rsc:mgc_out_stdreg.d).tmp#5 + + Total: 210 210 0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) + + Timing Report + Critical Path + Max Delay: 14.431315999999997 + Slack: 5.568684000000003 + + Path Startpoint Endpoint Delay Slack + ----------------------------------------------- --------------------------------------------- ------------------------------------------- ------- ------- + 1 sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d) 14.4313 5.5687 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2))#11.itm 0.0000 0.0000 + sobel:core/conc#139 0.0000 0.0000 + sobel:core/conc#139.itm 0.0000 0.0000 + sobel:core/ACC1:acc#49 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#49.itm 0.0000 1.2059 + sobel:core/ACC1:slc#5 0.0000 1.2059 + sobel:core/ACC1:slc#5.itm 0.0000 1.2059 + sobel:core/conc#138 0.0000 1.2059 + sobel:core/conc#138.itm 0.0000 1.2059 + sobel:core/ACC1:acc#51 mgc_add_12_1_12_1_13 1.2718 2.4777 + sobel:core/ACC1:acc#51.itm 0.0000 2.4777 + sobel:core/ACC1:slc#7 0.0000 2.4777 + sobel:core/ACC1:slc#7.itm 0.0000 2.4777 + sobel:core/ACC1:acc#42 mgc_add_12_1_12_1_13 1.2718 3.7496 + sobel:core/ACC1:acc#42.psp.sva 0.0000 3.7496 + sobel:core/slc(ACC1:acc#42.psp.sva)#7 0.0000 3.7496 + sobel:core/slc(ACC1:acc#42.psp.sva)#7.itm 0.0000 3.7496 + sobel:core/FRAME:acc#15 mgc_add_3_0_3_0_4 0.7609 4.5105 + sobel:core/FRAME:acc#15.itm 0.0000 4.5105 + sobel:core/FRAME:acc#17 mgc_add_4_0_4_0_5 0.8536 5.3640 + sobel:core/FRAME:acc#17.itm 0.0000 5.3640 + sobel:core/FRAME:acc#18 mgc_add_5_0_5_1_7 0.6126 5.9766 + sobel:core/FRAME:acc#18.sdt 0.0000 5.9766 + sobel:core/slc(FRAME:acc#18.sdt)#1 0.0000 5.9766 + sobel:core/slc(FRAME:acc#18.sdt)#1.itm 0.0000 5.9766 + sobel:core/FRAME:acc#49 mgc_add_5_0_5_0_5 0.9376 6.9142 + sobel:core/FRAME:acc#49.psp 0.0000 6.9142 + sobel:core/slc(FRAME:acc#49.psp)#1 0.0000 6.9142 + sobel:core/slc(FRAME:acc#49.psp)#1.itm 0.0000 6.9142 + sobel:core/conc#118 0.0000 6.9142 + sobel:core/conc#118.itm 0.0000 6.9142 + sobel:core/FRAME:acc#26 mgc_add_5_0_5_1_7 0.6126 7.5269 + sobel:core/FRAME:acc#26.itm 0.0000 7.5269 + sobel:core/FRAME:slc#5 0.0000 7.5269 + sobel:core/FRAME:slc#5.itm 0.0000 7.5269 + sobel:core/FRAME:not#52 mgc_not_1 0.0000 7.5269 + sobel:core/FRAME:not#52.itm 0.0000 7.5269 + sobel:core/conc#117 0.0000 7.5269 + sobel:core/conc#117.itm 0.0000 7.5269 + sobel:core/FRAME:acc#19 mgc_add_3_0_3_0_4 0.7609 8.2878 + sobel:core/FRAME:acc#19.itm 0.0000 8.2878 + sobel:core/FRAME:acc#20 mgc_add_4_0_4_0_5 0.8536 9.1413 + sobel:core/FRAME:acc#20.itm 0.0000 9.1413 + sobel:core/FRAME:acc#21 mgc_add_5_0_5_1_7 0.6126 9.7540 + sobel:core/FRAME:acc#21.itm 0.0000 9.7540 + sobel:core/FRAME:acc#22 mgc_add_6_0_5_1_8 0.6934 10.4474 + sobel:core/FRAME:acc#22.itm 0.0000 10.4474 + sobel:core/FRAME:acc#23 mgc_add_9_0_8_1_10 1.0725 11.5198 + sobel:core/FRAME:acc#23.itm 0.0000 11.5198 + sobel:core/FRAME:acc#24 mgc_add_11_0_10_1_12 1.2076 12.7275 + sobel:core/FRAME:acc#24.sdt 0.0000 12.7275 + sobel:core/slc(FRAME:acc#24.sdt)#1 0.0000 12.7275 + sobel:core/slc(FRAME:acc#24.sdt)#1.itm 0.0000 12.7275 + sobel:core/FRAME:acc mgc_add_12_0_11_1_12 1.4360 14.1634 + sobel:core/FRAME:acc.psp 0.0000 14.1634 + sobel:core/slc(FRAME:acc.psp) 0.0000 14.1634 + sobel:core/slc(FRAME:acc.psp).itm 0.0000 14.1634 + sobel:core/conc#147 0.0000 14.1634 + sobel:core/conc#147.itm 0.0000 14.1634 + sobel:core/FRAME:or mgc_or_10_2 0.2679 14.4313 + sobel:core/FRAME:or.itm 0.0000 14.4313 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 14.4313 + + 2 sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 14.4313 5.5687 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2))#11.itm 0.0000 0.0000 + sobel:core/conc#139 0.0000 0.0000 + sobel:core/conc#139.itm 0.0000 0.0000 + sobel:core/ACC1:acc#49 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#49.itm 0.0000 1.2059 + sobel:core/ACC1:slc#5 0.0000 1.2059 + sobel:core/ACC1:slc#5.itm 0.0000 1.2059 + sobel:core/conc#138 0.0000 1.2059 + sobel:core/conc#138.itm 0.0000 1.2059 + sobel:core/ACC1:acc#51 mgc_add_12_1_12_1_13 1.2718 2.4777 + sobel:core/ACC1:acc#51.itm 0.0000 2.4777 + sobel:core/ACC1:slc#7 0.0000 2.4777 + sobel:core/ACC1:slc#7.itm 0.0000 2.4777 + sobel:core/ACC1:acc#42 mgc_add_12_1_12_1_13 1.2718 3.7496 + sobel:core/ACC1:acc#42.psp.sva 0.0000 3.7496 + sobel:core/slc(ACC1:acc#42.psp.sva)#7 0.0000 3.7496 + sobel:core/slc(ACC1:acc#42.psp.sva)#7.itm 0.0000 3.7496 + sobel:core/FRAME:acc#15 mgc_add_3_0_3_0_4 0.7609 4.5105 + sobel:core/FRAME:acc#15.itm 0.0000 4.5105 + sobel:core/FRAME:acc#17 mgc_add_4_0_4_0_5 0.8536 5.3640 + sobel:core/FRAME:acc#17.itm 0.0000 5.3640 + sobel:core/FRAME:acc#18 mgc_add_5_0_5_1_7 0.6126 5.9766 + sobel:core/FRAME:acc#18.sdt 0.0000 5.9766 + sobel:core/slc(FRAME:acc#18.sdt)#1 0.0000 5.9766 + sobel:core/slc(FRAME:acc#18.sdt)#1.itm 0.0000 5.9766 + sobel:core/FRAME:acc#49 mgc_add_5_0_5_0_5 0.9376 6.9142 + sobel:core/FRAME:acc#49.psp 0.0000 6.9142 + sobel:core/slc(FRAME:acc#49.psp)#1 0.0000 6.9142 + sobel:core/slc(FRAME:acc#49.psp)#1.itm 0.0000 6.9142 + sobel:core/conc#118 0.0000 6.9142 + sobel:core/conc#118.itm 0.0000 6.9142 + sobel:core/FRAME:acc#26 mgc_add_5_0_5_1_7 0.6126 7.5269 + sobel:core/FRAME:acc#26.itm 0.0000 7.5269 + sobel:core/FRAME:slc#5 0.0000 7.5269 + sobel:core/FRAME:slc#5.itm 0.0000 7.5269 + sobel:core/FRAME:not#52 mgc_not_1 0.0000 7.5269 + sobel:core/FRAME:not#52.itm 0.0000 7.5269 + sobel:core/conc#117 0.0000 7.5269 + sobel:core/conc#117.itm 0.0000 7.5269 + sobel:core/FRAME:acc#19 mgc_add_3_0_3_0_4 0.7609 8.2878 + sobel:core/FRAME:acc#19.itm 0.0000 8.2878 + sobel:core/FRAME:acc#20 mgc_add_4_0_4_0_5 0.8536 9.1413 + sobel:core/FRAME:acc#20.itm 0.0000 9.1413 + sobel:core/FRAME:acc#21 mgc_add_5_0_5_1_7 0.6126 9.7540 + sobel:core/FRAME:acc#21.itm 0.0000 9.7540 + sobel:core/FRAME:acc#22 mgc_add_6_0_5_1_8 0.6934 10.4474 + sobel:core/FRAME:acc#22.itm 0.0000 10.4474 + sobel:core/FRAME:acc#23 mgc_add_9_0_8_1_10 1.0725 11.5198 + sobel:core/FRAME:acc#23.itm 0.0000 11.5198 + sobel:core/FRAME:acc#24 mgc_add_11_0_10_1_12 1.2076 12.7275 + sobel:core/FRAME:acc#24.sdt 0.0000 12.7275 + sobel:core/slc(FRAME:acc#24.sdt)#1 0.0000 12.7275 + sobel:core/slc(FRAME:acc#24.sdt)#1.itm 0.0000 12.7275 + sobel:core/FRAME:acc mgc_add_12_0_11_1_12 1.4360 14.1634 + sobel:core/FRAME:acc.psp 0.0000 14.1634 + sobel:core/slc(FRAME:acc.psp)#2 0.0000 14.1634 + sobel:core/slc(FRAME:acc.psp)#2.itm 0.0000 14.1634 + sobel:core/FRAME:or#3 mgc_or_5_2 0.2679 14.4313 + sobel:core/FRAME:or#3.itm 0.0000 14.4313 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 mgc_reg_pos_5_1_0_0_0_1_1 0.0000 14.4313 + + 3 sobel:core/reg(ACC1:slc(regs.regs(2))#14.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#3 14.4313 5.5687 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2))#14.itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2))#14.itm 0.0000 0.0000 + sobel:core/conc#131 0.0000 0.0000 + sobel:core/conc#131.itm 0.0000 0.0000 + sobel:core/ACC1:acc#53 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#53.itm 0.0000 1.2059 + sobel:core/ACC1:slc#9 0.0000 1.2059 + sobel:core/ACC1:slc#9.itm 0.0000 1.2059 + sobel:core/conc#130 0.0000 1.2059 + sobel:core/conc#130.itm 0.0000 1.2059 + sobel:core/ACC1:acc#55 mgc_add_12_1_12_1_13 1.2718 2.4777 + sobel:core/ACC1:acc#55.itm 0.0000 2.4777 + sobel:core/ACC1:slc#11 0.0000 2.4777 + sobel:core/ACC1:slc#11.itm 0.0000 2.4777 + sobel:core/ACC1:acc#43 mgc_add_12_1_12_1_13 1.2718 3.7496 + sobel:core/ACC1:acc#43.psp.sva 0.0000 3.7496 + sobel:core/slc(ACC1:acc#43.psp.sva)#7 0.0000 3.7496 + sobel:core/slc(ACC1:acc#43.psp.sva)#7.itm 0.0000 3.7496 + sobel:core/FRAME:acc#28 mgc_add_3_0_3_0_4 0.7609 4.5105 + sobel:core/FRAME:acc#28.itm 0.0000 4.5105 + sobel:core/FRAME:acc#30 mgc_add_4_0_4_0_5 0.8536 5.3640 + sobel:core/FRAME:acc#30.itm 0.0000 5.3640 + sobel:core/FRAME:acc#31 mgc_add_5_0_5_1_7 0.6126 5.9766 + sobel:core/FRAME:acc#31.sdt 0.0000 5.9766 + sobel:core/slc(FRAME:acc#31.sdt)#1 0.0000 5.9766 + sobel:core/slc(FRAME:acc#31.sdt)#1.itm 0.0000 5.9766 + sobel:core/FRAME:acc#55 mgc_add_5_0_5_0_5 0.9376 6.9142 + sobel:core/FRAME:acc#55.psp 0.0000 6.9142 + sobel:core/slc(FRAME:acc#55.psp)#1 0.0000 6.9142 + sobel:core/slc(FRAME:acc#55.psp)#1.itm 0.0000 6.9142 + sobel:core/conc#127 0.0000 6.9142 + sobel:core/conc#127.itm 0.0000 6.9142 + sobel:core/FRAME:acc#39 mgc_add_5_0_5_1_7 0.6126 7.5269 + sobel:core/FRAME:acc#39.itm 0.0000 7.5269 + sobel:core/FRAME:slc#6 0.0000 7.5269 + sobel:core/FRAME:slc#6.itm 0.0000 7.5269 + sobel:core/FRAME:not#54 mgc_not_1 0.0000 7.5269 + sobel:core/FRAME:not#54.itm 0.0000 7.5269 + sobel:core/conc#126 0.0000 7.5269 + sobel:core/conc#126.itm 0.0000 7.5269 + sobel:core/FRAME:acc#32 mgc_add_3_0_3_0_4 0.7609 8.2878 + sobel:core/FRAME:acc#32.itm 0.0000 8.2878 + sobel:core/FRAME:acc#33 mgc_add_4_0_4_0_5 0.8536 9.1413 + sobel:core/FRAME:acc#33.itm 0.0000 9.1413 + sobel:core/FRAME:acc#34 mgc_add_5_0_5_1_7 0.6126 9.7540 + sobel:core/FRAME:acc#34.itm 0.0000 9.7540 + sobel:core/FRAME:acc#35 mgc_add_6_0_5_1_8 0.6934 10.4474 + sobel:core/FRAME:acc#35.itm 0.0000 10.4474 + sobel:core/FRAME:acc#36 mgc_add_9_0_8_1_10 1.0725 11.5198 + sobel:core/FRAME:acc#36.itm 0.0000 11.5198 + sobel:core/FRAME:acc#37 mgc_add_11_0_10_1_12 1.2076 12.7275 + sobel:core/FRAME:acc#37.sdt 0.0000 12.7275 + sobel:core/slc(FRAME:acc#37.sdt)#1 0.0000 12.7275 + sobel:core/slc(FRAME:acc#37.sdt)#1.itm 0.0000 12.7275 + sobel:core/FRAME:acc#61 mgc_add_12_0_11_1_12 1.4360 14.1634 + sobel:core/FRAME:acc#61.psp 0.0000 14.1634 + sobel:core/slc(FRAME:acc#61.psp)#2 0.0000 14.1634 + sobel:core/slc(FRAME:acc#61.psp)#2.itm 0.0000 14.1634 + sobel:core/FRAME:or#4 mgc_or_1_2 0.2679 14.4313 + sobel:core/FRAME:or#4.itm 0.0000 14.4313 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#3 mgc_reg_pos_1_1_0_0_0_1_1 0.0000 14.4313 + + 4 sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 14.4313 5.5687 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2))#11.itm 0.0000 0.0000 + sobel:core/conc#139 0.0000 0.0000 + sobel:core/conc#139.itm 0.0000 0.0000 + sobel:core/ACC1:acc#49 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#49.itm 0.0000 1.2059 + sobel:core/ACC1:slc#5 0.0000 1.2059 + sobel:core/ACC1:slc#5.itm 0.0000 1.2059 + sobel:core/conc#138 0.0000 1.2059 + sobel:core/conc#138.itm 0.0000 1.2059 + sobel:core/ACC1:acc#51 mgc_add_12_1_12_1_13 1.2718 2.4777 + sobel:core/ACC1:acc#51.itm 0.0000 2.4777 + sobel:core/ACC1:slc#7 0.0000 2.4777 + sobel:core/ACC1:slc#7.itm 0.0000 2.4777 + sobel:core/ACC1:acc#42 mgc_add_12_1_12_1_13 1.2718 3.7496 + sobel:core/ACC1:acc#42.psp.sva 0.0000 3.7496 + sobel:core/slc(ACC1:acc#42.psp.sva)#7 0.0000 3.7496 + sobel:core/slc(ACC1:acc#42.psp.sva)#7.itm 0.0000 3.7496 + sobel:core/FRAME:acc#15 mgc_add_3_0_3_0_4 0.7609 4.5105 + sobel:core/FRAME:acc#15.itm 0.0000 4.5105 + sobel:core/FRAME:acc#17 mgc_add_4_0_4_0_5 0.8536 5.3640 + sobel:core/FRAME:acc#17.itm 0.0000 5.3640 + sobel:core/FRAME:acc#18 mgc_add_5_0_5_1_7 0.6126 5.9766 + sobel:core/FRAME:acc#18.sdt 0.0000 5.9766 + sobel:core/slc(FRAME:acc#18.sdt)#1 0.0000 5.9766 + sobel:core/slc(FRAME:acc#18.sdt)#1.itm 0.0000 5.9766 + sobel:core/FRAME:acc#49 mgc_add_5_0_5_0_5 0.9376 6.9142 + sobel:core/FRAME:acc#49.psp 0.0000 6.9142 + sobel:core/slc(FRAME:acc#49.psp)#2 0.0000 6.9142 + sobel:core/slc(FRAME:acc#49.psp)#2.itm 0.0000 6.9142 + sobel:core/FRAME:not#15 mgc_not_3 0.0000 6.9142 + sobel:core/FRAME:not#15.itm 0.0000 6.9142 + sobel:core/FRAME:conc#42 0.0000 6.9142 + sobel:core/FRAME:conc#42.itm 0.0000 6.9142 + sobel:core/FRAME:acc#26 mgc_add_5_0_5_1_7 0.6126 7.5269 + sobel:core/FRAME:acc#26.itm 0.0000 7.5269 + sobel:core/FRAME:slc#5 0.0000 7.5269 + sobel:core/FRAME:slc#5.itm 0.0000 7.5269 + sobel:core/FRAME:not#52 mgc_not_1 0.0000 7.5269 + sobel:core/FRAME:not#52.itm 0.0000 7.5269 + sobel:core/conc#117 0.0000 7.5269 + sobel:core/conc#117.itm 0.0000 7.5269 + sobel:core/FRAME:acc#19 mgc_add_3_0_3_0_4 0.7609 8.2878 + sobel:core/FRAME:acc#19.itm 0.0000 8.2878 + sobel:core/FRAME:acc#20 mgc_add_4_0_4_0_5 0.8536 9.1413 + sobel:core/FRAME:acc#20.itm 0.0000 9.1413 + sobel:core/FRAME:acc#21 mgc_add_5_0_5_1_7 0.6126 9.7540 + sobel:core/FRAME:acc#21.itm 0.0000 9.7540 + sobel:core/FRAME:acc#22 mgc_add_6_0_5_1_8 0.6934 10.4474 + sobel:core/FRAME:acc#22.itm 0.0000 10.4474 + sobel:core/FRAME:acc#23 mgc_add_9_0_8_1_10 1.0725 11.5198 + sobel:core/FRAME:acc#23.itm 0.0000 11.5198 + sobel:core/FRAME:acc#24 mgc_add_11_0_10_1_12 1.2076 12.7275 + sobel:core/FRAME:acc#24.sdt 0.0000 12.7275 + sobel:core/slc(FRAME:acc#24.sdt)#1 0.0000 12.7275 + sobel:core/slc(FRAME:acc#24.sdt)#1.itm 0.0000 12.7275 + sobel:core/FRAME:acc mgc_add_12_0_11_1_12 1.4360 14.1634 + sobel:core/FRAME:acc.psp 0.0000 14.1634 + sobel:core/slc(FRAME:acc.psp)#2 0.0000 14.1634 + sobel:core/slc(FRAME:acc.psp)#2.itm 0.0000 14.1634 + sobel:core/FRAME:or#3 mgc_or_5_2 0.2679 14.4313 + sobel:core/FRAME:or#3.itm 0.0000 14.4313 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 mgc_reg_pos_5_1_0_0_0_1_1 0.0000 14.4313 + + 5 sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 14.4313 5.5687 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2))#11.itm 0.0000 0.0000 + sobel:core/conc#139 0.0000 0.0000 + sobel:core/conc#139.itm 0.0000 0.0000 + sobel:core/ACC1:acc#49 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#49.itm 0.0000 1.2059 + sobel:core/ACC1:slc#5 0.0000 1.2059 + sobel:core/ACC1:slc#5.itm 0.0000 1.2059 + sobel:core/conc#138 0.0000 1.2059 + sobel:core/conc#138.itm 0.0000 1.2059 + sobel:core/ACC1:acc#51 mgc_add_12_1_12_1_13 1.2718 2.4777 + sobel:core/ACC1:acc#51.itm 0.0000 2.4777 + sobel:core/ACC1:slc#7 0.0000 2.4777 + sobel:core/ACC1:slc#7.itm 0.0000 2.4777 + sobel:core/ACC1:acc#42 mgc_add_12_1_12_1_13 1.2718 3.7496 + sobel:core/ACC1:acc#42.psp.sva 0.0000 3.7496 + sobel:core/slc(ACC1:acc#42.psp.sva)#7 0.0000 3.7496 + sobel:core/slc(ACC1:acc#42.psp.sva)#7.itm 0.0000 3.7496 + sobel:core/FRAME:acc#15 mgc_add_3_0_3_0_4 0.7609 4.5105 + sobel:core/FRAME:acc#15.itm 0.0000 4.5105 + sobel:core/FRAME:acc#17 mgc_add_4_0_4_0_5 0.8536 5.3640 + sobel:core/FRAME:acc#17.itm 0.0000 5.3640 + sobel:core/FRAME:acc#18 mgc_add_5_0_5_1_7 0.6126 5.9766 + sobel:core/FRAME:acc#18.sdt 0.0000 5.9766 + sobel:core/slc(FRAME:acc#18.sdt)#1 0.0000 5.9766 + sobel:core/slc(FRAME:acc#18.sdt)#1.itm 0.0000 5.9766 + sobel:core/FRAME:acc#49 mgc_add_5_0_5_0_5 0.9376 6.9142 + sobel:core/FRAME:acc#49.psp 0.0000 6.9142 + sobel:core/slc(FRAME:acc#49.psp)#4 0.0000 6.9142 + sobel:core/slc(FRAME:acc#49.psp)#4.itm 0.0000 6.9142 + sobel:core/FRAME:not#47 mgc_not_1 0.0000 6.9142 + sobel:core/FRAME:not#47.itm 0.0000 6.9142 + sobel:core/FRAME:conc#42 0.0000 6.9142 + sobel:core/FRAME:conc#42.itm 0.0000 6.9142 + sobel:core/FRAME:acc#26 mgc_add_5_0_5_1_7 0.6126 7.5269 + sobel:core/FRAME:acc#26.itm 0.0000 7.5269 + sobel:core/FRAME:slc#5 0.0000 7.5269 + sobel:core/FRAME:slc#5.itm 0.0000 7.5269 + sobel:core/FRAME:not#52 mgc_not_1 0.0000 7.5269 + sobel:core/FRAME:not#52.itm 0.0000 7.5269 + sobel:core/conc#117 0.0000 7.5269 + sobel:core/conc#117.itm 0.0000 7.5269 + sobel:core/FRAME:acc#19 mgc_add_3_0_3_0_4 0.7609 8.2878 + sobel:core/FRAME:acc#19.itm 0.0000 8.2878 + sobel:core/FRAME:acc#20 mgc_add_4_0_4_0_5 0.8536 9.1413 + sobel:core/FRAME:acc#20.itm 0.0000 9.1413 + sobel:core/FRAME:acc#21 mgc_add_5_0_5_1_7 0.6126 9.7540 + sobel:core/FRAME:acc#21.itm 0.0000 9.7540 + sobel:core/FRAME:acc#22 mgc_add_6_0_5_1_8 0.6934 10.4474 + sobel:core/FRAME:acc#22.itm 0.0000 10.4474 + sobel:core/FRAME:acc#23 mgc_add_9_0_8_1_10 1.0725 11.5198 + sobel:core/FRAME:acc#23.itm 0.0000 11.5198 + sobel:core/FRAME:acc#24 mgc_add_11_0_10_1_12 1.2076 12.7275 + sobel:core/FRAME:acc#24.sdt 0.0000 12.7275 + sobel:core/slc(FRAME:acc#24.sdt)#1 0.0000 12.7275 + sobel:core/slc(FRAME:acc#24.sdt)#1.itm 0.0000 12.7275 + sobel:core/FRAME:acc mgc_add_12_0_11_1_12 1.4360 14.1634 + sobel:core/FRAME:acc.psp 0.0000 14.1634 + sobel:core/slc(FRAME:acc.psp)#2 0.0000 14.1634 + sobel:core/slc(FRAME:acc.psp)#2.itm 0.0000 14.1634 + sobel:core/FRAME:or#3 mgc_or_5_2 0.2679 14.4313 + sobel:core/FRAME:or#3.itm 0.0000 14.4313 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 mgc_reg_pos_5_1_0_0_0_1_1 0.0000 14.4313 + + 6 sobel:core/reg(ACC1:slc(regs.regs(2))#14.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#3 14.4313 5.5687 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2))#14.itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2))#14.itm 0.0000 0.0000 + sobel:core/conc#131 0.0000 0.0000 + sobel:core/conc#131.itm 0.0000 0.0000 + sobel:core/ACC1:acc#53 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#53.itm 0.0000 1.2059 + sobel:core/ACC1:slc#9 0.0000 1.2059 + sobel:core/ACC1:slc#9.itm 0.0000 1.2059 + sobel:core/conc#130 0.0000 1.2059 + sobel:core/conc#130.itm 0.0000 1.2059 + sobel:core/ACC1:acc#55 mgc_add_12_1_12_1_13 1.2718 2.4777 + sobel:core/ACC1:acc#55.itm 0.0000 2.4777 + sobel:core/ACC1:slc#11 0.0000 2.4777 + sobel:core/ACC1:slc#11.itm 0.0000 2.4777 + sobel:core/ACC1:acc#43 mgc_add_12_1_12_1_13 1.2718 3.7496 + sobel:core/ACC1:acc#43.psp.sva 0.0000 3.7496 + sobel:core/slc(ACC1:acc#43.psp.sva)#7 0.0000 3.7496 + sobel:core/slc(ACC1:acc#43.psp.sva)#7.itm 0.0000 3.7496 + sobel:core/FRAME:acc#28 mgc_add_3_0_3_0_4 0.7609 4.5105 + sobel:core/FRAME:acc#28.itm 0.0000 4.5105 + sobel:core/FRAME:acc#30 mgc_add_4_0_4_0_5 0.8536 5.3640 + sobel:core/FRAME:acc#30.itm 0.0000 5.3640 + sobel:core/FRAME:acc#31 mgc_add_5_0_5_1_7 0.6126 5.9766 + sobel:core/FRAME:acc#31.sdt 0.0000 5.9766 + sobel:core/slc(FRAME:acc#31.sdt)#1 0.0000 5.9766 + sobel:core/slc(FRAME:acc#31.sdt)#1.itm 0.0000 5.9766 + sobel:core/FRAME:acc#55 mgc_add_5_0_5_0_5 0.9376 6.9142 + sobel:core/FRAME:acc#55.psp 0.0000 6.9142 + sobel:core/slc(FRAME:acc#55.psp)#2 0.0000 6.9142 + sobel:core/slc(FRAME:acc#55.psp)#2.itm 0.0000 6.9142 + sobel:core/FRAME:not#24 mgc_not_3 0.0000 6.9142 + sobel:core/FRAME:not#24.itm 0.0000 6.9142 + sobel:core/FRAME:conc#46 0.0000 6.9142 + sobel:core/FRAME:conc#46.itm 0.0000 6.9142 + sobel:core/FRAME:acc#39 mgc_add_5_0_5_1_7 0.6126 7.5269 + sobel:core/FRAME:acc#39.itm 0.0000 7.5269 + sobel:core/FRAME:slc#6 0.0000 7.5269 + sobel:core/FRAME:slc#6.itm 0.0000 7.5269 + sobel:core/FRAME:not#54 mgc_not_1 0.0000 7.5269 + sobel:core/FRAME:not#54.itm 0.0000 7.5269 + sobel:core/conc#126 0.0000 7.5269 + sobel:core/conc#126.itm 0.0000 7.5269 + sobel:core/FRAME:acc#32 mgc_add_3_0_3_0_4 0.7609 8.2878 + sobel:core/FRAME:acc#32.itm 0.0000 8.2878 + sobel:core/FRAME:acc#33 mgc_add_4_0_4_0_5 0.8536 9.1413 + sobel:core/FRAME:acc#33.itm 0.0000 9.1413 + sobel:core/FRAME:acc#34 mgc_add_5_0_5_1_7 0.6126 9.7540 + sobel:core/FRAME:acc#34.itm 0.0000 9.7540 + sobel:core/FRAME:acc#35 mgc_add_6_0_5_1_8 0.6934 10.4474 + sobel:core/FRAME:acc#35.itm 0.0000 10.4474 + sobel:core/FRAME:acc#36 mgc_add_9_0_8_1_10 1.0725 11.5198 + sobel:core/FRAME:acc#36.itm 0.0000 11.5198 + sobel:core/FRAME:acc#37 mgc_add_11_0_10_1_12 1.2076 12.7275 + sobel:core/FRAME:acc#37.sdt 0.0000 12.7275 + sobel:core/slc(FRAME:acc#37.sdt)#1 0.0000 12.7275 + sobel:core/slc(FRAME:acc#37.sdt)#1.itm 0.0000 12.7275 + sobel:core/FRAME:acc#61 mgc_add_12_0_11_1_12 1.4360 14.1634 + sobel:core/FRAME:acc#61.psp 0.0000 14.1634 + sobel:core/slc(FRAME:acc#61.psp)#2 0.0000 14.1634 + sobel:core/slc(FRAME:acc#61.psp)#2.itm 0.0000 14.1634 + sobel:core/FRAME:or#4 mgc_or_1_2 0.2679 14.4313 + sobel:core/FRAME:or#4.itm 0.0000 14.4313 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#3 mgc_reg_pos_1_1_0_0_0_1_1 0.0000 14.4313 + + 7 sobel:core/reg(ACC1:slc(regs.regs(2))#12.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 14.4313 5.5687 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2))#12.itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2))#12.itm 0.0000 0.0000 + sobel:core/conc#140 0.0000 0.0000 + sobel:core/conc#140.itm 0.0000 0.0000 + sobel:core/ACC1:acc#49 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#49.itm 0.0000 1.2059 + sobel:core/ACC1:slc#5 0.0000 1.2059 + sobel:core/ACC1:slc#5.itm 0.0000 1.2059 + sobel:core/conc#138 0.0000 1.2059 + sobel:core/conc#138.itm 0.0000 1.2059 + sobel:core/ACC1:acc#51 mgc_add_12_1_12_1_13 1.2718 2.4777 + sobel:core/ACC1:acc#51.itm 0.0000 2.4777 + sobel:core/ACC1:slc#7 0.0000 2.4777 + sobel:core/ACC1:slc#7.itm 0.0000 2.4777 + sobel:core/ACC1:acc#42 mgc_add_12_1_12_1_13 1.2718 3.7496 + sobel:core/ACC1:acc#42.psp.sva 0.0000 3.7496 + sobel:core/slc(ACC1:acc#42.psp.sva)#7 0.0000 3.7496 + sobel:core/slc(ACC1:acc#42.psp.sva)#7.itm 0.0000 3.7496 + sobel:core/FRAME:acc#15 mgc_add_3_0_3_0_4 0.7609 4.5105 + sobel:core/FRAME:acc#15.itm 0.0000 4.5105 + sobel:core/FRAME:acc#17 mgc_add_4_0_4_0_5 0.8536 5.3640 + sobel:core/FRAME:acc#17.itm 0.0000 5.3640 + sobel:core/FRAME:acc#18 mgc_add_5_0_5_1_7 0.6126 5.9766 + sobel:core/FRAME:acc#18.sdt 0.0000 5.9766 + sobel:core/slc(FRAME:acc#18.sdt)#1 0.0000 5.9766 + sobel:core/slc(FRAME:acc#18.sdt)#1.itm 0.0000 5.9766 + sobel:core/FRAME:acc#49 mgc_add_5_0_5_0_5 0.9376 6.9142 + sobel:core/FRAME:acc#49.psp 0.0000 6.9142 + sobel:core/slc(FRAME:acc#49.psp)#4 0.0000 6.9142 + sobel:core/slc(FRAME:acc#49.psp)#4.itm 0.0000 6.9142 + sobel:core/FRAME:not#47 mgc_not_1 0.0000 6.9142 + sobel:core/FRAME:not#47.itm 0.0000 6.9142 + sobel:core/FRAME:conc#42 0.0000 6.9142 + sobel:core/FRAME:conc#42.itm 0.0000 6.9142 + sobel:core/FRAME:acc#26 mgc_add_5_0_5_1_7 0.6126 7.5269 + sobel:core/FRAME:acc#26.itm 0.0000 7.5269 + sobel:core/FRAME:slc#5 0.0000 7.5269 + sobel:core/FRAME:slc#5.itm 0.0000 7.5269 + sobel:core/FRAME:not#52 mgc_not_1 0.0000 7.5269 + sobel:core/FRAME:not#52.itm 0.0000 7.5269 + sobel:core/conc#117 0.0000 7.5269 + sobel:core/conc#117.itm 0.0000 7.5269 + sobel:core/FRAME:acc#19 mgc_add_3_0_3_0_4 0.7609 8.2878 + sobel:core/FRAME:acc#19.itm 0.0000 8.2878 + sobel:core/FRAME:acc#20 mgc_add_4_0_4_0_5 0.8536 9.1413 + sobel:core/FRAME:acc#20.itm 0.0000 9.1413 + sobel:core/FRAME:acc#21 mgc_add_5_0_5_1_7 0.6126 9.7540 + sobel:core/FRAME:acc#21.itm 0.0000 9.7540 + sobel:core/FRAME:acc#22 mgc_add_6_0_5_1_8 0.6934 10.4474 + sobel:core/FRAME:acc#22.itm 0.0000 10.4474 + sobel:core/FRAME:acc#23 mgc_add_9_0_8_1_10 1.0725 11.5198 + sobel:core/FRAME:acc#23.itm 0.0000 11.5198 + sobel:core/FRAME:acc#24 mgc_add_11_0_10_1_12 1.2076 12.7275 + sobel:core/FRAME:acc#24.sdt 0.0000 12.7275 + sobel:core/slc(FRAME:acc#24.sdt)#1 0.0000 12.7275 + sobel:core/slc(FRAME:acc#24.sdt)#1.itm 0.0000 12.7275 + sobel:core/FRAME:acc mgc_add_12_0_11_1_12 1.4360 14.1634 + sobel:core/FRAME:acc.psp 0.0000 14.1634 + sobel:core/slc(FRAME:acc.psp)#2 0.0000 14.1634 + sobel:core/slc(FRAME:acc.psp)#2.itm 0.0000 14.1634 + sobel:core/FRAME:or#3 mgc_or_5_2 0.2679 14.4313 + sobel:core/FRAME:or#3.itm 0.0000 14.4313 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 mgc_reg_pos_5_1_0_0_0_1_1 0.0000 14.4313 + + 8 sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 14.4313 5.5687 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/vin:rsc:mgc_in_wire.d 0.0000 0.0000 + sobel:core/slc(regs.regs(0).sva#4) 0.0000 0.0000 + sobel:core/slc(regs.regs(0).sva#4).itm 0.0000 0.0000 + sobel:core/ACC1:not#22 mgc_not_10 0.0000 0.0000 + sobel:core/ACC1:not#22.itm 0.0000 0.0000 + sobel:core/conc#142 0.0000 0.0000 + sobel:core/conc#142.itm 0.0000 0.0000 + sobel:core/ACC1:acc#48 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#48.itm 0.0000 1.2059 + sobel:core/ACC1:slc#4 0.0000 1.2059 + sobel:core/ACC1:slc#4.itm 0.0000 1.2059 + sobel:core/conc#141 0.0000 1.2059 + sobel:core/conc#141.itm 0.0000 1.2059 + sobel:core/ACC1:acc#51 mgc_add_12_1_12_1_13 1.2718 2.4777 + sobel:core/ACC1:acc#51.itm 0.0000 2.4777 + sobel:core/ACC1:slc#7 0.0000 2.4777 + sobel:core/ACC1:slc#7.itm 0.0000 2.4777 + sobel:core/ACC1:acc#42 mgc_add_12_1_12_1_13 1.2718 3.7496 + sobel:core/ACC1:acc#42.psp.sva 0.0000 3.7496 + sobel:core/slc(ACC1:acc#42.psp.sva)#7 0.0000 3.7496 + sobel:core/slc(ACC1:acc#42.psp.sva)#7.itm 0.0000 3.7496 + sobel:core/FRAME:acc#15 mgc_add_3_0_3_0_4 0.7609 4.5105 + sobel:core/FRAME:acc#15.itm 0.0000 4.5105 + sobel:core/FRAME:acc#17 mgc_add_4_0_4_0_5 0.8536 5.3640 + sobel:core/FRAME:acc#17.itm 0.0000 5.3640 + sobel:core/FRAME:acc#18 mgc_add_5_0_5_1_7 0.6126 5.9766 + sobel:core/FRAME:acc#18.sdt 0.0000 5.9766 + sobel:core/slc(FRAME:acc#18.sdt)#1 0.0000 5.9766 + sobel:core/slc(FRAME:acc#18.sdt)#1.itm 0.0000 5.9766 + sobel:core/FRAME:acc#49 mgc_add_5_0_5_0_5 0.9376 6.9142 + sobel:core/FRAME:acc#49.psp 0.0000 6.9142 + sobel:core/slc(FRAME:acc#49.psp)#4 0.0000 6.9142 + sobel:core/slc(FRAME:acc#49.psp)#4.itm 0.0000 6.9142 + sobel:core/FRAME:not#47 mgc_not_1 0.0000 6.9142 + sobel:core/FRAME:not#47.itm 0.0000 6.9142 + sobel:core/FRAME:conc#42 0.0000 6.9142 + sobel:core/FRAME:conc#42.itm 0.0000 6.9142 + sobel:core/FRAME:acc#26 mgc_add_5_0_5_1_7 0.6126 7.5269 + sobel:core/FRAME:acc#26.itm 0.0000 7.5269 + sobel:core/FRAME:slc#5 0.0000 7.5269 + sobel:core/FRAME:slc#5.itm 0.0000 7.5269 + sobel:core/FRAME:not#52 mgc_not_1 0.0000 7.5269 + sobel:core/FRAME:not#52.itm 0.0000 7.5269 + sobel:core/conc#117 0.0000 7.5269 + sobel:core/conc#117.itm 0.0000 7.5269 + sobel:core/FRAME:acc#19 mgc_add_3_0_3_0_4 0.7609 8.2878 + sobel:core/FRAME:acc#19.itm 0.0000 8.2878 + sobel:core/FRAME:acc#20 mgc_add_4_0_4_0_5 0.8536 9.1413 + sobel:core/FRAME:acc#20.itm 0.0000 9.1413 + sobel:core/FRAME:acc#21 mgc_add_5_0_5_1_7 0.6126 9.7540 + sobel:core/FRAME:acc#21.itm 0.0000 9.7540 + sobel:core/FRAME:acc#22 mgc_add_6_0_5_1_8 0.6934 10.4474 + sobel:core/FRAME:acc#22.itm 0.0000 10.4474 + sobel:core/FRAME:acc#23 mgc_add_9_0_8_1_10 1.0725 11.5198 + sobel:core/FRAME:acc#23.itm 0.0000 11.5198 + sobel:core/FRAME:acc#24 mgc_add_11_0_10_1_12 1.2076 12.7275 + sobel:core/FRAME:acc#24.sdt 0.0000 12.7275 + sobel:core/slc(FRAME:acc#24.sdt)#1 0.0000 12.7275 + sobel:core/slc(FRAME:acc#24.sdt)#1.itm 0.0000 12.7275 + sobel:core/FRAME:acc mgc_add_12_0_11_1_12 1.4360 14.1634 + sobel:core/FRAME:acc.psp 0.0000 14.1634 + sobel:core/slc(FRAME:acc.psp)#2 0.0000 14.1634 + sobel:core/slc(FRAME:acc.psp)#2.itm 0.0000 14.1634 + sobel:core/FRAME:or#3 mgc_or_5_2 0.2679 14.4313 + sobel:core/FRAME:or#3.itm 0.0000 14.4313 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 mgc_reg_pos_5_1_0_0_0_1_1 0.0000 14.4313 + + 9 sobel:core/reg(ACC1:slc(regs.regs(2))#14.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#3 14.4313 5.5687 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2))#14.itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2))#14.itm 0.0000 0.0000 + sobel:core/conc#131 0.0000 0.0000 + sobel:core/conc#131.itm 0.0000 0.0000 + sobel:core/ACC1:acc#53 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#53.itm 0.0000 1.2059 + sobel:core/ACC1:slc#9 0.0000 1.2059 + sobel:core/ACC1:slc#9.itm 0.0000 1.2059 + sobel:core/conc#130 0.0000 1.2059 + sobel:core/conc#130.itm 0.0000 1.2059 + sobel:core/ACC1:acc#55 mgc_add_12_1_12_1_13 1.2718 2.4777 + sobel:core/ACC1:acc#55.itm 0.0000 2.4777 + sobel:core/ACC1:slc#11 0.0000 2.4777 + sobel:core/ACC1:slc#11.itm 0.0000 2.4777 + sobel:core/ACC1:acc#43 mgc_add_12_1_12_1_13 1.2718 3.7496 + sobel:core/ACC1:acc#43.psp.sva 0.0000 3.7496 + sobel:core/slc(ACC1:acc#43.psp.sva)#8 0.0000 3.7496 + sobel:core/slc(ACC1:acc#43.psp.sva)#8.itm 0.0000 3.7496 + sobel:core/FRAME:not#35 mgc_not_3 0.0000 3.7496 + sobel:core/FRAME:not#35.itm 0.0000 3.7496 + sobel:core/FRAME:acc#28 mgc_add_3_0_3_0_4 0.7609 4.5105 + sobel:core/FRAME:acc#28.itm 0.0000 4.5105 + sobel:core/FRAME:acc#30 mgc_add_4_0_4_0_5 0.8536 5.3640 + sobel:core/FRAME:acc#30.itm 0.0000 5.3640 + sobel:core/FRAME:acc#31 mgc_add_5_0_5_1_7 0.6126 5.9766 + sobel:core/FRAME:acc#31.sdt 0.0000 5.9766 + sobel:core/slc(FRAME:acc#31.sdt)#1 0.0000 5.9766 + sobel:core/slc(FRAME:acc#31.sdt)#1.itm 0.0000 5.9766 + sobel:core/FRAME:acc#55 mgc_add_5_0_5_0_5 0.9376 6.9142 + sobel:core/FRAME:acc#55.psp 0.0000 6.9142 + sobel:core/slc(FRAME:acc#55.psp)#2 0.0000 6.9142 + sobel:core/slc(FRAME:acc#55.psp)#2.itm 0.0000 6.9142 + sobel:core/FRAME:not#24 mgc_not_3 0.0000 6.9142 + sobel:core/FRAME:not#24.itm 0.0000 6.9142 + sobel:core/FRAME:conc#46 0.0000 6.9142 + sobel:core/FRAME:conc#46.itm 0.0000 6.9142 + sobel:core/FRAME:acc#39 mgc_add_5_0_5_1_7 0.6126 7.5269 + sobel:core/FRAME:acc#39.itm 0.0000 7.5269 + sobel:core/FRAME:slc#6 0.0000 7.5269 + sobel:core/FRAME:slc#6.itm 0.0000 7.5269 + sobel:core/FRAME:not#54 mgc_not_1 0.0000 7.5269 + sobel:core/FRAME:not#54.itm 0.0000 7.5269 + sobel:core/conc#126 0.0000 7.5269 + sobel:core/conc#126.itm 0.0000 7.5269 + sobel:core/FRAME:acc#32 mgc_add_3_0_3_0_4 0.7609 8.2878 + sobel:core/FRAME:acc#32.itm 0.0000 8.2878 + sobel:core/FRAME:acc#33 mgc_add_4_0_4_0_5 0.8536 9.1413 + sobel:core/FRAME:acc#33.itm 0.0000 9.1413 + sobel:core/FRAME:acc#34 mgc_add_5_0_5_1_7 0.6126 9.7540 + sobel:core/FRAME:acc#34.itm 0.0000 9.7540 + sobel:core/FRAME:acc#35 mgc_add_6_0_5_1_8 0.6934 10.4474 + sobel:core/FRAME:acc#35.itm 0.0000 10.4474 + sobel:core/FRAME:acc#36 mgc_add_9_0_8_1_10 1.0725 11.5198 + sobel:core/FRAME:acc#36.itm 0.0000 11.5198 + sobel:core/FRAME:acc#37 mgc_add_11_0_10_1_12 1.2076 12.7275 + sobel:core/FRAME:acc#37.sdt 0.0000 12.7275 + sobel:core/slc(FRAME:acc#37.sdt)#1 0.0000 12.7275 + sobel:core/slc(FRAME:acc#37.sdt)#1.itm 0.0000 12.7275 + sobel:core/FRAME:acc#61 mgc_add_12_0_11_1_12 1.4360 14.1634 + sobel:core/FRAME:acc#61.psp 0.0000 14.1634 + sobel:core/slc(FRAME:acc#61.psp)#2 0.0000 14.1634 + sobel:core/slc(FRAME:acc#61.psp)#2.itm 0.0000 14.1634 + sobel:core/FRAME:or#4 mgc_or_1_2 0.2679 14.4313 + sobel:core/FRAME:or#4.itm 0.0000 14.4313 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#3 mgc_reg_pos_1_1_0_0_0_1_1 0.0000 14.4313 + + 10 sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 14.4313 5.5687 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2))#11.itm 0.0000 0.0000 + sobel:core/conc#139 0.0000 0.0000 + sobel:core/conc#139.itm 0.0000 0.0000 + sobel:core/ACC1:acc#49 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#49.itm 0.0000 1.2059 + sobel:core/ACC1:slc#5 0.0000 1.2059 + sobel:core/ACC1:slc#5.itm 0.0000 1.2059 + sobel:core/conc#138 0.0000 1.2059 + sobel:core/conc#138.itm 0.0000 1.2059 + sobel:core/ACC1:acc#51 mgc_add_12_1_12_1_13 1.2718 2.4777 + sobel:core/ACC1:acc#51.itm 0.0000 2.4777 + sobel:core/ACC1:slc#7 0.0000 2.4777 + sobel:core/ACC1:slc#7.itm 0.0000 2.4777 + sobel:core/ACC1:acc#42 mgc_add_12_1_12_1_13 1.2718 3.7496 + sobel:core/ACC1:acc#42.psp.sva 0.0000 3.7496 + sobel:core/slc(ACC1:acc#42.psp.sva)#8 0.0000 3.7496 + sobel:core/slc(ACC1:acc#42.psp.sva)#8.itm 0.0000 3.7496 + sobel:core/FRAME:not#33 mgc_not_3 0.0000 3.7496 + sobel:core/FRAME:not#33.itm 0.0000 3.7496 + sobel:core/FRAME:acc#15 mgc_add_3_0_3_0_4 0.7609 4.5105 + sobel:core/FRAME:acc#15.itm 0.0000 4.5105 + sobel:core/FRAME:acc#17 mgc_add_4_0_4_0_5 0.8536 5.3640 + sobel:core/FRAME:acc#17.itm 0.0000 5.3640 + sobel:core/FRAME:acc#18 mgc_add_5_0_5_1_7 0.6126 5.9766 + sobel:core/FRAME:acc#18.sdt 0.0000 5.9766 + sobel:core/slc(FRAME:acc#18.sdt)#1 0.0000 5.9766 + sobel:core/slc(FRAME:acc#18.sdt)#1.itm 0.0000 5.9766 + sobel:core/FRAME:acc#49 mgc_add_5_0_5_0_5 0.9376 6.9142 + sobel:core/FRAME:acc#49.psp 0.0000 6.9142 + sobel:core/slc(FRAME:acc#49.psp)#4 0.0000 6.9142 + sobel:core/slc(FRAME:acc#49.psp)#4.itm 0.0000 6.9142 + sobel:core/FRAME:not#47 mgc_not_1 0.0000 6.9142 + sobel:core/FRAME:not#47.itm 0.0000 6.9142 + sobel:core/FRAME:conc#42 0.0000 6.9142 + sobel:core/FRAME:conc#42.itm 0.0000 6.9142 + sobel:core/FRAME:acc#26 mgc_add_5_0_5_1_7 0.6126 7.5269 + sobel:core/FRAME:acc#26.itm 0.0000 7.5269 + sobel:core/FRAME:slc#5 0.0000 7.5269 + sobel:core/FRAME:slc#5.itm 0.0000 7.5269 + sobel:core/FRAME:not#52 mgc_not_1 0.0000 7.5269 + sobel:core/FRAME:not#52.itm 0.0000 7.5269 + sobel:core/conc#117 0.0000 7.5269 + sobel:core/conc#117.itm 0.0000 7.5269 + sobel:core/FRAME:acc#19 mgc_add_3_0_3_0_4 0.7609 8.2878 + sobel:core/FRAME:acc#19.itm 0.0000 8.2878 + sobel:core/FRAME:acc#20 mgc_add_4_0_4_0_5 0.8536 9.1413 + sobel:core/FRAME:acc#20.itm 0.0000 9.1413 + sobel:core/FRAME:acc#21 mgc_add_5_0_5_1_7 0.6126 9.7540 + sobel:core/FRAME:acc#21.itm 0.0000 9.7540 + sobel:core/FRAME:acc#22 mgc_add_6_0_5_1_8 0.6934 10.4474 + sobel:core/FRAME:acc#22.itm 0.0000 10.4474 + sobel:core/FRAME:acc#23 mgc_add_9_0_8_1_10 1.0725 11.5198 + sobel:core/FRAME:acc#23.itm 0.0000 11.5198 + sobel:core/FRAME:acc#24 mgc_add_11_0_10_1_12 1.2076 12.7275 + sobel:core/FRAME:acc#24.sdt 0.0000 12.7275 + sobel:core/slc(FRAME:acc#24.sdt)#1 0.0000 12.7275 + sobel:core/slc(FRAME:acc#24.sdt)#1.itm 0.0000 12.7275 + sobel:core/FRAME:acc mgc_add_12_0_11_1_12 1.4360 14.1634 + sobel:core/FRAME:acc.psp 0.0000 14.1634 + sobel:core/slc(FRAME:acc.psp)#2 0.0000 14.1634 + sobel:core/slc(FRAME:acc.psp)#2.itm 0.0000 14.1634 + sobel:core/FRAME:or#3 mgc_or_5_2 0.2679 14.4313 + sobel:core/FRAME:or#3.itm 0.0000 14.4313 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 mgc_reg_pos_5_1_0_0_0_1_1 0.0000 14.4313 + + + Register Input and Register-to-Output Slack + Clock period or pin-to-reg delay constraint (clk): 20.0 + Clock uncertainty constraint (clk) : 0.0 + + Instance Port Slack (Delay) Messages + --------------------------------------------- --------------------------- ------- ------- -------- + sobel:core/reg(ACC1:slc(regs.regs(2))#14.itm) slc(regs.regs(1).sva)#2.itm 20.0000 0.0000 + sobel:core/reg(ACC1:slc(regs.regs(2))#15.itm) slc(regs.regs(1).sva)#1.itm 20.0000 0.0000 + sobel:core/reg(ACC1:slc(regs.regs(2))#16.itm) slc(regs.regs(1).sva).itm 20.0000 0.0000 + sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) slc(regs.regs(1).sva)#5.itm 20.0000 0.0000 + sobel:core/reg(ACC1:slc(regs.regs(2))#12.itm) slc(regs.regs(1).sva)#4.itm 20.0000 0.0000 + sobel:core/reg(ACC1:slc(regs.regs(2))#13.itm) slc(regs.regs(1).sva)#3.itm 20.0000 0.0000 + sobel:core/reg(ACC1:slc(regs.regs(2)).itm) slc(regs.regs(1).sva)#8.itm 20.0000 0.0000 + sobel:core/reg(ACC1:slc(regs.regs(2))#9.itm) slc(regs.regs(1).sva)#7.itm 20.0000 0.0000 + sobel:core/reg(ACC1:slc(regs.regs(2))#10.itm) slc(regs.regs(1).sva)#6.itm 20.0000 0.0000 + sobel:core/reg(regs.regs(1).sva) vin:rsc:mgc_in_wire.d 5.5687 14.4313 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d) FRAME:or.itm 5.5687 14.4313 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#1 slc(FRAME:acc.psp)#1.itm 5.8366 14.1634 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 FRAME:or#3.itm 5.5687 14.4313 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#3 FRAME:or#4.itm 5.5687 14.4313 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#4 slc(FRAME:acc#61.psp)#1.itm 5.8366 14.1634 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#5 slc(FRAME:acc#37.sdt).itm 7.2725 12.7275 + sobel vout:rsc.z 20.0000 0.0000 + + Operator Bitwidth Summary + Operation Size (bits) Count + ---------- ----------- ----- + add + - 13 6 + - 12 10 + - 11 3 + - 10 5 + - 8 2 + - 7 9 + - 6 1 + - 5 9 + - 4 12 + mul + - 11 3 + - 9 3 + not + - 10 9 + - 3 12 + - 1 11 + or + - 2 3 + read_port + - 90 1 + reg + - 90 1 + - 10 10 + - 9 1 + - 5 1 + - 4 1 + - 1 2 + write_port + - 30 1 + + End of Report |