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Diffstat (limited to 'Sobel/sobel.v2/cycle.rpt')
| -rw-r--r-- | Sobel/sobel.v2/cycle.rpt | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/Sobel/sobel.v2/cycle.rpt b/Sobel/sobel.v2/cycle.rpt new file mode 100644 index 0000000..7d24aaf --- /dev/null +++ b/Sobel/sobel.v2/cycle.rpt @@ -0,0 +1,85 @@ +-- Catapult University Version: Report +-- ---------------------------- --------------------------------------------------- +-- Version: 2011a.126 Production Release +-- Build Date: Wed Aug 8 00:52:07 PDT 2012 + +-- Generated by: mg3115@EEWS104A-013 +-- Generated date: Tue Mar 08 14:09:35 +0000 2016 + +Solution Settings: sobel.v2 + Current state: schedule + Project: Sobel + + Design Input Files Specified + $PROJECT_HOME/sobel.h + $MGC_HOME/shared/include/ac_int.h + $PROJECT_HOME/bmp_io.cpp + $PROJECT_HOME/bmp_io.h + $PROJECT_HOME/tb_blur.cpp + $MGC_HOME/shared/include/mc_testbench.h + $MGC_HOME/shared/include/mc_scverify.h + $MGC_HOME/shared/include/ac_int.h + $PROJECT_HOME/sobel.h + $PROJECT_HOME/bmp_io.h + $PROJECT_HOME/bmp_io.h + $PROJECT_HOME/shift_class.h + $PROJECT_HOME/sobel.cpp + $MGC_HOME/shared/include/ac_fixed.h + $MGC_HOME/shared/include/ac_int.h + $PROJECT_HOME/sobel.h + $PROJECT_HOME/shift_class.h + + Processes/Blocks in Design + Process Real Operation(s) count Latency Throughput Reset Length II Comments + ------------- ----------------------- ------- ---------- ------------ -- -------- + /sobel/core 161 921601 921600 0 1 + Design Total: 161 921601 921600 0 0 + + Clock Information + Clock Signal Edge Period Sharing Alloc (%) Uncertainty Used by Processes/Blocks + ------------ ------ ------ ----------------- ----------- ------------------------ + clk rising 20.000 20.00 0.000000 /sobel/core + + I/O Data Ranges + Port Mode DeclType DeclWidth DeclRange ActType ActWidth ActRange + ---------- ---- -------- --------- --------- ------- -------- -------- + vin:rsc.z IN Unsigned 90 + clk IN Unsigned 1 + en IN Unsigned 1 + arst_n IN Unsigned 1 + vout:rsc.z OUT Unsigned 30 + + Memory Resources + Resource Name: /sobel/vin:rsc + Memory Component: mgc_in_wire Size: 1 x 90 + External: true Packing Mode: sidebyside + Memory Map: + Variable Indices Phys Memory Address + ---------- ------- ----------------------- + /sobel/vin 0:89 00000000-00000000 (0-0) + + Resource Name: /sobel/vout:rsc + Memory Component: mgc_out_stdreg Size: 1 x 30 + External: true Packing Mode: sidebyside + Memory Map: + Variable Indices Phys Memory Address + ----------- ------- ----------------------- + /sobel/vout 0:29 00000000-00000000 (0-0) + + Multi-Cycle (Combinational) Component Usage + Instance Component Name Delay + -------- -------------- ----- + + Loops + Process Loop Iterations C-Steps Total Cycles Duration Unroll Init Comments + ----------- ---------------- ---------- ------- ------------- --------- ------ ---- -------- + /sobel/core core:rlp Infinite 0 921602 18.43 ms + /sobel/core main Infinite 3 921602 18.43 ms 1 + + Loop Execution Profile + Process Loop Total Cycles % of Overall Design Cycles Throughput Cycles Comments + ----------- ---------------- ------------ -------------------------- ----------------- -------- + /sobel/core core:rlp 0 0.00 921600 + /sobel/core main 921602 100.00 921600 + + End of Report |