diff options
Diffstat (limited to 'Sobel/sobel.v5/rtl.rpt')
| -rw-r--r-- | Sobel/sobel.v5/rtl.rpt | 793 |
1 files changed, 793 insertions, 0 deletions
diff --git a/Sobel/sobel.v5/rtl.rpt b/Sobel/sobel.v5/rtl.rpt new file mode 100644 index 0000000..2264c8c --- /dev/null +++ b/Sobel/sobel.v5/rtl.rpt @@ -0,0 +1,793 @@ +-- Catapult University Version: Report +-- ---------------------------- --------------------------------------------------- +-- Version: 2011a.126 Production Release +-- Build Date: Wed Aug 8 00:52:07 PDT 2012 + +-- Generated by: mg3115@EEWS104A-013 +-- Generated date: Tue Mar 08 14:36:28 +0000 2016 + +Solution Settings: sobel.v5 + Current state: extract + Project: Sobel + + Design Input Files Specified + $PROJECT_HOME/sobel.h + $MGC_HOME/shared/include/ac_int.h + $PROJECT_HOME/bmp_io.cpp + $PROJECT_HOME/bmp_io.h + $PROJECT_HOME/tb_blur.cpp + $MGC_HOME/shared/include/mc_testbench.h + $MGC_HOME/shared/include/mc_scverify.h + $MGC_HOME/shared/include/ac_int.h + $PROJECT_HOME/sobel.h + $PROJECT_HOME/bmp_io.h + $PROJECT_HOME/bmp_io.h + $PROJECT_HOME/shift_class.h + $PROJECT_HOME/sobel.cpp + $MGC_HOME/shared/include/ac_fixed.h + $MGC_HOME/shared/include/ac_int.h + $PROJECT_HOME/sobel.h + $PROJECT_HOME/shift_class.h + + Processes/Blocks in Design + Process Real Operation(s) count Latency Throughput Reset Length II Comments + ------------- ----------------------- ------- ---------- ------------ -- -------- + /sobel/core 56 307200 307200 0 1 + Design Total: 56 307200 307200 0 0 + + Bill Of Materials (Datapath) + Component Name Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign + --------------------------------------- ---------- --------------------------- ---------- ----- ---------- ----------- + [Lib: mgc_Altera-Cyclone-III-6_beh_psr] + mgc_add(1,0,1,0,2) 2.319 0.000 2.319 0.506 2 2 + mgc_add(10,0,10,1,11) 11.000 0.000 11.000 1.139 1 1 + mgc_add(10,1,10,1,11) 11.000 0.000 11.000 1.139 6 4 + mgc_add(11,1,11,1,12) 12.000 0.000 12.000 1.206 6 6 + mgc_add(12,1,12,1,13) 13.000 0.000 13.000 1.272 1 1 + mgc_add(13,1,12,1,14) 14.000 0.000 14.000 1.338 1 1 + mgc_add(19,0,2,1,19) 20.000 0.000 20.000 1.908 1 0 + mgc_add(2,0,2,0,3) 3.311 0.000 3.311 0.653 3 1 + mgc_add(2,1,1,1,3) 3.000 0.000 3.000 0.495 2 2 + mgc_add(3,0,3,1,4) 4.000 0.000 4.000 0.598 2 1 + mgc_add(4,0,4,1,6) 5.000 0.000 5.000 0.529 3 2 + mgc_add(4,1,2,1,5) 5.000 0.000 5.000 0.697 1 0 + mgc_add(5,0,5,1,6) 6.000 0.000 6.000 0.775 4 4 + mgc_add(6,0,6,1,7) 7.000 0.000 7.000 0.854 1 1 + mgc_add(7,0,6,0,8) 8.271 0.000 8.271 1.093 0 1 + mgc_add(7,0,7,0,7) 8.267 0.000 8.267 1.091 1 1 + mgc_add(8,0,7,0,8) 9.262 0.000 9.262 1.165 1 0 + mgc_add(9,0,6,1,10) 10.000 0.000 10.000 1.076 2 1 + mgc_and(19,2) 13.867 0.000 13.867 0.263 1 0 + mgc_mul(4,0,5,0,9) 330.250 2.000 10.250 2.700 1 1 + mgc_not(1) 0.000 0.000 0.000 0.000 0 1 + mgc_not(10) 0.000 0.000 0.000 0.000 0 3 + mgc_not(2) 0.000 0.000 0.000 0.000 0 1 + mgc_not(3) 0.000 0.000 0.000 0.000 0 1 + mgc_or(10,2) 7.298 0.000 7.298 0.268 1 1 + mgc_or(6,2) 4.379 0.000 4.379 0.268 1 1 + mgc_reg_pos(10,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 8 + mgc_reg_pos(30,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 2 + mgc_reg_pos(6,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 1 + [Lib: mgc_ioport] + mgc_in_wire(1,90) 0.000 0.000 0.000 0.000 1 1 + mgc_out_stdreg(2,30) 0.000 0.000 0.000 0.000 1 1 + + TOTAL AREA (After Assignment): 581.415 2.000 261.000 + + Area Scores + Post-Scheduling Post-DP & FSM Post-Assignment + ----------------- --------------- -------------- --------------- + Total Area Score: 668.9 581.4 581.4 + Total Reg: 0.0 0.0 0.0 + + DataPath: 668.9 (100%) 581.4 (100%) 581.4 (100%) + MUX: 0.0 0.0 0.0 + FUNC: 643.4 (96%) 569.7 (98%) 569.7 (98%) + LOGIC: 25.5 (4%) 11.7 (2%) 11.7 (2%) + BUFFER: 0.0 0.0 0.0 + MEM: 0.0 0.0 0.0 + ROM: 0.0 0.0 0.0 + REG: 0.0 0.0 0.0 + + + FSM: 0.0 0.0 0.0 + FSM-REG: 0.0 0.0 0.0 + FSM-COMB: 0.0 0.0 0.0 + + + Register-to-Variable Mappings + Register Size(bits) Gated Register CG Opt Done Variables + ------------------------------------ ---------- -------------- ----------- ----------------------------------------------------- + regs.regs(1)#1.sva 30 Y regs.regs(1)#1.sva + regs.regs(1).sg2.sva 30 Y regs.regs(1).sg2.sva + ACC1:slc(regs.regs(2)#1)#1.itm 10 Y ACC1:slc(regs.regs(2)#1)#1.itm + ACC1:slc(regs.regs(2)#1)#2.itm 10 Y ACC1:slc(regs.regs(2)#1)#2.itm + ACC1:slc(regs.regs(2)#1).itm 10 Y ACC1:slc(regs.regs(2)#1).itm + ACC1:slc(regs.regs(2).sg2)#1.itm 10 Y ACC1:slc(regs.regs(2).sg2)#1.itm + ACC1:slc(regs.regs(2).sg2)#2.itm 10 Y ACC1:slc(regs.regs(2).sg2)#2.itm + ACC1:slc(regs.regs(2).sg2).itm 10 Y ACC1:slc(regs.regs(2).sg2).itm + reg(vout:rsc:mgc_out_stdreg.d).tmp 10 Y reg(vout:rsc:mgc_out_stdreg.d).tmp + reg(vout:rsc:mgc_out_stdreg.d).tmp#3 10 Y reg(vout:rsc:mgc_out_stdreg.d).tmp#3 + reg(vout:rsc:mgc_out_stdreg.d).tmp#2 6 Y reg(vout:rsc:mgc_out_stdreg.d).tmp#2 + + Total: 146 146 0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) + + Timing Report + Critical Path + Max Delay: 14.432002 + Slack: 5.567997999999999 + + Path Startpoint Endpoint Delay Slack + -------------------------------------------------- ------------------------------------------------ ------------------------------------------- ------- ------- + 1 sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d) 14.4320 5.5680 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2).sg2).itm 0.0000 0.0000 + sobel:core/conc 0.0000 0.0000 + sobel:core/conc.itm 0.0000 0.0000 + sobel:core/ACC1:acc#36 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#36.itm 0.0000 1.2059 + sobel:core/ACC1:slc#3 0.0000 1.2059 + sobel:core/ACC1:slc#3.itm 0.0000 1.2059 + sobel:core/ACC1:acc#41 mgc_add_11_1_11_1_12 1.2059 2.4119 + sobel:core/ACC1:acc#41.itm 0.0000 2.4119 + sobel:core/ACC1:acc#43 mgc_add_12_1_12_1_13 1.2718 3.6837 + sobel:core/ACC1:acc#43.itm 0.0000 3.6837 + sobel:core/ACC1:acc mgc_add_13_1_12_1_14 1.3384 5.0221 + sobel:core/ACC1:acc.itm 0.0000 5.0221 + sobel:core/ACC1:slc 0.0000 5.0221 + sobel:core/ACC1:slc.psp.sva 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#6 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#6.itm 0.0000 5.0221 + sobel:core/FRAME:acc#31 mgc_add_1_0_1_0_2 0.5058 5.5278 + sobel:core/FRAME:acc#31.itm 0.0000 5.5278 + sobel:core/FRAME:conc#29 0.0000 5.5278 + sobel:core/FRAME:conc#29.itm 0.0000 5.5278 + sobel:core/FRAME:acc#11 mgc_add_4_0_4_1_6 0.5286 6.0564 + sobel:core/FRAME:acc#11.itm 0.0000 6.0564 + sobel:core/FRAME:acc#13 mgc_add_5_0_5_1_6 0.7751 6.8315 + sobel:core/FRAME:acc#13.itm 0.0000 6.8315 + sobel:core/FRAME:acc#14 mgc_add_6_0_6_1_7 0.8537 7.6852 + sobel:core/FRAME:acc#14.itm 0.0000 7.6852 + sobel:core/acc mgc_add_7_0_7_0_7 1.0910 8.7763 + sobel:core/acc.imod.sva 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#12 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#12.itm 0.0000 8.7763 + sobel:core/conc#55 0.0000 8.7763 + sobel:core/conc#55.itm 0.0000 8.7763 + sobel:core/FRAME:acc#16 mgc_add_5_0_5_1_6 0.7751 9.5514 + sobel:core/FRAME:acc#16.itm 0.0000 9.5514 + sobel:core/acc#3 mgc_add_5_0_5_1_6 0.7751 10.3265 + sobel:core/acc#3.itm 0.0000 10.3265 + sobel:core/FRAME:slc#5 0.0000 10.3265 + sobel:core/FRAME:slc#5.itm 0.0000 10.3265 + sobel:core/FRAME:acc#18 mgc_add_2_1_1_1_3 0.4952 10.8217 + sobel:core/FRAME:acc#18.itm 0.0000 10.8217 + sobel:core/FRAME:acc#20 mgc_add_3_0_3_1_4 0.5984 11.4202 + sobel:core/FRAME:acc#20.itm 0.0000 11.4202 + sobel:core/FRAME:acc#21 mgc_add_4_0_4_1_6 0.5286 11.9487 + sobel:core/FRAME:acc#21.itm 0.0000 11.9487 + sobel:core/FRAME:acc#22 mgc_add_9_0_6_1_10 1.0764 13.0252 + sobel:core/FRAME:acc#22.cse 0.0000 13.0252 + sobel:core/FRAME:acc#3 mgc_add_10_1_10_1_11 1.1389 14.1641 + sobel:core/FRAME:acc#3.itm 0.0000 14.1641 + sobel:core/FRAME:or mgc_or_10_2 0.2679 14.4320 + sobel:core/FRAME:or.itm 0.0000 14.4320 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 14.4320 + + 2 sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 14.4320 5.5680 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2).sg2).itm 0.0000 0.0000 + sobel:core/conc 0.0000 0.0000 + sobel:core/conc.itm 0.0000 0.0000 + sobel:core/ACC1:acc#36 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#36.itm 0.0000 1.2059 + sobel:core/ACC1:slc#3 0.0000 1.2059 + sobel:core/ACC1:slc#3.itm 0.0000 1.2059 + sobel:core/ACC1:acc#41 mgc_add_11_1_11_1_12 1.2059 2.4119 + sobel:core/ACC1:acc#41.itm 0.0000 2.4119 + sobel:core/ACC1:acc#43 mgc_add_12_1_12_1_13 1.2718 3.6837 + sobel:core/ACC1:acc#43.itm 0.0000 3.6837 + sobel:core/ACC1:acc mgc_add_13_1_12_1_14 1.3384 5.0221 + sobel:core/ACC1:acc.itm 0.0000 5.0221 + sobel:core/ACC1:slc 0.0000 5.0221 + sobel:core/ACC1:slc.psp.sva 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#6 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#6.itm 0.0000 5.0221 + sobel:core/FRAME:acc#31 mgc_add_1_0_1_0_2 0.5058 5.5278 + sobel:core/FRAME:acc#31.itm 0.0000 5.5278 + sobel:core/FRAME:conc#29 0.0000 5.5278 + sobel:core/FRAME:conc#29.itm 0.0000 5.5278 + sobel:core/FRAME:acc#11 mgc_add_4_0_4_1_6 0.5286 6.0564 + sobel:core/FRAME:acc#11.itm 0.0000 6.0564 + sobel:core/FRAME:acc#13 mgc_add_5_0_5_1_6 0.7751 6.8315 + sobel:core/FRAME:acc#13.itm 0.0000 6.8315 + sobel:core/FRAME:acc#14 mgc_add_6_0_6_1_7 0.8537 7.6852 + sobel:core/FRAME:acc#14.itm 0.0000 7.6852 + sobel:core/acc mgc_add_7_0_7_0_7 1.0910 8.7763 + sobel:core/acc.imod.sva 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#12 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#12.itm 0.0000 8.7763 + sobel:core/conc#55 0.0000 8.7763 + sobel:core/conc#55.itm 0.0000 8.7763 + sobel:core/FRAME:acc#16 mgc_add_5_0_5_1_6 0.7751 9.5514 + sobel:core/FRAME:acc#16.itm 0.0000 9.5514 + sobel:core/acc#3 mgc_add_5_0_5_1_6 0.7751 10.3265 + sobel:core/acc#3.itm 0.0000 10.3265 + sobel:core/FRAME:slc#5 0.0000 10.3265 + sobel:core/FRAME:slc#5.itm 0.0000 10.3265 + sobel:core/FRAME:acc#18 mgc_add_2_1_1_1_3 0.4952 10.8217 + sobel:core/FRAME:acc#18.itm 0.0000 10.8217 + sobel:core/FRAME:acc#20 mgc_add_3_0_3_1_4 0.5984 11.4202 + sobel:core/FRAME:acc#20.itm 0.0000 11.4202 + sobel:core/FRAME:acc#21 mgc_add_4_0_4_1_6 0.5286 11.9487 + sobel:core/FRAME:acc#21.itm 0.0000 11.9487 + sobel:core/FRAME:acc#22 mgc_add_9_0_6_1_10 1.0764 13.0252 + sobel:core/FRAME:acc#22.cse 0.0000 13.0252 + sobel:core/FRAME:acc#5 mgc_add_10_0_10_1_11 1.1389 14.1641 + sobel:core/FRAME:acc#5.psp.sva 0.0000 14.1641 + sobel:core/slc(FRAME:acc#5.psp.sva)#2 0.0000 14.1641 + sobel:core/slc(FRAME:acc#5.psp.sva)#2.itm 0.0000 14.1641 + sobel:core/FRAME:or#3 mgc_or_6_2 0.2679 14.4320 + sobel:core/FRAME:or#3.itm 0.0000 14.4320 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 mgc_reg_pos_6_1_0_0_0_1_1 0.0000 14.4320 + + 3 sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d) 14.4320 5.5680 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2).sg2).itm 0.0000 0.0000 + sobel:core/conc 0.0000 0.0000 + sobel:core/conc.itm 0.0000 0.0000 + sobel:core/ACC1:acc#36 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#36.itm 0.0000 1.2059 + sobel:core/ACC1:slc#3 0.0000 1.2059 + sobel:core/ACC1:slc#3.itm 0.0000 1.2059 + sobel:core/ACC1:acc#41 mgc_add_11_1_11_1_12 1.2059 2.4119 + sobel:core/ACC1:acc#41.itm 0.0000 2.4119 + sobel:core/ACC1:acc#43 mgc_add_12_1_12_1_13 1.2718 3.6837 + sobel:core/ACC1:acc#43.itm 0.0000 3.6837 + sobel:core/ACC1:acc mgc_add_13_1_12_1_14 1.3384 5.0221 + sobel:core/ACC1:acc.itm 0.0000 5.0221 + sobel:core/ACC1:slc 0.0000 5.0221 + sobel:core/ACC1:slc.psp.sva 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#6 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#6.itm 0.0000 5.0221 + sobel:core/FRAME:acc#31 mgc_add_1_0_1_0_2 0.5058 5.5278 + sobel:core/FRAME:acc#31.itm 0.0000 5.5278 + sobel:core/FRAME:conc#29 0.0000 5.5278 + sobel:core/FRAME:conc#29.itm 0.0000 5.5278 + sobel:core/FRAME:acc#11 mgc_add_4_0_4_1_6 0.5286 6.0564 + sobel:core/FRAME:acc#11.itm 0.0000 6.0564 + sobel:core/FRAME:acc#13 mgc_add_5_0_5_1_6 0.7751 6.8315 + sobel:core/FRAME:acc#13.itm 0.0000 6.8315 + sobel:core/FRAME:acc#14 mgc_add_6_0_6_1_7 0.8537 7.6852 + sobel:core/FRAME:acc#14.itm 0.0000 7.6852 + sobel:core/acc mgc_add_7_0_7_0_7 1.0910 8.7763 + sobel:core/acc.imod.sva 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#12 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#12.itm 0.0000 8.7763 + sobel:core/conc#55 0.0000 8.7763 + sobel:core/conc#55.itm 0.0000 8.7763 + sobel:core/FRAME:acc#16 mgc_add_5_0_5_1_6 0.7751 9.5514 + sobel:core/FRAME:acc#16.itm 0.0000 9.5514 + sobel:core/acc#3 mgc_add_5_0_5_1_6 0.7751 10.3265 + sobel:core/acc#3.itm 0.0000 10.3265 + sobel:core/FRAME:slc#5 0.0000 10.3265 + sobel:core/FRAME:slc#5.itm 0.0000 10.3265 + sobel:core/FRAME:acc#18 mgc_add_2_1_1_1_3 0.4952 10.8217 + sobel:core/FRAME:acc#18.itm 0.0000 10.8217 + sobel:core/FRAME:acc#20 mgc_add_3_0_3_1_4 0.5984 11.4202 + sobel:core/FRAME:acc#20.itm 0.0000 11.4202 + sobel:core/FRAME:acc#21 mgc_add_4_0_4_1_6 0.5286 11.9487 + sobel:core/FRAME:acc#21.itm 0.0000 11.9487 + sobel:core/FRAME:acc#22 mgc_add_9_0_6_1_10 1.0764 13.0252 + sobel:core/FRAME:acc#22.cse 0.0000 13.0252 + sobel:core/FRAME:acc#5 mgc_add_10_0_10_1_11 1.1389 14.1641 + sobel:core/FRAME:acc#5.psp.sva 0.0000 14.1641 + sobel:core/slc(FRAME:acc#5.psp.sva)#4 0.0000 14.1641 + sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm 0.0000 14.1641 + sobel:core/conc#59 0.0000 14.1641 + sobel:core/conc#59.itm 0.0000 14.1641 + sobel:core/FRAME:or mgc_or_10_2 0.2679 14.4320 + sobel:core/FRAME:or.itm 0.0000 14.4320 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 14.4320 + + 4 sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d) 14.4320 5.5680 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2).sg2).itm 0.0000 0.0000 + sobel:core/conc 0.0000 0.0000 + sobel:core/conc.itm 0.0000 0.0000 + sobel:core/ACC1:acc#36 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#36.itm 0.0000 1.2059 + sobel:core/ACC1:slc#3 0.0000 1.2059 + sobel:core/ACC1:slc#3.itm 0.0000 1.2059 + sobel:core/ACC1:acc#41 mgc_add_11_1_11_1_12 1.2059 2.4119 + sobel:core/ACC1:acc#41.itm 0.0000 2.4119 + sobel:core/ACC1:acc#43 mgc_add_12_1_12_1_13 1.2718 3.6837 + sobel:core/ACC1:acc#43.itm 0.0000 3.6837 + sobel:core/ACC1:acc mgc_add_13_1_12_1_14 1.3384 5.0221 + sobel:core/ACC1:acc.itm 0.0000 5.0221 + sobel:core/ACC1:slc 0.0000 5.0221 + sobel:core/ACC1:slc.psp.sva 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#6 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#6.itm 0.0000 5.0221 + sobel:core/FRAME:acc#31 mgc_add_1_0_1_0_2 0.5058 5.5278 + sobel:core/FRAME:acc#31.itm 0.0000 5.5278 + sobel:core/FRAME:conc#29 0.0000 5.5278 + sobel:core/FRAME:conc#29.itm 0.0000 5.5278 + sobel:core/FRAME:acc#11 mgc_add_4_0_4_1_6 0.5286 6.0564 + sobel:core/FRAME:acc#11.itm 0.0000 6.0564 + sobel:core/FRAME:acc#13 mgc_add_5_0_5_1_6 0.7751 6.8315 + sobel:core/FRAME:acc#13.itm 0.0000 6.8315 + sobel:core/FRAME:acc#14 mgc_add_6_0_6_1_7 0.8537 7.6852 + sobel:core/FRAME:acc#14.itm 0.0000 7.6852 + sobel:core/acc mgc_add_7_0_7_0_7 1.0910 8.7763 + sobel:core/acc.imod.sva 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#10 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#10.itm 0.0000 8.7763 + sobel:core/conc#55 0.0000 8.7763 + sobel:core/conc#55.itm 0.0000 8.7763 + sobel:core/FRAME:acc#16 mgc_add_5_0_5_1_6 0.7751 9.5514 + sobel:core/FRAME:acc#16.itm 0.0000 9.5514 + sobel:core/acc#3 mgc_add_5_0_5_1_6 0.7751 10.3265 + sobel:core/acc#3.itm 0.0000 10.3265 + sobel:core/FRAME:slc#5 0.0000 10.3265 + sobel:core/FRAME:slc#5.itm 0.0000 10.3265 + sobel:core/FRAME:acc#18 mgc_add_2_1_1_1_3 0.4952 10.8217 + sobel:core/FRAME:acc#18.itm 0.0000 10.8217 + sobel:core/FRAME:acc#20 mgc_add_3_0_3_1_4 0.5984 11.4202 + sobel:core/FRAME:acc#20.itm 0.0000 11.4202 + sobel:core/FRAME:acc#21 mgc_add_4_0_4_1_6 0.5286 11.9487 + sobel:core/FRAME:acc#21.itm 0.0000 11.9487 + sobel:core/FRAME:acc#22 mgc_add_9_0_6_1_10 1.0764 13.0252 + sobel:core/FRAME:acc#22.cse 0.0000 13.0252 + sobel:core/FRAME:acc#5 mgc_add_10_0_10_1_11 1.1389 14.1641 + sobel:core/FRAME:acc#5.psp.sva 0.0000 14.1641 + sobel:core/slc(FRAME:acc#5.psp.sva)#4 0.0000 14.1641 + sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm 0.0000 14.1641 + sobel:core/conc#59 0.0000 14.1641 + sobel:core/conc#59.itm 0.0000 14.1641 + sobel:core/FRAME:or mgc_or_10_2 0.2679 14.4320 + sobel:core/FRAME:or.itm 0.0000 14.4320 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 14.4320 + + 5 sobel:core/reg(ACC1:slc(regs.regs(2).sg2)#2.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d) 14.4320 5.5680 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2).sg2)#2.itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2).sg2)#2.itm 0.0000 0.0000 + sobel:core/conc#51 0.0000 0.0000 + sobel:core/conc#51.itm 0.0000 0.0000 + sobel:core/ACC1:acc#35 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#35.itm 0.0000 1.2059 + sobel:core/ACC1:slc#2 0.0000 1.2059 + sobel:core/ACC1:slc#2.itm 0.0000 1.2059 + sobel:core/ACC1:acc#40 mgc_add_11_1_11_1_12 1.2059 2.4119 + sobel:core/ACC1:acc#40.itm 0.0000 2.4119 + sobel:core/ACC1:acc#43 mgc_add_12_1_12_1_13 1.2718 3.6837 + sobel:core/ACC1:acc#43.itm 0.0000 3.6837 + sobel:core/ACC1:acc mgc_add_13_1_12_1_14 1.3384 5.0221 + sobel:core/ACC1:acc.itm 0.0000 5.0221 + sobel:core/ACC1:slc 0.0000 5.0221 + sobel:core/ACC1:slc.psp.sva 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#6 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#6.itm 0.0000 5.0221 + sobel:core/FRAME:acc#31 mgc_add_1_0_1_0_2 0.5058 5.5278 + sobel:core/FRAME:acc#31.itm 0.0000 5.5278 + sobel:core/FRAME:conc#29 0.0000 5.5278 + sobel:core/FRAME:conc#29.itm 0.0000 5.5278 + sobel:core/FRAME:acc#11 mgc_add_4_0_4_1_6 0.5286 6.0564 + sobel:core/FRAME:acc#11.itm 0.0000 6.0564 + sobel:core/FRAME:acc#13 mgc_add_5_0_5_1_6 0.7751 6.8315 + sobel:core/FRAME:acc#13.itm 0.0000 6.8315 + sobel:core/FRAME:acc#14 mgc_add_6_0_6_1_7 0.8537 7.6852 + sobel:core/FRAME:acc#14.itm 0.0000 7.6852 + sobel:core/acc mgc_add_7_0_7_0_7 1.0910 8.7763 + sobel:core/acc.imod.sva 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#10 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#10.itm 0.0000 8.7763 + sobel:core/conc#55 0.0000 8.7763 + sobel:core/conc#55.itm 0.0000 8.7763 + sobel:core/FRAME:acc#16 mgc_add_5_0_5_1_6 0.7751 9.5514 + sobel:core/FRAME:acc#16.itm 0.0000 9.5514 + sobel:core/acc#3 mgc_add_5_0_5_1_6 0.7751 10.3265 + sobel:core/acc#3.itm 0.0000 10.3265 + sobel:core/FRAME:slc#5 0.0000 10.3265 + sobel:core/FRAME:slc#5.itm 0.0000 10.3265 + sobel:core/FRAME:acc#18 mgc_add_2_1_1_1_3 0.4952 10.8217 + sobel:core/FRAME:acc#18.itm 0.0000 10.8217 + sobel:core/FRAME:acc#20 mgc_add_3_0_3_1_4 0.5984 11.4202 + sobel:core/FRAME:acc#20.itm 0.0000 11.4202 + sobel:core/FRAME:acc#21 mgc_add_4_0_4_1_6 0.5286 11.9487 + sobel:core/FRAME:acc#21.itm 0.0000 11.9487 + sobel:core/FRAME:acc#22 mgc_add_9_0_6_1_10 1.0764 13.0252 + sobel:core/FRAME:acc#22.cse 0.0000 13.0252 + sobel:core/FRAME:acc#5 mgc_add_10_0_10_1_11 1.1389 14.1641 + sobel:core/FRAME:acc#5.psp.sva 0.0000 14.1641 + sobel:core/slc(FRAME:acc#5.psp.sva)#4 0.0000 14.1641 + sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm 0.0000 14.1641 + sobel:core/conc#59 0.0000 14.1641 + sobel:core/conc#59.itm 0.0000 14.1641 + sobel:core/FRAME:or mgc_or_10_2 0.2679 14.4320 + sobel:core/FRAME:or.itm 0.0000 14.4320 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 14.4320 + + 6 sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d) 14.4320 5.5680 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2).sg2).itm 0.0000 0.0000 + sobel:core/conc 0.0000 0.0000 + sobel:core/conc.itm 0.0000 0.0000 + sobel:core/ACC1:acc#36 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#36.itm 0.0000 1.2059 + sobel:core/ACC1:slc#3 0.0000 1.2059 + sobel:core/ACC1:slc#3.itm 0.0000 1.2059 + sobel:core/ACC1:acc#41 mgc_add_11_1_11_1_12 1.2059 2.4119 + sobel:core/ACC1:acc#41.itm 0.0000 2.4119 + sobel:core/ACC1:acc#43 mgc_add_12_1_12_1_13 1.2718 3.6837 + sobel:core/ACC1:acc#43.itm 0.0000 3.6837 + sobel:core/ACC1:acc mgc_add_13_1_12_1_14 1.3384 5.0221 + sobel:core/ACC1:acc.itm 0.0000 5.0221 + sobel:core/ACC1:slc 0.0000 5.0221 + sobel:core/ACC1:slc.psp.sva 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#6 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#6.itm 0.0000 5.0221 + sobel:core/FRAME:acc#31 mgc_add_1_0_1_0_2 0.5058 5.5278 + sobel:core/FRAME:acc#31.itm 0.0000 5.5278 + sobel:core/FRAME:conc#29 0.0000 5.5278 + sobel:core/FRAME:conc#29.itm 0.0000 5.5278 + sobel:core/FRAME:acc#11 mgc_add_4_0_4_1_6 0.5286 6.0564 + sobel:core/FRAME:acc#11.itm 0.0000 6.0564 + sobel:core/FRAME:acc#13 mgc_add_5_0_5_1_6 0.7751 6.8315 + sobel:core/FRAME:acc#13.itm 0.0000 6.8315 + sobel:core/FRAME:acc#14 mgc_add_6_0_6_1_7 0.8537 7.6852 + sobel:core/FRAME:acc#14.itm 0.0000 7.6852 + sobel:core/acc mgc_add_7_0_7_0_7 1.0910 8.7763 + sobel:core/acc.imod.sva 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#4 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#4.itm 0.0000 8.7763 + sobel:core/FRAME:acc#16 mgc_add_5_0_5_1_6 0.7751 9.5514 + sobel:core/FRAME:acc#16.itm 0.0000 9.5514 + sobel:core/acc#3 mgc_add_5_0_5_1_6 0.7751 10.3265 + sobel:core/acc#3.itm 0.0000 10.3265 + sobel:core/FRAME:slc#5 0.0000 10.3265 + sobel:core/FRAME:slc#5.itm 0.0000 10.3265 + sobel:core/FRAME:acc#18 mgc_add_2_1_1_1_3 0.4952 10.8217 + sobel:core/FRAME:acc#18.itm 0.0000 10.8217 + sobel:core/FRAME:acc#20 mgc_add_3_0_3_1_4 0.5984 11.4202 + sobel:core/FRAME:acc#20.itm 0.0000 11.4202 + sobel:core/FRAME:acc#21 mgc_add_4_0_4_1_6 0.5286 11.9487 + sobel:core/FRAME:acc#21.itm 0.0000 11.9487 + sobel:core/FRAME:acc#22 mgc_add_9_0_6_1_10 1.0764 13.0252 + sobel:core/FRAME:acc#22.cse 0.0000 13.0252 + sobel:core/FRAME:acc#5 mgc_add_10_0_10_1_11 1.1389 14.1641 + sobel:core/FRAME:acc#5.psp.sva 0.0000 14.1641 + sobel:core/slc(FRAME:acc#5.psp.sva)#4 0.0000 14.1641 + sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm 0.0000 14.1641 + sobel:core/conc#59 0.0000 14.1641 + sobel:core/conc#59.itm 0.0000 14.1641 + sobel:core/FRAME:or mgc_or_10_2 0.2679 14.4320 + sobel:core/FRAME:or.itm 0.0000 14.4320 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 14.4320 + + 7 sobel:core/reg(ACC1:slc(regs.regs(2)#1)#1.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d) 14.4320 5.5680 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2)#1)#1.itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm 0.0000 0.0000 + sobel:core/ACC1:not#9 mgc_not_10 0.0000 0.0000 + sobel:core/ACC1:not#9.itm 0.0000 0.0000 + sobel:core/conc#53 0.0000 0.0000 + sobel:core/conc#53.itm 0.0000 0.0000 + sobel:core/ACC1:acc#34 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#34.itm 0.0000 1.2059 + sobel:core/ACC1:slc#1 0.0000 1.2059 + sobel:core/ACC1:slc#1.itm 0.0000 1.2059 + sobel:core/ACC1:acc#40 mgc_add_11_1_11_1_12 1.2059 2.4119 + sobel:core/ACC1:acc#40.itm 0.0000 2.4119 + sobel:core/ACC1:acc#43 mgc_add_12_1_12_1_13 1.2718 3.6837 + sobel:core/ACC1:acc#43.itm 0.0000 3.6837 + sobel:core/ACC1:acc mgc_add_13_1_12_1_14 1.3384 5.0221 + sobel:core/ACC1:acc.itm 0.0000 5.0221 + sobel:core/ACC1:slc 0.0000 5.0221 + sobel:core/ACC1:slc.psp.sva 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#6 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#6.itm 0.0000 5.0221 + sobel:core/FRAME:acc#31 mgc_add_1_0_1_0_2 0.5058 5.5278 + sobel:core/FRAME:acc#31.itm 0.0000 5.5278 + sobel:core/FRAME:conc#29 0.0000 5.5278 + sobel:core/FRAME:conc#29.itm 0.0000 5.5278 + sobel:core/FRAME:acc#11 mgc_add_4_0_4_1_6 0.5286 6.0564 + sobel:core/FRAME:acc#11.itm 0.0000 6.0564 + sobel:core/FRAME:acc#13 mgc_add_5_0_5_1_6 0.7751 6.8315 + sobel:core/FRAME:acc#13.itm 0.0000 6.8315 + sobel:core/FRAME:acc#14 mgc_add_6_0_6_1_7 0.8537 7.6852 + sobel:core/FRAME:acc#14.itm 0.0000 7.6852 + sobel:core/acc mgc_add_7_0_7_0_7 1.0910 8.7763 + sobel:core/acc.imod.sva 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#10 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#10.itm 0.0000 8.7763 + sobel:core/conc#55 0.0000 8.7763 + sobel:core/conc#55.itm 0.0000 8.7763 + sobel:core/FRAME:acc#16 mgc_add_5_0_5_1_6 0.7751 9.5514 + sobel:core/FRAME:acc#16.itm 0.0000 9.5514 + sobel:core/acc#3 mgc_add_5_0_5_1_6 0.7751 10.3265 + sobel:core/acc#3.itm 0.0000 10.3265 + sobel:core/FRAME:slc#5 0.0000 10.3265 + sobel:core/FRAME:slc#5.itm 0.0000 10.3265 + sobel:core/FRAME:acc#18 mgc_add_2_1_1_1_3 0.4952 10.8217 + sobel:core/FRAME:acc#18.itm 0.0000 10.8217 + sobel:core/FRAME:acc#20 mgc_add_3_0_3_1_4 0.5984 11.4202 + sobel:core/FRAME:acc#20.itm 0.0000 11.4202 + sobel:core/FRAME:acc#21 mgc_add_4_0_4_1_6 0.5286 11.9487 + sobel:core/FRAME:acc#21.itm 0.0000 11.9487 + sobel:core/FRAME:acc#22 mgc_add_9_0_6_1_10 1.0764 13.0252 + sobel:core/FRAME:acc#22.cse 0.0000 13.0252 + sobel:core/FRAME:acc#5 mgc_add_10_0_10_1_11 1.1389 14.1641 + sobel:core/FRAME:acc#5.psp.sva 0.0000 14.1641 + sobel:core/slc(FRAME:acc#5.psp.sva)#4 0.0000 14.1641 + sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm 0.0000 14.1641 + sobel:core/conc#59 0.0000 14.1641 + sobel:core/conc#59.itm 0.0000 14.1641 + sobel:core/FRAME:or mgc_or_10_2 0.2679 14.4320 + sobel:core/FRAME:or.itm 0.0000 14.4320 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 14.4320 + + 8 sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d) 14.4320 5.5680 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2).sg2).itm 0.0000 0.0000 + sobel:core/conc 0.0000 0.0000 + sobel:core/conc.itm 0.0000 0.0000 + sobel:core/ACC1:acc#36 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#36.itm 0.0000 1.2059 + sobel:core/ACC1:slc#3 0.0000 1.2059 + sobel:core/ACC1:slc#3.itm 0.0000 1.2059 + sobel:core/ACC1:acc#41 mgc_add_11_1_11_1_12 1.2059 2.4119 + sobel:core/ACC1:acc#41.itm 0.0000 2.4119 + sobel:core/ACC1:acc#43 mgc_add_12_1_12_1_13 1.2718 3.6837 + sobel:core/ACC1:acc#43.itm 0.0000 3.6837 + sobel:core/ACC1:acc mgc_add_13_1_12_1_14 1.3384 5.0221 + sobel:core/ACC1:acc.itm 0.0000 5.0221 + sobel:core/ACC1:slc 0.0000 5.0221 + sobel:core/ACC1:slc.psp.sva 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#6 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#6.itm 0.0000 5.0221 + sobel:core/FRAME:acc#31 mgc_add_1_0_1_0_2 0.5058 5.5278 + sobel:core/FRAME:acc#31.itm 0.0000 5.5278 + sobel:core/FRAME:conc#29 0.0000 5.5278 + sobel:core/FRAME:conc#29.itm 0.0000 5.5278 + sobel:core/FRAME:acc#11 mgc_add_4_0_4_1_6 0.5286 6.0564 + sobel:core/FRAME:acc#11.itm 0.0000 6.0564 + sobel:core/FRAME:acc#13 mgc_add_5_0_5_1_6 0.7751 6.8315 + sobel:core/FRAME:acc#13.itm 0.0000 6.8315 + sobel:core/FRAME:acc#14 mgc_add_6_0_6_1_7 0.8537 7.6852 + sobel:core/FRAME:acc#14.itm 0.0000 7.6852 + sobel:core/acc mgc_add_7_0_7_0_7 1.0910 8.7763 + sobel:core/acc.imod.sva 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#15 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#15.itm 0.0000 8.7763 + sobel:core/conc#55 0.0000 8.7763 + sobel:core/conc#55.itm 0.0000 8.7763 + sobel:core/FRAME:acc#16 mgc_add_5_0_5_1_6 0.7751 9.5514 + sobel:core/FRAME:acc#16.itm 0.0000 9.5514 + sobel:core/acc#3 mgc_add_5_0_5_1_6 0.7751 10.3265 + sobel:core/acc#3.itm 0.0000 10.3265 + sobel:core/FRAME:slc#5 0.0000 10.3265 + sobel:core/FRAME:slc#5.itm 0.0000 10.3265 + sobel:core/FRAME:acc#18 mgc_add_2_1_1_1_3 0.4952 10.8217 + sobel:core/FRAME:acc#18.itm 0.0000 10.8217 + sobel:core/FRAME:acc#20 mgc_add_3_0_3_1_4 0.5984 11.4202 + sobel:core/FRAME:acc#20.itm 0.0000 11.4202 + sobel:core/FRAME:acc#21 mgc_add_4_0_4_1_6 0.5286 11.9487 + sobel:core/FRAME:acc#21.itm 0.0000 11.9487 + sobel:core/FRAME:acc#22 mgc_add_9_0_6_1_10 1.0764 13.0252 + sobel:core/FRAME:acc#22.cse 0.0000 13.0252 + sobel:core/FRAME:acc#5 mgc_add_10_0_10_1_11 1.1389 14.1641 + sobel:core/FRAME:acc#5.psp.sva 0.0000 14.1641 + sobel:core/slc(FRAME:acc#5.psp.sva)#4 0.0000 14.1641 + sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm 0.0000 14.1641 + sobel:core/conc#59 0.0000 14.1641 + sobel:core/conc#59.itm 0.0000 14.1641 + sobel:core/FRAME:or mgc_or_10_2 0.2679 14.4320 + sobel:core/FRAME:or.itm 0.0000 14.4320 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 14.4320 + + 9 sobel:core/reg(ACC1:slc(regs.regs(2)#1)#2.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d) 14.4320 5.5680 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2)#1)#2.itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm 0.0000 0.0000 + sobel:core/ACC1:not#10 mgc_not_10 0.0000 0.0000 + sobel:core/ACC1:not#10.itm 0.0000 0.0000 + sobel:core/conc#54 0.0000 0.0000 + sobel:core/conc#54.itm 0.0000 0.0000 + sobel:core/ACC1:acc#34 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#34.itm 0.0000 1.2059 + sobel:core/ACC1:slc#1 0.0000 1.2059 + sobel:core/ACC1:slc#1.itm 0.0000 1.2059 + sobel:core/ACC1:acc#40 mgc_add_11_1_11_1_12 1.2059 2.4119 + sobel:core/ACC1:acc#40.itm 0.0000 2.4119 + sobel:core/ACC1:acc#43 mgc_add_12_1_12_1_13 1.2718 3.6837 + sobel:core/ACC1:acc#43.itm 0.0000 3.6837 + sobel:core/ACC1:acc mgc_add_13_1_12_1_14 1.3384 5.0221 + sobel:core/ACC1:acc.itm 0.0000 5.0221 + sobel:core/ACC1:slc 0.0000 5.0221 + sobel:core/ACC1:slc.psp.sva 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#6 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#6.itm 0.0000 5.0221 + sobel:core/FRAME:acc#31 mgc_add_1_0_1_0_2 0.5058 5.5278 + sobel:core/FRAME:acc#31.itm 0.0000 5.5278 + sobel:core/FRAME:conc#29 0.0000 5.5278 + sobel:core/FRAME:conc#29.itm 0.0000 5.5278 + sobel:core/FRAME:acc#11 mgc_add_4_0_4_1_6 0.5286 6.0564 + sobel:core/FRAME:acc#11.itm 0.0000 6.0564 + sobel:core/FRAME:acc#13 mgc_add_5_0_5_1_6 0.7751 6.8315 + sobel:core/FRAME:acc#13.itm 0.0000 6.8315 + sobel:core/FRAME:acc#14 mgc_add_6_0_6_1_7 0.8537 7.6852 + sobel:core/FRAME:acc#14.itm 0.0000 7.6852 + sobel:core/acc mgc_add_7_0_7_0_7 1.0910 8.7763 + sobel:core/acc.imod.sva 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#10 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#10.itm 0.0000 8.7763 + sobel:core/conc#55 0.0000 8.7763 + sobel:core/conc#55.itm 0.0000 8.7763 + sobel:core/FRAME:acc#16 mgc_add_5_0_5_1_6 0.7751 9.5514 + sobel:core/FRAME:acc#16.itm 0.0000 9.5514 + sobel:core/acc#3 mgc_add_5_0_5_1_6 0.7751 10.3265 + sobel:core/acc#3.itm 0.0000 10.3265 + sobel:core/FRAME:slc#5 0.0000 10.3265 + sobel:core/FRAME:slc#5.itm 0.0000 10.3265 + sobel:core/FRAME:acc#18 mgc_add_2_1_1_1_3 0.4952 10.8217 + sobel:core/FRAME:acc#18.itm 0.0000 10.8217 + sobel:core/FRAME:acc#20 mgc_add_3_0_3_1_4 0.5984 11.4202 + sobel:core/FRAME:acc#20.itm 0.0000 11.4202 + sobel:core/FRAME:acc#21 mgc_add_4_0_4_1_6 0.5286 11.9487 + sobel:core/FRAME:acc#21.itm 0.0000 11.9487 + sobel:core/FRAME:acc#22 mgc_add_9_0_6_1_10 1.0764 13.0252 + sobel:core/FRAME:acc#22.cse 0.0000 13.0252 + sobel:core/FRAME:acc#5 mgc_add_10_0_10_1_11 1.1389 14.1641 + sobel:core/FRAME:acc#5.psp.sva 0.0000 14.1641 + sobel:core/slc(FRAME:acc#5.psp.sva)#4 0.0000 14.1641 + sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm 0.0000 14.1641 + sobel:core/conc#59 0.0000 14.1641 + sobel:core/conc#59.itm 0.0000 14.1641 + sobel:core/FRAME:or mgc_or_10_2 0.2679 14.4320 + sobel:core/FRAME:or.itm 0.0000 14.4320 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 14.4320 + + 10 sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d) 14.4320 5.5680 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:slc(regs.regs(2).sg2).itm 0.0000 0.0000 + sobel:core/conc 0.0000 0.0000 + sobel:core/conc.itm 0.0000 0.0000 + sobel:core/ACC1:acc#36 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#36.itm 0.0000 1.2059 + sobel:core/ACC1:slc#3 0.0000 1.2059 + sobel:core/ACC1:slc#3.itm 0.0000 1.2059 + sobel:core/ACC1:acc#41 mgc_add_11_1_11_1_12 1.2059 2.4119 + sobel:core/ACC1:acc#41.itm 0.0000 2.4119 + sobel:core/ACC1:acc#43 mgc_add_12_1_12_1_13 1.2718 3.6837 + sobel:core/ACC1:acc#43.itm 0.0000 3.6837 + sobel:core/ACC1:acc mgc_add_13_1_12_1_14 1.3384 5.0221 + sobel:core/ACC1:acc.itm 0.0000 5.0221 + sobel:core/ACC1:slc 0.0000 5.0221 + sobel:core/ACC1:slc.psp.sva 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#15 0.0000 5.0221 + sobel:core/slc(ACC1:slc.psp.sva)#15.itm 0.0000 5.0221 + sobel:core/FRAME:not#19 mgc_not_1 0.0000 5.0221 + sobel:core/FRAME:not#19.itm 0.0000 5.0221 + sobel:core/FRAME:acc#31 mgc_add_1_0_1_0_2 0.5058 5.5278 + sobel:core/FRAME:acc#31.itm 0.0000 5.5278 + sobel:core/FRAME:conc#29 0.0000 5.5278 + sobel:core/FRAME:conc#29.itm 0.0000 5.5278 + sobel:core/FRAME:acc#11 mgc_add_4_0_4_1_6 0.5286 6.0564 + sobel:core/FRAME:acc#11.itm 0.0000 6.0564 + sobel:core/FRAME:acc#13 mgc_add_5_0_5_1_6 0.7751 6.8315 + sobel:core/FRAME:acc#13.itm 0.0000 6.8315 + sobel:core/FRAME:acc#14 mgc_add_6_0_6_1_7 0.8537 7.6852 + sobel:core/FRAME:acc#14.itm 0.0000 7.6852 + sobel:core/acc mgc_add_7_0_7_0_7 1.0910 8.7763 + sobel:core/acc.imod.sva 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#15 0.0000 8.7763 + sobel:core/slc(acc.imod.sva)#15.itm 0.0000 8.7763 + sobel:core/conc#55 0.0000 8.7763 + sobel:core/conc#55.itm 0.0000 8.7763 + sobel:core/FRAME:acc#16 mgc_add_5_0_5_1_6 0.7751 9.5514 + sobel:core/FRAME:acc#16.itm 0.0000 9.5514 + sobel:core/acc#3 mgc_add_5_0_5_1_6 0.7751 10.3265 + sobel:core/acc#3.itm 0.0000 10.3265 + sobel:core/FRAME:slc#5 0.0000 10.3265 + sobel:core/FRAME:slc#5.itm 0.0000 10.3265 + sobel:core/FRAME:acc#18 mgc_add_2_1_1_1_3 0.4952 10.8217 + sobel:core/FRAME:acc#18.itm 0.0000 10.8217 + sobel:core/FRAME:acc#20 mgc_add_3_0_3_1_4 0.5984 11.4202 + sobel:core/FRAME:acc#20.itm 0.0000 11.4202 + sobel:core/FRAME:acc#21 mgc_add_4_0_4_1_6 0.5286 11.9487 + sobel:core/FRAME:acc#21.itm 0.0000 11.9487 + sobel:core/FRAME:acc#22 mgc_add_9_0_6_1_10 1.0764 13.0252 + sobel:core/FRAME:acc#22.cse 0.0000 13.0252 + sobel:core/FRAME:acc#5 mgc_add_10_0_10_1_11 1.1389 14.1641 + sobel:core/FRAME:acc#5.psp.sva 0.0000 14.1641 + sobel:core/slc(FRAME:acc#5.psp.sva)#4 0.0000 14.1641 + sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm 0.0000 14.1641 + sobel:core/conc#59 0.0000 14.1641 + sobel:core/conc#59.itm 0.0000 14.1641 + sobel:core/FRAME:or mgc_or_10_2 0.2679 14.4320 + sobel:core/FRAME:or.itm 0.0000 14.4320 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 14.4320 + + + Register Input and Register-to-Output Slack + Clock period or pin-to-reg delay constraint (clk): 20.0 + Clock uncertainty constraint (clk) : 0.0 + + Instance Port Slack (Delay) Messages + ------------------------------------------------ ------------------------------- ------- ------- -------- + sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm) slc(regs.regs(1).sg2.sva)#2.itm 20.0000 0.0000 + sobel:core/reg(ACC1:slc(regs.regs(2).sg2)#1.itm) slc(regs.regs(1).sg2.sva)#1.itm 20.0000 0.0000 + sobel:core/reg(ACC1:slc(regs.regs(2).sg2)#2.itm) slc(regs.regs(1).sg2.sva).itm 20.0000 0.0000 + sobel:core/reg(ACC1:slc(regs.regs(2)#1).itm) slc(regs.regs(1)#1.sva)#2.itm 20.0000 0.0000 + sobel:core/reg(ACC1:slc(regs.regs(2)#1)#1.itm) slc(regs.regs(1)#1.sva)#1.itm 20.0000 0.0000 + sobel:core/reg(ACC1:slc(regs.regs(2)#1)#2.itm) slc(regs.regs(1)#1.sva).itm 20.0000 0.0000 + sobel:core/reg(regs.regs(1)#1.sva) slc(regs.regs(0).sva#8).itm 20.0000 0.0000 + sobel:core/reg(regs.regs(1).sg2.sva) slc(regs.regs(0).sva#7).itm 20.0000 0.0000 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d) FRAME:or.itm 5.5680 14.4320 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 FRAME:or#3.itm 5.5680 14.4320 + sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#3 slc(FRAME:acc#5.psp.sva)#3.itm 5.8359 14.1641 + sobel vout:rsc.z 20.0000 0.0000 + + Operator Bitwidth Summary + Operation Size (bits) Count + ---------- ----------- ----- + add + - 14 1 + - 13 1 + - 12 6 + - 11 5 + - 10 1 + - 8 1 + - 7 2 + - 6 6 + - 4 1 + - 3 3 + - 2 2 + mul + - 9 1 + not + - 10 3 + - 3 1 + - 2 1 + - 1 1 + or + - 2 2 + read_port + - 90 1 + reg + - 30 2 + - 10 8 + - 6 1 + write_port + - 30 1 + + End of Report |