diff options
Diffstat (limited to 'Sobel/sobel.v6/rtl.rpt')
| -rw-r--r-- | Sobel/sobel.v6/rtl.rpt | 760 |
1 files changed, 760 insertions, 0 deletions
diff --git a/Sobel/sobel.v6/rtl.rpt b/Sobel/sobel.v6/rtl.rpt new file mode 100644 index 0000000..2fe0a15 --- /dev/null +++ b/Sobel/sobel.v6/rtl.rpt @@ -0,0 +1,760 @@ +-- Catapult University Version: Report +-- ---------------------------- --------------------------------------------------- +-- Version: 2011a.126 Production Release +-- Build Date: Wed Aug 8 00:52:07 PDT 2012 + +-- Generated by: mg3115@EEWS104A-013 +-- Generated date: Tue Mar 08 14:54:00 +0000 2016 + +Solution Settings: sobel.v6 + Current state: extract + Project: Sobel + + Design Input Files Specified + $PROJECT_HOME/sobel.h + $MGC_HOME/shared/include/ac_int.h + $PROJECT_HOME/bmp_io.cpp + $PROJECT_HOME/bmp_io.h + $PROJECT_HOME/tb_blur.cpp + $MGC_HOME/shared/include/mc_testbench.h + $MGC_HOME/shared/include/mc_scverify.h + $MGC_HOME/shared/include/ac_int.h + $PROJECT_HOME/sobel.h + $PROJECT_HOME/bmp_io.h + $PROJECT_HOME/bmp_io.h + $PROJECT_HOME/shift_class.h + $PROJECT_HOME/sobel.cpp + $MGC_HOME/shared/include/ac_fixed.h + $MGC_HOME/shared/include/ac_int.h + $PROJECT_HOME/sobel.h + $PROJECT_HOME/shift_class.h + + Processes/Blocks in Design + Process Real Operation(s) count Latency Throughput Reset Length II Comments + ------------- ----------------------- ------- ---------- ------------ -- -------- + /sobel/core 298 307202 307200 0 1 + Design Total: 298 307202 307200 0 0 + + Bill Of Materials (Datapath) + Component Name Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign + --------------------------------------- ---------- --------------------------- ---------- ----- ---------- ----------- + [Lib: mgc_Altera-Cyclone-III-6_beh_psr] + mgc_add(1,0,1,0,2) 2.319 0.000 2.319 0.506 21 22 + mgc_add(10,0,10,0,11) 11.241 0.000 11.241 1.301 2 2 + mgc_add(10,1,10,1,11) 11.000 0.000 11.000 1.139 3 3 + mgc_add(11,0,10,1,12) 12.000 0.000 12.000 1.208 2 2 + mgc_add(11,0,11,0,12) 12.233 0.000 12.233 1.368 1 1 + mgc_add(11,1,11,1,12) 12.000 0.000 12.000 1.206 3 3 + mgc_add(12,0,12,0,13) 13.224 0.000 13.224 1.434 1 1 + mgc_add(12,0,12,1,14) 13.000 0.000 13.000 1.109 3 3 + mgc_add(13,0,13,0,14) 14.215 0.000 14.215 1.499 1 1 + mgc_add(14,0,14,1,15) 15.000 0.000 15.000 1.401 2 2 + mgc_add(15,0,15,0,16) 16.198 0.000 16.198 1.627 2 2 + mgc_add(16,0,15,1,16) 17.000 0.000 17.000 1.691 1 1 + mgc_add(16,0,16,0,17) 17.189 0.000 17.189 1.690 9 9 + mgc_add(17,0,16,0,18) 18.184 0.000 18.184 1.754 4 4 + mgc_add(19,0,2,1,19) 20.000 0.000 20.000 1.908 1 0 + mgc_add(2,0,1,0,3) 3.315 0.000 3.315 0.658 0 1 + mgc_add(2,0,2,0,3) 3.311 0.000 3.311 0.653 48 45 + mgc_add(3,0,3,0,4) 4.302 0.000 4.302 0.761 37 37 + mgc_add(4,0,3,0,5) 5.297 0.000 5.297 0.856 0 1 + mgc_add(4,0,4,0,5) 5.293 0.000 5.293 0.854 13 12 + mgc_add(5,0,5,0,6) 6.285 0.000 6.285 0.938 12 12 + mgc_add(6,0,5,1,8) 7.000 0.000 7.000 0.693 1 1 + mgc_add(6,0,6,0,6) 7.276 0.000 7.276 1.016 5 5 + mgc_add(6,0,6,0,7) 7.276 0.000 7.276 1.016 3 3 + mgc_add(7,0,7,0,8) 8.267 0.000 8.267 1.091 2 1 + mgc_add(7,0,7,1,9) 8.000 0.000 8.000 0.766 2 2 + mgc_add(8,0,8,0,9) 9.259 0.000 9.259 1.163 2 1 + mgc_add(9,0,9,1,10) 10.000 0.000 10.000 1.071 3 3 + mgc_and(19,2) 13.867 0.000 13.867 0.263 1 0 + mgc_mul(2,0,11,0,12) 330.250 2.000 10.250 3.181 3 3 + mgc_mul(2,0,13,0,14) 330.250 2.000 10.250 3.266 3 3 + mgc_mul(2,0,15,0,16) 330.250 2.000 10.250 3.352 2 2 + mgc_mul(2,0,7,0,8) 330.250 2.000 10.250 3.011 4 4 + mgc_mul(2,0,9,0,11) 330.250 2.000 10.250 3.044 5 5 + mgc_mul(3,0,11,0,12) 330.250 2.000 10.250 3.194 1 1 + mgc_mul(3,0,6,0,9) 330.250 2.000 10.250 2.846 5 5 + mgc_mux(30,1,2) 27.583 0.000 27.583 0.369 0 1 + mgc_not(1) 0.000 0.000 0.000 0.000 0 77 + mgc_not(10) 0.000 0.000 0.000 0.000 0 3 + mgc_not(3) 0.000 0.000 0.000 0.000 0 4 + mgc_or(10,2) 7.298 0.000 7.298 0.268 1 1 + mgc_or(6,2) 4.379 0.000 4.379 0.268 1 1 + mgc_reg_pos(1,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 13 + mgc_reg_pos(10,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 9 + mgc_reg_pos(12,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 2 + mgc_reg_pos(13,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 1 + mgc_reg_pos(14,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 2 + mgc_reg_pos(16,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 1 + mgc_reg_pos(2,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 1 + mgc_reg_pos(3,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 1 + mgc_reg_pos(30,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 3 + mgc_reg_pos(6,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 5 + mgc_reg_pos(7,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 1 + mgc_reg_pos(8,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 2 + [Lib: mgc_ioport] + mgc_in_wire(1,90) 0.000 0.000 0.000 0.000 1 1 + mgc_out_stdreg(2,30) 0.000 0.000 0.000 0.000 1 1 + + TOTAL AREA (After Assignment): 8771.468 46.000 1411.000 + + Area Scores + Post-Scheduling Post-DP & FSM Post-Assignment + ----------------- --------------- --------------- --------------- + Total Area Score: 8799.6 8790.6 8771.5 + Total Reg: 0.0 0.0 0.0 + + DataPath: 8799.6 (100%) 8790.6 (100%) 8771.5 (100%) + MUX: 0.0 46.7 (1%) 27.6 (0%) + FUNC: 8774.0 (100%) 8732.2 (99%) 8732.2 (100%) + LOGIC: 25.5 (0%) 11.7 (0%) 11.7 (0%) + BUFFER: 0.0 0.0 0.0 + MEM: 0.0 0.0 0.0 + ROM: 0.0 0.0 0.0 + REG: 0.0 0.0 0.0 + + + FSM: 0.0 0.0 0.0 + FSM-REG: 0.0 0.0 0.0 + FSM-COMB: 0.0 0.0 0.0 + + + Register-to-Variable Mappings + Register Size(bits) Gated Register CG Opt Done Variables + --------------------------------------- ---------- -------------- ----------- ----------------------------------------------------- + regs.regs(1)#1.sva 30 Y regs.regs(1)#1.sva + regs.regs(1).sg2.sva 30 Y regs.regs(1).sg2.sva + vout:rsc:mgc_out_stdreg.d 30 Y vout:rsc:mgc_out_stdreg.d + ACC1:acc#281.itm#1 16 Y ACC1:acc#281.itm#1 + ACC1:mul#91.itm#1 14 Y ACC1:mul#91.itm#1 + ACC1:mul#96.itm#1 14 Y ACC1:mul#96.itm#1 + mul#1.itm#1 13 Y mul#1.itm#1 + ACC1:acc#268.itm#1 12 Y ACC1:acc#268.itm#1 + ACC1:mul#90.itm#1 12 Y ACC1:mul#90.itm#1 + ACC1:acc#264.itm#1 10 Y ACC1:acc#264.itm#1 + ACC1:mul#104.itm#1 10 Y ACC1:mul#104.itm#1 + ACC1:mul#89.itm#1 10 Y ACC1:mul#89.itm#1 + regs.regs:slc(regs.regs(2))#6.itm 10 Y regs.regs:slc(regs.regs(2))#6.itm + regs.regs:slc(regs.regs(2))#7.itm 10 Y regs.regs:slc(regs.regs(2))#7.itm + regs.regs:slc(regs.regs(2)).itm 10 Y regs.regs:slc(regs.regs(2)).itm + regs.regs:slc(regs.regs(2).sg2)#1.itm 10 Y regs.regs:slc(regs.regs(2).sg2)#1.itm + regs.regs:slc(regs.regs(2).sg2)#2.itm 10 Y regs.regs:slc(regs.regs(2).sg2)#2.itm + regs.regs:slc(regs.regs(2).sg2).itm 10 Y regs.regs:slc(regs.regs(2).sg2).itm + ACC1:mul#103.itm#1 8 Y ACC1:mul#103.itm#1 + ACC1:mul#99.itm#1 8 Y ACC1:mul#99.itm#1 + ACC1:acc#255.itm#1 7 Y ACC1:acc#255.itm#1 + ACC1:acc#251.itm#1 6 Y ACC1:acc#251.itm#1 + ACC1:acc#252.itm#1 6 Y ACC1:acc#252.itm#1 + ACC1:mul#98.itm#1 6 Y ACC1:mul#98.itm#1 + FRAME:acc#12.itm#1 6 Y FRAME:acc#12.itm#1 + intensity:slc(intensity#2.sg1).itm#1 6 Y intensity:slc(intensity#2.sg1).itm#1 + intensity:slc(intensity#2.sg1)#11.itm#1 3 Y intensity:slc(intensity#2.sg1)#11.itm#1 + intensity:slc(intensity#2.sg1)#9.itm#1 2 Y intensity:slc(intensity#2.sg1)#9.itm#1 + ACC1-2:slc(acc.idiv)#106.itm#1 1 Y ACC1-2:slc(acc.idiv)#106.itm#1 + ACC1-2:slc(acc.idiv)#131.itm#1 1 Y ACC1-2:slc(acc.idiv)#131.itm#1 + ACC1-2:slc(acc.idiv)#132.itm#1 1 Y ACC1-2:slc(acc.idiv)#132.itm#1 + ACC1-3:slc(acc.idiv)#131.itm#1 1 Y ACC1-3:slc(acc.idiv)#131.itm#1 + ACC1-3:slc(acc.idiv)#132.itm#1 1 Y ACC1-3:slc(acc.idiv)#132.itm#1 + ACC1:slc(acc.idiv#2)#90.itm#1 1 Y ACC1:slc(acc.idiv#2)#90.itm#1 + ACC1:slc(acc.idiv#3)#36.itm#1 1 Y ACC1:slc(acc.idiv#3)#36.itm#1 + ACC1:slc(acc.idiv)#91.itm#1 1 Y ACC1:slc(acc.idiv)#91.itm#1 + ACC1:slc(acc.imod#17)#8.itm#1 1 Y ACC1:slc(acc.imod#17)#8.itm#1 + ACC1:slc(acc.imod)#28.itm#1 1 Y ACC1:slc(acc.imod)#28.itm#1 + intensity:slc(intensity#2.sg1)#12.itm#1 1 Y intensity:slc(intensity#2.sg1)#12.itm#1 + main.stage_0#2 1 Y main.stage_0#2 + main.stage_0#3 1 Y main.stage_0#3 + + Total: 332 332 0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) + + Timing Report + Critical Path + Max Delay: 15.982251999999999 + Slack: 4.017748000000001 + + Path Startpoint Endpoint Delay Slack + --------------------------------------------------- ------------------------------------------------- ---------------------------------- ------- ------- + 1 sobel:core/reg(ACC1:acc#252.itm#1) sobel:core/reg(FRAME:acc#12.itm#1) 15.9823 4.0177 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:acc#252.itm#1) mgc_reg_pos_6_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:acc#252.itm#1 0.0000 0.0000 + sobel:core/ACC1:acc#256 mgc_add_6_0_6_0_7 1.0162 1.0162 + sobel:core/ACC1:acc#256.itm 0.0000 1.0162 + sobel:core/ACC1:acc#260 mgc_add_7_0_7_0_8 1.0910 2.1072 + sobel:core/ACC1:acc#260.itm 0.0000 2.1072 + sobel:core/ACC1:acc#263 mgc_add_9_0_9_1_10 1.0706 3.1778 + sobel:core/ACC1:acc#263.itm 0.0000 3.1778 + sobel:core/ACC1:acc#266 mgc_add_10_0_10_0_11 1.3014 4.4793 + sobel:core/ACC1:acc#266.itm 0.0000 4.4793 + sobel:core/ACC1:acc#269 mgc_add_12_0_12_1_14 1.1093 5.5886 + sobel:core/ACC1:acc#269.itm 0.0000 5.5886 + sobel:core/ACC1:acc#271 mgc_add_12_0_12_0_13 1.4343 7.0229 + sobel:core/ACC1:acc#271.itm 0.0000 7.0229 + sobel:core/ACC1:acc#273 mgc_add_14_0_14_1_15 1.4009 8.4238 + sobel:core/ACC1:acc#273.itm 0.0000 8.4238 + sobel:core/ACC1:acc#276 mgc_add_15_0_15_0_16 1.6269 10.0507 + sobel:core/ACC1:acc#276.itm 0.0000 10.0507 + sobel:core/ACC1:acc#280 mgc_add_16_0_16_0_17 1.6898 11.7404 + sobel:core/ACC1:acc#280.itm 0.0000 11.7404 + sobel:core/ACC1:acc mgc_add_16_0_16_0_17 1.6898 13.4302 + sobel:core/ACC1:acc.itm 0.0000 13.4302 + sobel:core/ACC1:slc 0.0000 13.4302 + sobel:core/intensity#2.sg1.sva 0.0000 13.4302 + sobel:core/slc(intensity#2.sg1.sva)#8 0.0000 13.4302 + sobel:core/slc(intensity#2.sg1.sva)#8.itm 0.0000 13.4302 + sobel:core/FRAME:acc#9 mgc_add_3_0_3_0_4 0.7609 14.1911 + sobel:core/FRAME:acc#9.itm 0.0000 14.1911 + sobel:core/FRAME:acc#11 mgc_add_4_0_4_0_5 0.8536 15.0447 + sobel:core/FRAME:acc#11.itm 0.0000 15.0447 + sobel:core/FRAME:acc#12 mgc_add_5_0_5_0_6 0.9376 15.9823 + sobel:core/FRAME:acc#12.itm 0.0000 15.9823 + sobel:core/reg(FRAME:acc#12.itm#1) mgc_reg_pos_6_1_0_0_0_1_1 0.0000 15.9823 + + 2 sobel:core/reg(ACC1:acc#252.itm#1) sobel:core/reg(FRAME:acc#12.itm#1) 15.9823 4.0177 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:acc#252.itm#1) mgc_reg_pos_6_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:acc#252.itm#1 0.0000 0.0000 + sobel:core/ACC1:acc#256 mgc_add_6_0_6_0_7 1.0162 1.0162 + sobel:core/ACC1:acc#256.itm 0.0000 1.0162 + sobel:core/ACC1:acc#260 mgc_add_7_0_7_0_8 1.0910 2.1072 + sobel:core/ACC1:acc#260.itm 0.0000 2.1072 + sobel:core/ACC1:acc#263 mgc_add_9_0_9_1_10 1.0706 3.1778 + sobel:core/ACC1:acc#263.itm 0.0000 3.1778 + sobel:core/ACC1:acc#266 mgc_add_10_0_10_0_11 1.3014 4.4793 + sobel:core/ACC1:acc#266.itm 0.0000 4.4793 + sobel:core/ACC1:acc#269 mgc_add_12_0_12_1_14 1.1093 5.5886 + sobel:core/ACC1:acc#269.itm 0.0000 5.5886 + sobel:core/ACC1:acc#271 mgc_add_12_0_12_0_13 1.4343 7.0229 + sobel:core/ACC1:acc#271.itm 0.0000 7.0229 + sobel:core/ACC1:acc#273 mgc_add_14_0_14_1_15 1.4009 8.4238 + sobel:core/ACC1:acc#273.itm 0.0000 8.4238 + sobel:core/ACC1:acc#276 mgc_add_15_0_15_0_16 1.6269 10.0507 + sobel:core/ACC1:acc#276.itm 0.0000 10.0507 + sobel:core/ACC1:acc#280 mgc_add_16_0_16_0_17 1.6898 11.7404 + sobel:core/ACC1:acc#280.itm 0.0000 11.7404 + sobel:core/ACC1:acc mgc_add_16_0_16_0_17 1.6898 13.4302 + sobel:core/ACC1:acc.itm 0.0000 13.4302 + sobel:core/ACC1:slc 0.0000 13.4302 + sobel:core/intensity#2.sg1.sva 0.0000 13.4302 + sobel:core/slc(intensity#2.sg1.sva)#12 0.0000 13.4302 + sobel:core/slc(intensity#2.sg1.sva)#12.itm 0.0000 13.4302 + sobel:core/FRAME:not#36 mgc_not_1 0.0000 13.4302 + sobel:core/FRAME:not#36.itm 0.0000 13.4302 + sobel:core/conc#311 0.0000 13.4302 + sobel:core/conc#311.itm 0.0000 13.4302 + sobel:core/FRAME:acc#8 mgc_add_3_0_3_0_4 0.7609 14.1911 + sobel:core/FRAME:acc#8.itm 0.0000 14.1911 + sobel:core/FRAME:acc#11 mgc_add_4_0_4_0_5 0.8536 15.0447 + sobel:core/FRAME:acc#11.itm 0.0000 15.0447 + sobel:core/FRAME:acc#12 mgc_add_5_0_5_0_6 0.9376 15.9823 + sobel:core/FRAME:acc#12.itm 0.0000 15.9823 + sobel:core/reg(FRAME:acc#12.itm#1) mgc_reg_pos_6_1_0_0_0_1_1 0.0000 15.9823 + + 3 sobel:core/reg(ACC1:acc#252.itm#1) sobel:core/reg(FRAME:acc#12.itm#1) 15.9823 4.0177 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:acc#252.itm#1) mgc_reg_pos_6_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:acc#252.itm#1 0.0000 0.0000 + sobel:core/ACC1:acc#256 mgc_add_6_0_6_0_7 1.0162 1.0162 + sobel:core/ACC1:acc#256.itm 0.0000 1.0162 + sobel:core/ACC1:acc#260 mgc_add_7_0_7_0_8 1.0910 2.1072 + sobel:core/ACC1:acc#260.itm 0.0000 2.1072 + sobel:core/ACC1:acc#263 mgc_add_9_0_9_1_10 1.0706 3.1778 + sobel:core/ACC1:acc#263.itm 0.0000 3.1778 + sobel:core/ACC1:acc#266 mgc_add_10_0_10_0_11 1.3014 4.4793 + sobel:core/ACC1:acc#266.itm 0.0000 4.4793 + sobel:core/ACC1:acc#269 mgc_add_12_0_12_1_14 1.1093 5.5886 + sobel:core/ACC1:acc#269.itm 0.0000 5.5886 + sobel:core/ACC1:acc#271 mgc_add_12_0_12_0_13 1.4343 7.0229 + sobel:core/ACC1:acc#271.itm 0.0000 7.0229 + sobel:core/ACC1:acc#273 mgc_add_14_0_14_1_15 1.4009 8.4238 + sobel:core/ACC1:acc#273.itm 0.0000 8.4238 + sobel:core/ACC1:acc#276 mgc_add_15_0_15_0_16 1.6269 10.0507 + sobel:core/ACC1:acc#276.itm 0.0000 10.0507 + sobel:core/ACC1:acc#280 mgc_add_16_0_16_0_17 1.6898 11.7404 + sobel:core/ACC1:acc#280.itm 0.0000 11.7404 + sobel:core/ACC1:acc mgc_add_16_0_16_0_17 1.6898 13.4302 + sobel:core/ACC1:acc.itm 0.0000 13.4302 + sobel:core/ACC1:slc 0.0000 13.4302 + sobel:core/intensity#2.sg1.sva 0.0000 13.4302 + sobel:core/slc(intensity#2.sg1.sva)#7 0.0000 13.4302 + sobel:core/slc(intensity#2.sg1.sva)#7.itm 0.0000 13.4302 + sobel:core/FRAME:not#38 mgc_not_1 0.0000 13.4302 + sobel:core/FRAME:not#38.itm 0.0000 13.4302 + sobel:core/conc#311 0.0000 13.4302 + sobel:core/conc#311.itm 0.0000 13.4302 + sobel:core/FRAME:acc#8 mgc_add_3_0_3_0_4 0.7609 14.1911 + sobel:core/FRAME:acc#8.itm 0.0000 14.1911 + sobel:core/FRAME:acc#11 mgc_add_4_0_4_0_5 0.8536 15.0447 + sobel:core/FRAME:acc#11.itm 0.0000 15.0447 + sobel:core/FRAME:acc#12 mgc_add_5_0_5_0_6 0.9376 15.9823 + sobel:core/FRAME:acc#12.itm 0.0000 15.9823 + sobel:core/reg(FRAME:acc#12.itm#1) mgc_reg_pos_6_1_0_0_0_1_1 0.0000 15.9823 + + 4 sobel:core/reg(ACC1:acc#252.itm#1) sobel:core/reg(FRAME:acc#12.itm#1) 15.9823 4.0177 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:acc#252.itm#1) mgc_reg_pos_6_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:acc#252.itm#1 0.0000 0.0000 + sobel:core/ACC1:acc#256 mgc_add_6_0_6_0_7 1.0162 1.0162 + sobel:core/ACC1:acc#256.itm 0.0000 1.0162 + sobel:core/ACC1:acc#260 mgc_add_7_0_7_0_8 1.0910 2.1072 + sobel:core/ACC1:acc#260.itm 0.0000 2.1072 + sobel:core/ACC1:acc#263 mgc_add_9_0_9_1_10 1.0706 3.1778 + sobel:core/ACC1:acc#263.itm 0.0000 3.1778 + sobel:core/ACC1:acc#266 mgc_add_10_0_10_0_11 1.3014 4.4793 + sobel:core/ACC1:acc#266.itm 0.0000 4.4793 + sobel:core/ACC1:acc#269 mgc_add_12_0_12_1_14 1.1093 5.5886 + sobel:core/ACC1:acc#269.itm 0.0000 5.5886 + sobel:core/ACC1:acc#271 mgc_add_12_0_12_0_13 1.4343 7.0229 + sobel:core/ACC1:acc#271.itm 0.0000 7.0229 + sobel:core/ACC1:acc#273 mgc_add_14_0_14_1_15 1.4009 8.4238 + sobel:core/ACC1:acc#273.itm 0.0000 8.4238 + sobel:core/ACC1:acc#276 mgc_add_15_0_15_0_16 1.6269 10.0507 + sobel:core/ACC1:acc#276.itm 0.0000 10.0507 + sobel:core/ACC1:acc#280 mgc_add_16_0_16_0_17 1.6898 11.7404 + sobel:core/ACC1:acc#280.itm 0.0000 11.7404 + sobel:core/ACC1:acc mgc_add_16_0_16_0_17 1.6898 13.4302 + sobel:core/ACC1:acc.itm 0.0000 13.4302 + sobel:core/ACC1:slc 0.0000 13.4302 + sobel:core/intensity#2.sg1.sva 0.0000 13.4302 + sobel:core/slc(intensity#2.sg1.sva)#10 0.0000 13.4302 + sobel:core/slc(intensity#2.sg1.sva)#10.itm 0.0000 13.4302 + sobel:core/FRAME:acc#8 mgc_add_3_0_3_0_4 0.7609 14.1911 + sobel:core/FRAME:acc#8.itm 0.0000 14.1911 + sobel:core/FRAME:acc#11 mgc_add_4_0_4_0_5 0.8536 15.0447 + sobel:core/FRAME:acc#11.itm 0.0000 15.0447 + sobel:core/FRAME:acc#12 mgc_add_5_0_5_0_6 0.9376 15.9823 + sobel:core/FRAME:acc#12.itm 0.0000 15.9823 + sobel:core/reg(FRAME:acc#12.itm#1) mgc_reg_pos_6_1_0_0_0_1_1 0.0000 15.9823 + + 5 sobel:core/reg(ACC1:acc#251.itm#1) sobel:core/reg(FRAME:acc#12.itm#1) 15.9823 4.0177 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:acc#251.itm#1) mgc_reg_pos_6_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:acc#251.itm#1 0.0000 0.0000 + sobel:core/ACC1:acc#256 mgc_add_6_0_6_0_7 1.0162 1.0162 + sobel:core/ACC1:acc#256.itm 0.0000 1.0162 + sobel:core/ACC1:acc#260 mgc_add_7_0_7_0_8 1.0910 2.1072 + sobel:core/ACC1:acc#260.itm 0.0000 2.1072 + sobel:core/ACC1:acc#263 mgc_add_9_0_9_1_10 1.0706 3.1778 + sobel:core/ACC1:acc#263.itm 0.0000 3.1778 + sobel:core/ACC1:acc#266 mgc_add_10_0_10_0_11 1.3014 4.4793 + sobel:core/ACC1:acc#266.itm 0.0000 4.4793 + sobel:core/ACC1:acc#269 mgc_add_12_0_12_1_14 1.1093 5.5886 + sobel:core/ACC1:acc#269.itm 0.0000 5.5886 + sobel:core/ACC1:acc#271 mgc_add_12_0_12_0_13 1.4343 7.0229 + sobel:core/ACC1:acc#271.itm 0.0000 7.0229 + sobel:core/ACC1:acc#273 mgc_add_14_0_14_1_15 1.4009 8.4238 + sobel:core/ACC1:acc#273.itm 0.0000 8.4238 + sobel:core/ACC1:acc#276 mgc_add_15_0_15_0_16 1.6269 10.0507 + sobel:core/ACC1:acc#276.itm 0.0000 10.0507 + sobel:core/ACC1:acc#280 mgc_add_16_0_16_0_17 1.6898 11.7404 + sobel:core/ACC1:acc#280.itm 0.0000 11.7404 + sobel:core/ACC1:acc mgc_add_16_0_16_0_17 1.6898 13.4302 + sobel:core/ACC1:acc.itm 0.0000 13.4302 + sobel:core/ACC1:slc 0.0000 13.4302 + sobel:core/intensity#2.sg1.sva 0.0000 13.4302 + sobel:core/slc(intensity#2.sg1.sva)#10 0.0000 13.4302 + sobel:core/slc(intensity#2.sg1.sva)#10.itm 0.0000 13.4302 + sobel:core/FRAME:acc#8 mgc_add_3_0_3_0_4 0.7609 14.1911 + sobel:core/FRAME:acc#8.itm 0.0000 14.1911 + sobel:core/FRAME:acc#11 mgc_add_4_0_4_0_5 0.8536 15.0447 + sobel:core/FRAME:acc#11.itm 0.0000 15.0447 + sobel:core/FRAME:acc#12 mgc_add_5_0_5_0_6 0.9376 15.9823 + sobel:core/FRAME:acc#12.itm 0.0000 15.9823 + sobel:core/reg(FRAME:acc#12.itm#1) mgc_reg_pos_6_1_0_0_0_1_1 0.0000 15.9823 + + 6 sobel:core/reg(ACC1:acc#252.itm#1) sobel:core/reg(FRAME:acc#12.itm#1) 15.9823 4.0177 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:acc#252.itm#1) mgc_reg_pos_6_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:acc#252.itm#1 0.0000 0.0000 + sobel:core/ACC1:acc#256 mgc_add_6_0_6_0_7 1.0162 1.0162 + sobel:core/ACC1:acc#256.itm 0.0000 1.0162 + sobel:core/ACC1:acc#260 mgc_add_7_0_7_0_8 1.0910 2.1072 + sobel:core/ACC1:acc#260.itm 0.0000 2.1072 + sobel:core/ACC1:acc#263 mgc_add_9_0_9_1_10 1.0706 3.1778 + sobel:core/ACC1:acc#263.itm 0.0000 3.1778 + sobel:core/ACC1:acc#266 mgc_add_10_0_10_0_11 1.3014 4.4793 + sobel:core/ACC1:acc#266.itm 0.0000 4.4793 + sobel:core/ACC1:acc#269 mgc_add_12_0_12_1_14 1.1093 5.5886 + sobel:core/ACC1:acc#269.itm 0.0000 5.5886 + sobel:core/ACC1:acc#271 mgc_add_12_0_12_0_13 1.4343 7.0229 + sobel:core/ACC1:acc#271.itm 0.0000 7.0229 + sobel:core/ACC1:acc#273 mgc_add_14_0_14_1_15 1.4009 8.4238 + sobel:core/ACC1:acc#273.itm 0.0000 8.4238 + sobel:core/ACC1:acc#276 mgc_add_15_0_15_0_16 1.6269 10.0507 + sobel:core/ACC1:acc#276.itm 0.0000 10.0507 + sobel:core/ACC1:acc#280 mgc_add_16_0_16_0_17 1.6898 11.7404 + sobel:core/ACC1:acc#280.itm 0.0000 11.7404 + sobel:core/ACC1:acc mgc_add_16_0_16_0_17 1.6898 13.4302 + sobel:core/ACC1:acc.itm 0.0000 13.4302 + sobel:core/ACC1:slc 0.0000 13.4302 + sobel:core/intensity#2.sg1.sva 0.0000 13.4302 + sobel:core/slc(intensity#2.sg1.sva)#9 0.0000 13.4302 + sobel:core/slc(intensity#2.sg1.sva)#9.itm 0.0000 13.4302 + sobel:core/FRAME:not#26 mgc_not_3 0.0000 13.4302 + sobel:core/FRAME:not#26.itm 0.0000 13.4302 + sobel:core/FRAME:acc#9 mgc_add_3_0_3_0_4 0.7609 14.1911 + sobel:core/FRAME:acc#9.itm 0.0000 14.1911 + sobel:core/FRAME:acc#11 mgc_add_4_0_4_0_5 0.8536 15.0447 + sobel:core/FRAME:acc#11.itm 0.0000 15.0447 + sobel:core/FRAME:acc#12 mgc_add_5_0_5_0_6 0.9376 15.9823 + sobel:core/FRAME:acc#12.itm 0.0000 15.9823 + sobel:core/reg(FRAME:acc#12.itm#1) mgc_reg_pos_6_1_0_0_0_1_1 0.0000 15.9823 + + 7 sobel:core/reg(ACC1:acc#251.itm#1) sobel:core/reg(FRAME:acc#12.itm#1) 15.9823 4.0177 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(ACC1:acc#251.itm#1) mgc_reg_pos_6_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/ACC1:acc#251.itm#1 0.0000 0.0000 + sobel:core/ACC1:acc#256 mgc_add_6_0_6_0_7 1.0162 1.0162 + sobel:core/ACC1:acc#256.itm 0.0000 1.0162 + sobel:core/ACC1:acc#260 mgc_add_7_0_7_0_8 1.0910 2.1072 + sobel:core/ACC1:acc#260.itm 0.0000 2.1072 + sobel:core/ACC1:acc#263 mgc_add_9_0_9_1_10 1.0706 3.1778 + sobel:core/ACC1:acc#263.itm 0.0000 3.1778 + sobel:core/ACC1:acc#266 mgc_add_10_0_10_0_11 1.3014 4.4793 + sobel:core/ACC1:acc#266.itm 0.0000 4.4793 + sobel:core/ACC1:acc#269 mgc_add_12_0_12_1_14 1.1093 5.5886 + sobel:core/ACC1:acc#269.itm 0.0000 5.5886 + sobel:core/ACC1:acc#271 mgc_add_12_0_12_0_13 1.4343 7.0229 + sobel:core/ACC1:acc#271.itm 0.0000 7.0229 + sobel:core/ACC1:acc#273 mgc_add_14_0_14_1_15 1.4009 8.4238 + sobel:core/ACC1:acc#273.itm 0.0000 8.4238 + sobel:core/ACC1:acc#276 mgc_add_15_0_15_0_16 1.6269 10.0507 + sobel:core/ACC1:acc#276.itm 0.0000 10.0507 + sobel:core/ACC1:acc#280 mgc_add_16_0_16_0_17 1.6898 11.7404 + sobel:core/ACC1:acc#280.itm 0.0000 11.7404 + sobel:core/ACC1:acc mgc_add_16_0_16_0_17 1.6898 13.4302 + sobel:core/ACC1:acc.itm 0.0000 13.4302 + sobel:core/ACC1:slc 0.0000 13.4302 + sobel:core/intensity#2.sg1.sva 0.0000 13.4302 + sobel:core/slc(intensity#2.sg1.sva)#9 0.0000 13.4302 + sobel:core/slc(intensity#2.sg1.sva)#9.itm 0.0000 13.4302 + sobel:core/FRAME:not#26 mgc_not_3 0.0000 13.4302 + sobel:core/FRAME:not#26.itm 0.0000 13.4302 + sobel:core/FRAME:acc#9 mgc_add_3_0_3_0_4 0.7609 14.1911 + sobel:core/FRAME:acc#9.itm 0.0000 14.1911 + sobel:core/FRAME:acc#11 mgc_add_4_0_4_0_5 0.8536 15.0447 + sobel:core/FRAME:acc#11.itm 0.0000 15.0447 + sobel:core/FRAME:acc#12 mgc_add_5_0_5_0_6 0.9376 15.9823 + sobel:core/FRAME:acc#12.itm 0.0000 15.9823 + sobel:core/reg(FRAME:acc#12.itm#1) mgc_reg_pos_6_1_0_0_0_1_1 0.0000 15.9823 + + 8 sobel:core/reg(regs.regs:slc(regs.regs(2))#6.itm) sobel:core/reg(ACC1:acc#281.itm#1) 15.3757 4.6243 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(regs.regs:slc(regs.regs(2))#6.itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/regs.regs:slc(regs.regs(2))#6.itm 0.0000 0.0000 + sobel:core/ACC1:not#73 mgc_not_10 0.0000 0.0000 + sobel:core/ACC1:not#73.itm 0.0000 0.0000 + sobel:core/conc#342 0.0000 0.0000 + sobel:core/conc#342.itm 0.0000 0.0000 + sobel:core/ACC1:acc#178 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#178.itm 0.0000 1.2059 + sobel:core/ACC1:slc#27 0.0000 1.2059 + sobel:core/ACC1:slc#27.itm 0.0000 1.2059 + sobel:core/ACC1:exs#95 0.0000 1.2059 + sobel:core/ACC1:exs#95.itm 0.0000 1.2059 + sobel:core/ACC1:acc#177 mgc_add_16_0_16_0_17 1.6898 2.8957 + sobel:core/ACC1:acc#177.itm 0.0000 2.8957 + sobel:core/ACC1-3:acc mgc_add_17_0_16_0_18 1.7536 4.6493 + sobel:core/acc.idiv.sva 0.0000 4.6493 + sobel:core/slc(acc.idiv.sva)#4 0.0000 4.6493 + sobel:core/slc(acc.idiv.sva)#4.itm 0.0000 4.6493 + sobel:core/conc#335 0.0000 4.6493 + sobel:core/conc#335.itm 0.0000 4.6493 + sobel:core/ACC1:acc#181 mgc_add_2_0_2_0_3 0.6525 5.3018 + sobel:core/ACC1:acc#181.itm 0.0000 5.3018 + sobel:core/ACC1:slc#30 0.0000 5.3018 + sobel:core/ACC1:slc#30.itm 0.0000 5.3018 + sobel:core/conc#334 0.0000 5.3018 + sobel:core/conc#334.itm 0.0000 5.3018 + sobel:core/ACC1:acc#185 mgc_add_3_0_3_0_4 0.7609 6.0627 + sobel:core/ACC1:acc#185.itm 0.0000 6.0627 + sobel:core/ACC1:slc#34 0.0000 6.0627 + sobel:core/ACC1:slc#34.itm 0.0000 6.0627 + sobel:core/conc#333 0.0000 6.0627 + sobel:core/conc#333.itm 0.0000 6.0627 + sobel:core/ACC1:acc#187 mgc_add_4_0_4_0_5 0.8536 6.9163 + sobel:core/ACC1:acc#187.itm 0.0000 6.9163 + sobel:core/ACC1:slc#36 0.0000 6.9163 + sobel:core/ACC1:slc#36.itm 0.0000 6.9163 + sobel:core/conc#332 0.0000 6.9163 + sobel:core/conc#332.itm 0.0000 6.9163 + sobel:core/ACC1:acc#188 mgc_add_5_0_5_0_6 0.9376 7.8539 + sobel:core/ACC1:acc#188.itm 0.0000 7.8539 + sobel:core/ACC1:slc#37 0.0000 7.8539 + sobel:core/ACC1:slc#37.itm 0.0000 7.8539 + sobel:core/conc#331 0.0000 7.8539 + sobel:core/conc#331.itm 0.0000 7.8539 + sobel:core/ACC1:acc#189 mgc_add_6_0_6_0_6 1.0162 8.8701 + sobel:core/ACC1:acc#189.itm 0.0000 8.8701 + sobel:core/ACC1:slc#38 0.0000 8.8701 + sobel:core/acc.imod.sva 0.0000 8.8701 + sobel:core/slc(acc.imod.sva)#10 0.0000 8.8701 + sobel:core/slc(acc.imod.sva)#10.itm 0.0000 8.8701 + sobel:core/ACC1:conc#253 0.0000 8.8701 + sobel:core/ACC1:conc#253.itm 0.0000 8.8701 + sobel:core/ACC1:acc#272 mgc_add_13_0_13_0_14 1.4992 10.3693 + sobel:core/ACC1:acc#272.itm 0.0000 10.3693 + sobel:core/ACC1:acc#275 mgc_add_15_0_15_0_16 1.6269 11.9962 + sobel:core/ACC1:acc#275.itm 0.0000 11.9962 + sobel:core/ACC1:acc#279 mgc_add_16_0_16_0_17 1.6898 13.6860 + sobel:core/ACC1:acc#279.itm 0.0000 13.6860 + sobel:core/ACC1:acc#281 mgc_add_16_0_16_0_17 1.6898 15.3757 + sobel:core/ACC1:acc#281.itm 0.0000 15.3757 + sobel:core/reg(ACC1:acc#281.itm#1) mgc_reg_pos_16_1_0_0_0_1_1 0.0000 15.3757 + + 9 sobel:core/reg(regs.regs:slc(regs.regs(2))#6.itm) sobel:core/reg(ACC1:acc#281.itm#1) 15.3757 4.6243 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/reg(regs.regs:slc(regs.regs(2))#6.itm) mgc_reg_pos_10_1_0_0_0_1_1 0.0000 0.0000 + sobel:core/regs.regs:slc(regs.regs(2))#6.itm 0.0000 0.0000 + sobel:core/ACC1:not#73 mgc_not_10 0.0000 0.0000 + sobel:core/ACC1:not#73.itm 0.0000 0.0000 + sobel:core/conc#342 0.0000 0.0000 + sobel:core/conc#342.itm 0.0000 0.0000 + sobel:core/ACC1:acc#178 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#178.itm 0.0000 1.2059 + sobel:core/ACC1:slc#27 0.0000 1.2059 + sobel:core/ACC1:slc#27.itm 0.0000 1.2059 + sobel:core/ACC1:exs#95 0.0000 1.2059 + sobel:core/ACC1:exs#95.itm 0.0000 1.2059 + sobel:core/ACC1:acc#177 mgc_add_16_0_16_0_17 1.6898 2.8957 + sobel:core/ACC1:acc#177.itm 0.0000 2.8957 + sobel:core/ACC1-3:acc mgc_add_17_0_16_0_18 1.7536 4.6493 + sobel:core/acc.idiv.sva 0.0000 4.6493 + sobel:core/slc(acc.idiv.sva)#7 0.0000 4.6493 + sobel:core/slc(acc.idiv.sva)#7.itm 0.0000 4.6493 + sobel:core/ACC1-3:not#5 mgc_not_1 0.0000 4.6493 + sobel:core/ACC1-3:not#5.itm 0.0000 4.6493 + sobel:core/conc#336 0.0000 4.6493 + sobel:core/conc#336.itm 0.0000 4.6493 + sobel:core/ACC1:acc#181 mgc_add_2_0_2_0_3 0.6525 5.3018 + sobel:core/ACC1:acc#181.itm 0.0000 5.3018 + sobel:core/ACC1:slc#30 0.0000 5.3018 + sobel:core/ACC1:slc#30.itm 0.0000 5.3018 + sobel:core/conc#334 0.0000 5.3018 + sobel:core/conc#334.itm 0.0000 5.3018 + sobel:core/ACC1:acc#185 mgc_add_3_0_3_0_4 0.7609 6.0627 + sobel:core/ACC1:acc#185.itm 0.0000 6.0627 + sobel:core/ACC1:slc#34 0.0000 6.0627 + sobel:core/ACC1:slc#34.itm 0.0000 6.0627 + sobel:core/conc#333 0.0000 6.0627 + sobel:core/conc#333.itm 0.0000 6.0627 + sobel:core/ACC1:acc#187 mgc_add_4_0_4_0_5 0.8536 6.9163 + sobel:core/ACC1:acc#187.itm 0.0000 6.9163 + sobel:core/ACC1:slc#36 0.0000 6.9163 + sobel:core/ACC1:slc#36.itm 0.0000 6.9163 + sobel:core/conc#332 0.0000 6.9163 + sobel:core/conc#332.itm 0.0000 6.9163 + sobel:core/ACC1:acc#188 mgc_add_5_0_5_0_6 0.9376 7.8539 + sobel:core/ACC1:acc#188.itm 0.0000 7.8539 + sobel:core/ACC1:slc#37 0.0000 7.8539 + sobel:core/ACC1:slc#37.itm 0.0000 7.8539 + sobel:core/conc#331 0.0000 7.8539 + sobel:core/conc#331.itm 0.0000 7.8539 + sobel:core/ACC1:acc#189 mgc_add_6_0_6_0_6 1.0162 8.8701 + sobel:core/ACC1:acc#189.itm 0.0000 8.8701 + sobel:core/ACC1:slc#38 0.0000 8.8701 + sobel:core/acc.imod.sva 0.0000 8.8701 + sobel:core/slc(acc.imod.sva)#10 0.0000 8.8701 + sobel:core/slc(acc.imod.sva)#10.itm 0.0000 8.8701 + sobel:core/ACC1:conc#253 0.0000 8.8701 + sobel:core/ACC1:conc#253.itm 0.0000 8.8701 + sobel:core/ACC1:acc#272 mgc_add_13_0_13_0_14 1.4992 10.3693 + sobel:core/ACC1:acc#272.itm 0.0000 10.3693 + sobel:core/ACC1:acc#275 mgc_add_15_0_15_0_16 1.6269 11.9962 + sobel:core/ACC1:acc#275.itm 0.0000 11.9962 + sobel:core/ACC1:acc#279 mgc_add_16_0_16_0_17 1.6898 13.6860 + sobel:core/ACC1:acc#279.itm 0.0000 13.6860 + sobel:core/ACC1:acc#281 mgc_add_16_0_16_0_17 1.6898 15.3757 + sobel:core/ACC1:acc#281.itm 0.0000 15.3757 + sobel:core/reg(ACC1:acc#281.itm#1) mgc_reg_pos_16_1_0_0_0_1_1 0.0000 15.3757 + + 10 sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#281.itm#1) 15.3757 4.6243 + + Instance Component Delta Delay + -------- --------- ----- ----- + sobel:core/vin:rsc:mgc_in_wire.d 0.0000 0.0000 + sobel:core/slc(regs.regs(0).sva#4)#1 0.0000 0.0000 + sobel:core/slc(regs.regs(0).sva#4)#1.itm 0.0000 0.0000 + sobel:core/conc#343 0.0000 0.0000 + sobel:core/conc#343.itm 0.0000 0.0000 + sobel:core/ACC1:acc#178 mgc_add_11_1_11_1_12 1.2059 1.2059 + sobel:core/ACC1:acc#178.itm 0.0000 1.2059 + sobel:core/ACC1:slc#27 0.0000 1.2059 + sobel:core/ACC1:slc#27.itm 0.0000 1.2059 + sobel:core/ACC1:exs#95 0.0000 1.2059 + sobel:core/ACC1:exs#95.itm 0.0000 1.2059 + sobel:core/ACC1:acc#177 mgc_add_16_0_16_0_17 1.6898 2.8957 + sobel:core/ACC1:acc#177.itm 0.0000 2.8957 + sobel:core/ACC1-3:acc mgc_add_17_0_16_0_18 1.7536 4.6493 + sobel:core/acc.idiv.sva 0.0000 4.6493 + sobel:core/slc(acc.idiv.sva)#7 0.0000 4.6493 + sobel:core/slc(acc.idiv.sva)#7.itm 0.0000 4.6493 + sobel:core/ACC1-3:not#5 mgc_not_1 0.0000 4.6493 + sobel:core/ACC1-3:not#5.itm 0.0000 4.6493 + sobel:core/conc#336 0.0000 4.6493 + sobel:core/conc#336.itm 0.0000 4.6493 + sobel:core/ACC1:acc#181 mgc_add_2_0_2_0_3 0.6525 5.3018 + sobel:core/ACC1:acc#181.itm 0.0000 5.3018 + sobel:core/ACC1:slc#30 0.0000 5.3018 + sobel:core/ACC1:slc#30.itm 0.0000 5.3018 + sobel:core/conc#334 0.0000 5.3018 + sobel:core/conc#334.itm 0.0000 5.3018 + sobel:core/ACC1:acc#185 mgc_add_3_0_3_0_4 0.7609 6.0627 + sobel:core/ACC1:acc#185.itm 0.0000 6.0627 + sobel:core/ACC1:slc#34 0.0000 6.0627 + sobel:core/ACC1:slc#34.itm 0.0000 6.0627 + sobel:core/conc#333 0.0000 6.0627 + sobel:core/conc#333.itm 0.0000 6.0627 + sobel:core/ACC1:acc#187 mgc_add_4_0_4_0_5 0.8536 6.9163 + sobel:core/ACC1:acc#187.itm 0.0000 6.9163 + sobel:core/ACC1:slc#36 0.0000 6.9163 + sobel:core/ACC1:slc#36.itm 0.0000 6.9163 + sobel:core/conc#332 0.0000 6.9163 + sobel:core/conc#332.itm 0.0000 6.9163 + sobel:core/ACC1:acc#188 mgc_add_5_0_5_0_6 0.9376 7.8539 + sobel:core/ACC1:acc#188.itm 0.0000 7.8539 + sobel:core/ACC1:slc#37 0.0000 7.8539 + sobel:core/ACC1:slc#37.itm 0.0000 7.8539 + sobel:core/conc#331 0.0000 7.8539 + sobel:core/conc#331.itm 0.0000 7.8539 + sobel:core/ACC1:acc#189 mgc_add_6_0_6_0_6 1.0162 8.8701 + sobel:core/ACC1:acc#189.itm 0.0000 8.8701 + sobel:core/ACC1:slc#38 0.0000 8.8701 + sobel:core/acc.imod.sva 0.0000 8.8701 + sobel:core/slc(acc.imod.sva)#10 0.0000 8.8701 + sobel:core/slc(acc.imod.sva)#10.itm 0.0000 8.8701 + sobel:core/ACC1:conc#253 0.0000 8.8701 + sobel:core/ACC1:conc#253.itm 0.0000 8.8701 + sobel:core/ACC1:acc#272 mgc_add_13_0_13_0_14 1.4992 10.3693 + sobel:core/ACC1:acc#272.itm 0.0000 10.3693 + sobel:core/ACC1:acc#275 mgc_add_15_0_15_0_16 1.6269 11.9962 + sobel:core/ACC1:acc#275.itm 0.0000 11.9962 + sobel:core/ACC1:acc#279 mgc_add_16_0_16_0_17 1.6898 13.6860 + sobel:core/ACC1:acc#279.itm 0.0000 13.6860 + sobel:core/ACC1:acc#281 mgc_add_16_0_16_0_17 1.6898 15.3757 + sobel:core/ACC1:acc#281.itm 0.0000 15.3757 + sobel:core/reg(ACC1:acc#281.itm#1) mgc_reg_pos_16_1_0_0_0_1_1 0.0000 15.3757 + + + Register Input and Register-to-Output Slack + Clock period or pin-to-reg delay constraint (clk): 20.0 + Clock uncertainty constraint (clk) : 0.0 + + Instance Port Slack (Delay) Messages + ------------------------------------------------------- ------------------------------- ------- ------- -------- + sobel:core/reg(vout:rsc:mgc_out_stdreg.d) mux.itm 10.7763 9.2237 + sobel:core/reg(intensity:slc(intensity#2.sg1)#9.itm#1) slc(intensity#2.sg1.sva)#4.itm 6.5698 13.4302 + sobel:core/reg(intensity:slc(intensity#2.sg1)#11.itm#1) slc(intensity#2.sg1.sva)#3.itm 6.5698 13.4302 + sobel:core/reg(intensity:slc(intensity#2.sg1).itm#1) slc(intensity#2.sg1.sva)#2.itm 6.5698 13.4302 + sobel:core/reg(intensity:slc(intensity#2.sg1)#12.itm#1) slc(intensity#2.sg1.sva).itm 6.5698 13.4302 + sobel:core/reg(FRAME:acc#12.itm#1) FRAME:acc#12.itm 4.0177 15.9823 + sobel:core/reg(main.stage_0#2) C1365_11#67 20.0000 0.0000 + sobel:core/reg(main.stage_0#3) main.stage_0#2 20.0000 0.0000 + sobel:core/reg(ACC1:acc#281.itm#1) ACC1:acc#281.itm 4.6243 15.3757 + sobel:core/reg(mul#1.itm#1) mul#1.itm 11.5784 8.4216 + sobel:core/reg(ACC1-2:slc(acc.idiv)#131.itm#1) slc(acc.idiv#3.sva)#27.itm 16.5566 3.4434 + sobel:core/reg(ACC1:mul#99.itm#1) ACC1:mul#99.itm 11.8342 8.1658 + sobel:core/reg(ACC1:slc(acc.imod#17)#8.itm#1) slc(acc.imod#17.sva)#2.itm 12.3359 7.6641 + sobel:core/reg(ACC1-2:slc(acc.idiv)#106.itm#1) slc(acc.idiv#3.sva)#19.itm 16.5566 3.4434 + sobel:core/reg(ACC1:acc#264.itm#1) ACC1:acc#264.itm 5.0725 14.9275 + sobel:core/reg(ACC1:mul#90.itm#1) ACC1:mul#90.itm 11.6637 8.3363 + sobel:core/reg(ACC1:mul#91.itm#1) ACC1:mul#91.itm 11.5784 8.4216 + sobel:core/reg(ACC1:mul#104.itm#1) ACC1:mul#104.itm 13.0067 6.9933 + sobel:core/reg(ACC1:slc(acc.idiv#2)#90.itm#1) slc(acc.idiv#2.sva)#19.itm 15.4177 4.5823 + sobel:core/reg(ACC1-3:slc(acc.idiv)#132.itm#1) slc(acc.idiv.sva)#24.itm 15.3507 4.6493 + sobel:core/reg(ACC1:mul#103.itm#1) ACC1:mul#103.itm 13.0401 6.9599 + sobel:core/reg(ACC1:slc(acc.idiv)#91.itm#1) slc(acc.idiv.sva)#19.itm 15.3507 4.6493 + sobel:core/reg(ACC1-3:slc(acc.idiv)#131.itm#1) slc(acc.idiv.sva)#22.itm 15.3507 4.6493 + sobel:core/reg(ACC1:mul#98.itm#1) ACC1:mul#98.itm 11.9988 8.0012 + sobel:core/reg(ACC1:slc(acc.idiv#3)#36.itm#1) slc(acc.idiv#3.sva)#25.itm 16.5566 3.4434 + sobel:core/reg(ACC1-2:slc(acc.idiv)#132.itm#1) slc(acc.idiv#3.sva)#22.itm 16.5566 3.4434 + sobel:core/reg(ACC1:acc#252.itm#1) ACC1:acc#252.itm 4.9873 15.0127 + sobel:core/reg(ACC1:acc#251.itm#1) ACC1:acc#251.itm 7.2314 12.7686 + sobel:core/reg(ACC1:acc#255.itm#1) ACC1:acc#255.itm 10.9826 9.0174 + sobel:core/reg(ACC1:mul#89.itm#1) ACC1:mul#89.itm 11.8008 8.1992 + sobel:core/reg(ACC1:acc#268.itm#1) ACC1:acc#268.itm 8.0012 11.9988 + sobel:core/reg(ACC1:mul#96.itm#1) ACC1:mul#96.itm 12.7844 7.2156 + sobel:core/reg(ACC1:slc(acc.imod)#28.itm#1) slc(acc.imod.sva).itm 11.1299 8.8701 + sobel:core/reg(regs.regs:slc(regs.regs(2).sg2)#1.itm) slc(regs.regs(1).sg2.sva)#2.itm 20.0000 0.0000 + sobel:core/reg(regs.regs:slc(regs.regs(2).sg2)#2.itm) slc(regs.regs(1).sg2.sva)#1.itm 20.0000 0.0000 + sobel:core/reg(regs.regs:slc(regs.regs(2).sg2).itm) slc(regs.regs(1).sg2.sva).itm 20.0000 0.0000 + sobel:core/reg(regs.regs:slc(regs.regs(2))#6.itm) slc(regs.regs(1)#1.sva)#2.itm 20.0000 0.0000 + sobel:core/reg(regs.regs:slc(regs.regs(2))#7.itm) slc(regs.regs(1)#1.sva)#1.itm 20.0000 0.0000 + sobel:core/reg(regs.regs:slc(regs.regs(2)).itm) slc(regs.regs(1)#1.sva).itm 20.0000 0.0000 + sobel:core/reg(regs.regs(1).sg2.sva) slc(regs.regs(0).sva#7).itm 20.0000 0.0000 + sobel:core/reg(regs.regs(1)#1.sva) slc(regs.regs(0).sva#8).itm 20.0000 0.0000 + sobel vout:rsc.z 20.0000 0.0000 + + Operator Bitwidth Summary + Operation Size (bits) Count + ---------- ----------- ----- + add + - 18 4 + - 17 9 + - 16 3 + - 15 2 + - 14 4 + - 13 1 + - 12 6 + - 11 5 + - 10 3 + - 9 3 + - 8 2 + - 7 3 + - 6 17 + - 5 13 + - 4 37 + - 3 46 + - 2 22 + mul + - 16 2 + - 14 3 + - 12 4 + - 11 5 + - 9 5 + - 8 4 + mux + - 1 1 + not + - 10 3 + - 3 4 + - 1 77 + or + - 2 2 + read_port + - 90 1 + reg + - 30 3 + - 16 1 + - 14 2 + - 13 1 + - 12 2 + - 10 9 + - 8 2 + - 7 1 + - 6 5 + - 3 1 + - 2 1 + - 1 13 + write_port + - 30 1 + + End of Report |