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diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.rpt new file mode 100644 index 0000000..760d753 --- /dev/null +++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.rpt @@ -0,0 +1,10106 @@ +TimeQuest Timing Analyzer report for DE0_D5M +Mon Mar 17 10:02:50 2014 +Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. SDC File List + 5. Clocks + 6. Slow 1200mV 85C Model Fmax Summary + 7. Timing Closure Recommendations + 8. Slow 1200mV 85C Model Setup Summary + 9. Slow 1200mV 85C Model Hold Summary + 10. Slow 1200mV 85C Model Recovery Summary + 11. Slow 1200mV 85C Model Removal Summary + 12. Slow 1200mV 85C Model Minimum Pulse Width Summary + 13. Slow 1200mV 85C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 14. Slow 1200mV 85C Model Setup: 'CLOCK_50' + 15. Slow 1200mV 85C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 16. Slow 1200mV 85C Model Hold: 'CLOCK_50' + 17. Slow 1200mV 85C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 18. Slow 1200mV 85C Model Recovery: 'CLOCK_50' + 19. Slow 1200mV 85C Model Removal: 'CLOCK_50' + 20. Slow 1200mV 85C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 21. Slow 1200mV 85C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 22. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' + 23. Setup Times + 24. Hold Times + 25. Clock to Output Times + 26. Minimum Clock to Output Times + 27. Output Enable Times + 28. Minimum Output Enable Times + 29. Output Disable Times + 30. Minimum Output Disable Times + 31. MTBF Summary + 32. Synchronizer Summary + 33. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years + 34. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years + 35. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years + 36. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years + 37. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years + 38. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years + 39. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years + 40. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years + 41. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years + 42. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years + 43. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years + 44. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years + 45. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years + 46. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years + 47. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years + 48. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years + 49. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years + 50. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years + 51. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years + 52. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years + 53. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years + 54. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years + 55. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years + 56. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years + 57. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years + 58. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years + 59. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years + 60. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years + 61. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years + 62. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years + 63. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years + 64. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years + 65. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years + 66. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years + 67. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years + 68. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years + 69. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years + 70. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years + 71. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years + 72. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years + 73. Slow 1200mV 0C Model Fmax Summary + 74. Slow 1200mV 0C Model Setup Summary + 75. Slow 1200mV 0C Model Hold Summary + 76. Slow 1200mV 0C Model Recovery Summary + 77. Slow 1200mV 0C Model Removal Summary + 78. Slow 1200mV 0C Model Minimum Pulse Width Summary + 79. Slow 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 80. Slow 1200mV 0C Model Setup: 'CLOCK_50' + 81. Slow 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 82. Slow 1200mV 0C Model Hold: 'CLOCK_50' + 83. Slow 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 84. Slow 1200mV 0C Model Recovery: 'CLOCK_50' + 85. Slow 1200mV 0C Model Removal: 'CLOCK_50' + 86. Slow 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 87. Slow 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 88. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' + 89. Setup Times + 90. Hold Times + 91. Clock to Output Times + 92. Minimum Clock to Output Times + 93. Output Enable Times + 94. Minimum Output Enable Times + 95. Output Disable Times + 96. Minimum Output Disable Times + 97. MTBF Summary + 98. Synchronizer Summary + 99. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +100. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years +101. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years +102. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years +103. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years +104. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years +105. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years +106. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years +107. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years +108. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years +109. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years +110. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years +111. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years +112. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years +113. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years +114. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years +115. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years +116. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years +117. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years +118. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years +119. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years +120. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years +121. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years +122. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years +123. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years +124. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years +125. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years +126. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years +127. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years +128. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years +129. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years +130. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years +131. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years +132. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years +133. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years +134. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years +135. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years +136. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years +137. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years +138. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years +139. Fast 1200mV 0C Model Setup Summary +140. Fast 1200mV 0C Model Hold Summary +141. Fast 1200mV 0C Model Recovery Summary +142. Fast 1200mV 0C Model Removal Summary +143. Fast 1200mV 0C Model Minimum Pulse Width Summary +144. Fast 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' +145. Fast 1200mV 0C Model Setup: 'CLOCK_50' +146. Fast 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' +147. Fast 1200mV 0C Model Hold: 'CLOCK_50' +148. Fast 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' +149. Fast 1200mV 0C Model Recovery: 'CLOCK_50' +150. Fast 1200mV 0C Model Removal: 'CLOCK_50' +151. Fast 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' +152. Fast 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' +153. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' +154. Setup Times +155. Hold Times +156. Clock to Output Times +157. Minimum Clock to Output Times +158. Output Enable Times +159. Minimum Output Enable Times +160. Output Disable Times +161. Minimum Output Disable Times +162. MTBF Summary +163. Synchronizer Summary +164. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +165. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years +166. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years +167. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years +168. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years +169. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years +170. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years +171. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years +172. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years +173. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years +174. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years +175. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years +176. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years +177. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years +178. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years +179. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years +180. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years +181. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years +182. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years +183. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years +184. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years +185. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years +186. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years +187. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years +188. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years +189. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years +190. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years +191. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years +192. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years +193. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years +194. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years +195. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years +196. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years +197. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years +198. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years +199. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years +200. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years +201. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years +202. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years +203. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years +204. Multicorner Timing Analysis Summary +205. Setup Times +206. Hold Times +207. Clock to Output Times +208. Minimum Clock to Output Times +209. Board Trace Model Assignments +210. Input Transition Times +211. Slow Corner Signal Integrity Metrics +212. Fast Corner Signal Integrity Metrics +213. Setup Transfers +214. Hold Transfers +215. Recovery Transfers +216. Removal Transfers +217. Report TCCS +218. Report RSKM +219. Unconstrained Paths +220. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+-----------------------------------------------------+ +; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Full Version ; +; Revision Name ; DE0_D5M ; +; Device Family ; Cyclone III ; +; Device Name ; EP3C16F484C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++--------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; < 0.1% ; +; Processors 5-8 ; 0.0% ; ++----------------------------+-------------+ + + ++---------------------------------------------------+ +; SDC File List ; ++---------------+--------+--------------------------+ +; SDC File Path ; Status ; Read at ; ++---------------+--------+--------------------------+ +; DE0_D5M.sdc ; OK ; Mon Mar 17 10:02:47 2014 ; ++---------------+--------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+ +; CLOCK_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8.000 ; 125.0 MHz ; 0.000 ; 4.000 ; 50.00 ; 2 ; 5 ; ; ; ; ; false ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|inclk[0] ; { inst|u6|altpll_component|auto_generated|pll1|clk[0] } ; +; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 8.000 ; 125.0 MHz ; -2.600 ; 1.400 ; 50.00 ; 2 ; 5 ; -117.0 ; ; ; ; false ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|inclk[0] ; { inst|u6|altpll_component|auto_generated|pll1|clk[1] } ; ++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++------------+-----------------+-----------------------------------------------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+-----------------------------------------------------+------+ +; 174.7 MHz ; 174.7 MHz ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; +; 207.04 MHz ; 207.04 MHz ; CLOCK_50 ; ; ++------------+-----------------+-----------------------------------------------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + ++------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup Summary ; ++-----------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+--------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.454 ; -22.246 ; +; CLOCK_50 ; 15.170 ; 0.000 ; ++-----------------------------------------------------+--------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.214 ; 0.000 ; +; CLOCK_50 ; 0.358 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Recovery Summary ; ++-----------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+--------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -1.497 ; -338.162 ; +; CLOCK_50 ; 14.980 ; 0.000 ; ++-----------------------------------------------------+--------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Removal Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; CLOCK_50 ; 1.616 ; 0.000 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.132 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.736 ; 0.000 ; +; CLOCK_50 ; 9.580 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; -0.454 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.208 ; 2.261 ; +; -0.454 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.208 ; 2.261 ; +; -0.454 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.208 ; 2.261 ; +; -0.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.250 ; +; -0.392 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.178 ; 2.229 ; +; -0.392 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.178 ; 2.229 ; +; -0.392 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.178 ; 2.229 ; +; -0.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.205 ; +; -0.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.205 ; +; -0.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.205 ; +; -0.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.205 ; +; -0.337 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.167 ; +; -0.337 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.167 ; +; -0.337 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.167 ; +; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.146 ; +; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.146 ; +; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.146 ; +; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.146 ; +; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.146 ; +; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.146 ; +; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.146 ; +; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.146 ; +; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.146 ; +; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.146 ; +; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.146 ; +; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.146 ; +; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.146 ; +; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.146 ; +; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.185 ; 2.146 ; +; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.123 ; +; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.123 ; +; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.123 ; +; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.123 ; +; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.123 ; +; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.123 ; +; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.123 ; +; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.123 ; +; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.123 ; +; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.123 ; +; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.123 ; +; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.123 ; +; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.123 ; +; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.123 ; +; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.123 ; +; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.189 ; 2.113 ; +; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.189 ; 2.113 ; +; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.189 ; 2.113 ; +; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.189 ; 2.113 ; +; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.189 ; 2.113 ; +; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.189 ; 2.113 ; +; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.189 ; 2.113 ; +; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.189 ; 2.113 ; +; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.189 ; 2.113 ; +; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.189 ; 2.113 ; +; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.189 ; 2.113 ; +; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.189 ; 2.113 ; +; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.189 ; 2.113 ; +; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.189 ; 2.113 ; +; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.189 ; 2.113 ; +; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.194 ; 1.968 ; +; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.194 ; 1.968 ; +; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.194 ; 1.968 ; +; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.194 ; 1.968 ; +; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.194 ; 1.968 ; +; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.194 ; 1.968 ; +; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.194 ; 1.968 ; +; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.221 ; 1.932 ; +; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.221 ; 1.932 ; +; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.221 ; 1.932 ; +; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.221 ; 1.932 ; +; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.221 ; 1.932 ; +; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.221 ; 1.932 ; +; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.221 ; 1.932 ; +; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.221 ; 1.932 ; +; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.221 ; 1.932 ; +; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.221 ; 1.932 ; +; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.221 ; 1.932 ; +; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.221 ; 1.932 ; +; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.221 ; 1.932 ; +; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.221 ; 1.932 ; +; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.221 ; 1.932 ; +; 2.276 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.086 ; 5.653 ; +; 2.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.088 ; 5.607 ; +; 2.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.088 ; 5.607 ; +; 2.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.088 ; 5.607 ; +; 2.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.088 ; 5.607 ; +; 2.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.278 ; 5.953 ; +; 2.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.088 ; 5.581 ; +; 2.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.088 ; 5.581 ; +; 2.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.088 ; 5.581 ; +; 2.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.086 ; 5.569 ; +; 2.365 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.086 ; 5.564 ; +; 2.384 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.276 ; 5.907 ; +; 2.384 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.276 ; 5.907 ; +; 2.384 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.276 ; 5.907 ; +; 2.384 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.276 ; 5.907 ; +; 2.404 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.088 ; 5.523 ; +; 2.404 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.088 ; 5.523 ; +; 2.404 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.088 ; 5.523 ; +; 2.404 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.088 ; 5.523 ; ++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'CLOCK_50' ; ++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 15.170 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.782 ; +; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.659 ; +; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.659 ; +; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.659 ; +; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.659 ; +; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.659 ; +; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.659 ; +; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.659 ; +; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.659 ; +; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.659 ; +; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.659 ; +; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.659 ; +; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.659 ; +; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.659 ; +; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.650 ; +; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.650 ; +; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.650 ; +; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.650 ; +; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.650 ; +; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.650 ; +; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.650 ; +; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.650 ; +; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.650 ; +; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.650 ; +; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.650 ; +; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.650 ; +; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.650 ; +; 15.384 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.568 ; +; 15.400 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.567 ; +; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.549 ; +; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.549 ; +; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.549 ; +; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.549 ; +; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.549 ; +; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.549 ; +; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.549 ; +; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.549 ; +; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.549 ; +; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.549 ; +; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.549 ; +; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.549 ; +; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.549 ; +; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.549 ; +; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.549 ; +; 15.409 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.558 ; +; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.554 ; +; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.554 ; +; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.554 ; +; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.554 ; +; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.554 ; +; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.554 ; +; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.554 ; +; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.554 ; +; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.554 ; +; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.554 ; +; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.554 ; +; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.554 ; +; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.554 ; +; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.527 ; +; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.527 ; +; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.527 ; +; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.527 ; +; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.527 ; +; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.527 ; +; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.527 ; +; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.527 ; +; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.527 ; +; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.527 ; +; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.527 ; +; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.527 ; +; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.527 ; +; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.527 ; +; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.527 ; +; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.527 ; +; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.484 ; +; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.484 ; +; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.484 ; +; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.484 ; +; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.484 ; +; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.484 ; +; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.484 ; +; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.484 ; +; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.484 ; +; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.484 ; +; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.484 ; +; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.484 ; +; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.484 ; +; 15.474 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.478 ; +; 15.477 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.475 ; +; 15.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.462 ; +; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.416 ; +; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.416 ; +; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.416 ; +; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.416 ; +; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.416 ; +; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.416 ; +; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.416 ; +; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.416 ; +; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.416 ; +; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.048 ; 4.416 ; ++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; 0.214 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.428 ; 0.799 ; +; 0.230 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.428 ; 0.815 ; +; 0.325 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.428 ; 0.910 ; +; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.428 ; 0.911 ; +; 0.334 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.902 ; +; 0.343 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.910 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.912 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.591 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.592 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.592 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.592 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.592 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.592 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.593 ; +; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.593 ; +; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.593 ; +; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.593 ; +; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.593 ; +; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.592 ; +; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.592 ; +; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.594 ; +; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.425 ; 0.943 ; +; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.425 ; 0.943 ; +; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.580 ; +; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.595 ; +; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.580 ; +; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.580 ; +; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.595 ; +; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.595 ; +; 0.372 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.591 ; +; 0.372 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.590 ; +; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[18] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.592 ; +; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.591 ; +; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.592 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.592 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[19] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.592 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[21] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.592 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.592 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.608 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.593 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.593 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.593 ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'CLOCK_50' ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.577 ; +; 0.361 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.580 ; +; 0.381 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.600 ; +; 0.382 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.038 ; 0.577 ; +; 0.385 ; DE0_D5M:inst|rClk[0] ; DE0_D5M:inst|rClk[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.038 ; 0.580 ; +; 0.390 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.609 ; +; 0.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.609 ; +; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.736 ; +; 0.524 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.743 ; +; 0.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.769 ; +; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.775 ; +; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.775 ; +; 0.557 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.776 ; +; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.775 ; +; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.776 ; +; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.776 ; +; 0.558 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.777 ; +; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.776 ; +; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.776 ; +; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.777 ; +; 0.559 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.778 ; +; 0.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.777 ; +; 0.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.777 ; +; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.778 ; +; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.779 ; +; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.779 ; +; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.779 ; +; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.779 ; +; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.780 ; +; 0.562 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.781 ; +; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.780 ; +; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.780 ; +; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.780 ; +; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.781 ; +; 0.563 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.781 ; +; 0.568 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 0.788 ; +; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.788 ; +; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.788 ; +; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.788 ; +; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 0.789 ; +; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 0.789 ; +; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 0.789 ; +; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 0.789 ; +; 0.569 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.788 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 0.790 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 0.790 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 0.790 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 0.790 ; +; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.788 ; +; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.788 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 0.791 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 0.791 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 0.791 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 0.791 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 0.791 ; +; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.789 ; +; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.789 ; +; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.789 ; +; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.790 ; +; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.790 ; +; 0.573 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.792 ; +; 0.573 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 0.793 ; +; 0.573 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 0.793 ; +; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.792 ; +; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.791 ; +; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.791 ; +; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.791 ; +; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.793 ; +; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.792 ; +; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.793 ; +; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.793 ; +; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.793 ; +; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.793 ; +; 0.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.794 ; +; 0.580 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.799 ; +; 0.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.800 ; +; 0.585 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.804 ; +; 0.586 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.805 ; +; 0.606 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.825 ; +; 0.700 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.919 ; +; 0.702 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.921 ; +; 0.710 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.929 ; +; 0.825 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 1.043 ; +; 0.831 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.050 ; +; 0.832 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.051 ; +; 0.832 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.051 ; +; 0.832 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.051 ; +; 0.832 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 1.050 ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.158 ; +; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.158 ; +; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.158 ; +; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.158 ; +; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.158 ; +; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.158 ; +; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.158 ; +; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.158 ; +; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.158 ; +; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.158 ; +; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.158 ; +; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.158 ; +; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.158 ; +; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.158 ; +; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.158 ; +; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.158 ; +; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.162 ; +; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.162 ; +; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.162 ; +; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.162 ; +; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.162 ; +; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.162 ; +; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.162 ; +; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.162 ; +; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.162 ; +; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.162 ; +; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.162 ; +; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.162 ; +; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.162 ; +; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.162 ; +; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.162 ; +; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.162 ; +; -1.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.285 ; 3.200 ; +; -1.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.277 ; 3.204 ; +; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.802 ; +; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.802 ; +; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.802 ; +; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.802 ; +; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.802 ; +; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.802 ; +; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.802 ; +; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.802 ; +; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.802 ; +; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.802 ; +; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.802 ; +; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.802 ; +; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.802 ; +; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.802 ; +; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.802 ; +; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.802 ; +; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.802 ; +; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.805 ; +; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.805 ; +; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.805 ; +; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.805 ; +; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.805 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.804 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.804 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.804 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.806 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.806 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.804 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.806 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.806 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.806 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.806 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.806 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.806 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.806 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.806 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.804 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.806 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.804 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.804 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.804 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.804 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.804 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.804 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.804 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.804 ; +; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.804 ; +; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.803 ; +; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.803 ; +; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.803 ; +; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.803 ; +; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.803 ; +; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.803 ; +; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.803 ; +; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.542 ; 2.797 ; +; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.542 ; 2.797 ; +; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.542 ; 2.797 ; +; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.542 ; 2.797 ; +; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.542 ; 2.797 ; +; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 2.793 ; +; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.546 ; 2.792 ; +; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.546 ; 2.792 ; +; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 2.793 ; +; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 2.793 ; +; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 2.793 ; +; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 2.793 ; ++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Recovery: 'CLOCK_50' ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 14.980 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.066 ; 5.101 ; +; 14.989 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.066 ; 5.092 ; +; 15.085 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.066 ; 4.996 ; +; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.838 ; +; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.838 ; +; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.838 ; +; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.838 ; +; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.838 ; +; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.838 ; +; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.838 ; +; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.838 ; +; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.838 ; +; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.838 ; +; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.838 ; +; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.838 ; +; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.838 ; +; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.838 ; +; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.838 ; +; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.838 ; +; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.829 ; +; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.829 ; +; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.829 ; +; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.829 ; +; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.829 ; +; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.829 ; +; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.829 ; +; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.829 ; +; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.829 ; +; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.829 ; +; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.829 ; +; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.829 ; +; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.829 ; +; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.829 ; +; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.829 ; +; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.829 ; +; 15.144 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.055 ; 4.926 ; +; 15.223 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.066 ; 4.858 ; +; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.733 ; +; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.733 ; +; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.733 ; +; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.733 ; +; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.733 ; +; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.733 ; +; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.733 ; +; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.733 ; +; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.733 ; +; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.733 ; +; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.733 ; +; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.733 ; +; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.733 ; +; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.733 ; +; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.733 ; +; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.733 ; +; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.663 ; +; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.663 ; +; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.663 ; +; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.663 ; +; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.663 ; +; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.663 ; +; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.663 ; +; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.663 ; +; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.663 ; +; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.663 ; +; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.663 ; +; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.663 ; +; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.663 ; +; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.663 ; +; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.663 ; +; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.663 ; +; 15.287 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.055 ; 4.783 ; +; 15.290 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.055 ; 4.780 ; +; 15.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.055 ; 4.773 ; +; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.595 ; +; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.595 ; +; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.595 ; +; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.595 ; +; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.595 ; +; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.595 ; +; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.595 ; +; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.595 ; +; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.595 ; +; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.595 ; +; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.595 ; +; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.595 ; +; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.595 ; +; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.595 ; +; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.595 ; +; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.595 ; +; 15.384 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.055 ; 4.686 ; +; 15.392 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.055 ; 4.678 ; +; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.520 ; +; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.520 ; +; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.520 ; +; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.520 ; +; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.520 ; +; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.520 ; +; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.520 ; +; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.520 ; +; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.520 ; +; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 4.520 ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Removal: 'CLOCK_50' ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.827 ; +; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.827 ; +; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.827 ; +; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.827 ; +; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.827 ; +; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.827 ; +; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.827 ; +; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.827 ; +; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.827 ; +; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.827 ; +; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.827 ; +; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.827 ; +; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.827 ; +; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.827 ; +; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.827 ; +; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.827 ; +; 1.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.228 ; 2.081 ; +; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.970 ; +; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.970 ; +; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.970 ; +; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.970 ; +; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.970 ; +; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.970 ; +; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.970 ; +; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.970 ; +; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.970 ; +; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.970 ; +; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.970 ; +; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.970 ; +; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.970 ; +; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.970 ; +; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.970 ; +; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.970 ; +; 1.838 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.228 ; 2.223 ; +; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.655 ; +; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.655 ; +; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.655 ; +; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.655 ; +; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.655 ; +; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.655 ; +; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.655 ; +; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.655 ; +; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.655 ; +; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.655 ; +; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.655 ; +; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.655 ; +; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.655 ; +; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.655 ; +; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.655 ; +; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.655 ; +; 2.514 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.238 ; 2.909 ; +; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.999 ; +; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.999 ; +; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.999 ; +; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.999 ; +; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.999 ; +; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.999 ; +; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.999 ; +; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.999 ; +; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.999 ; +; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.999 ; +; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.999 ; +; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.999 ; +; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.999 ; +; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.999 ; +; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.999 ; +; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.999 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 3.028 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 3.028 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 3.028 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 3.028 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 3.028 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 3.028 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 3.028 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 3.028 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 3.028 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 3.028 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 3.028 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 3.028 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 3.028 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 3.028 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 3.028 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 3.028 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.069 ; 3.031 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.069 ; 3.031 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.069 ; 3.031 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.069 ; 3.031 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.069 ; 3.031 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.069 ; 3.031 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.069 ; 3.031 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.069 ; 3.031 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.069 ; 3.031 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.069 ; 3.031 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.069 ; 3.031 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.069 ; 3.031 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.069 ; 3.031 ; +; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.069 ; 3.031 ; +; 2.807 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 3.019 ; +; 2.807 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 3.019 ; +; 2.807 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 3.019 ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; 4.132 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.681 ; 2.608 ; +; 4.132 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.681 ; 2.608 ; +; 4.132 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.681 ; 2.608 ; +; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.684 ; 2.606 ; +; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.684 ; 2.606 ; +; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.684 ; 2.606 ; +; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.684 ; 2.606 ; +; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.684 ; 2.606 ; +; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.684 ; 2.606 ; +; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.684 ; 2.606 ; +; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.684 ; 2.606 ; +; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.684 ; 2.606 ; +; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.684 ; 2.606 ; +; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.676 ; 2.614 ; +; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.676 ; 2.614 ; +; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.676 ; 2.614 ; +; 4.135 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.679 ; 2.613 ; +; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.680 ; 2.614 ; +; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.680 ; 2.614 ; +; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.680 ; 2.614 ; +; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.694 ; 2.605 ; +; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.694 ; 2.605 ; +; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.694 ; 2.605 ; +; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.694 ; 2.605 ; +; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.694 ; 2.605 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.692 ; 2.608 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.692 ; 2.608 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.692 ; 2.608 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.692 ; 2.608 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.692 ; 2.608 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.692 ; 2.608 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.692 ; 2.608 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.692 ; 2.608 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.692 ; 2.608 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.692 ; 2.608 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.611 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.611 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.611 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.611 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.611 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.611 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.611 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.611 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.611 ; +; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.611 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.687 ; 2.614 ; +; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.613 ; +; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.613 ; +; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.613 ; +; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.613 ; +; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.613 ; +; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.613 ; +; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.688 ; 2.614 ; +; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.688 ; 2.614 ; +; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.688 ; 2.614 ; +; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.688 ; 2.614 ; +; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.688 ; 2.614 ; +; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.688 ; 2.614 ; +; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.688 ; 2.614 ; +; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.613 ; +; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.613 ; +; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.613 ; +; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.613 ; +; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.613 ; +; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.613 ; +; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.613 ; +; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.613 ; +; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.613 ; +; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.613 ; +; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.688 ; 2.615 ; +; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.688 ; 2.615 ; +; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.613 ; +; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.613 ; +; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.613 ; +; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.613 ; +; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.613 ; +; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.615 ; +; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.615 ; +; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.615 ; +; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.615 ; +; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.615 ; +; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.615 ; +; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.615 ; +; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.615 ; +; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.615 ; +; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.615 ; +; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.615 ; +; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.615 ; +; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.615 ; +; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.615 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.691 ; 2.615 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.691 ; 2.615 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.691 ; 2.615 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.691 ; 2.615 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.691 ; 2.615 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.691 ; 2.615 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.691 ; 2.615 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.691 ; 2.615 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.691 ; 2.615 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.691 ; 2.615 ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 3.736 ; 3.966 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0 ; +; 3.736 ; 3.966 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0 ; +; 3.736 ; 3.966 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg ; +; 3.737 ; 3.967 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0 ; +; 3.737 ; 3.967 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0 ; +; 3.737 ; 3.967 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[1] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|CAS_N ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|CS_N[0] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|PM_STOP ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[11] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[1] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[8] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CAS_N ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CS_N[0] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[7] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_initial ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[12] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[14] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[19] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[20] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[21] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[22] ; +; 3.754 ; 3.970 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[9] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|DQM[0] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[0] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[2] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[5] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[7] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[2] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[3] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[4] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[5] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[6] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[7] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[8] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; ++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' ; ++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+ +; 9.580 ; 9.764 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|rClk[0] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_1 ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; +; 9.632 ; 9.816 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; +; 9.740 ; 9.740 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; 9.740 ; 9.740 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; 9.740 ; 9.740 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|observablevcoout ; +; 9.742 ; 9.742 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst|rClk[0]|clk ; ++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; 4.050 ; 4.731 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; 4.050 ; 4.731 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; 3.252 ; 3.792 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; 4.454 ; 5.044 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 4.454 ; 5.044 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 4.228 ; 4.804 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 4.088 ; 4.586 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.985 ; 4.485 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.971 ; 4.476 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.720 ; 4.223 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.722 ; 4.235 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.708 ; 4.219 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; -1.516 ; -2.017 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; -1.569 ; -2.104 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; -1.516 ; -2.017 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; -3.030 ; -3.522 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; -3.758 ; -4.336 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; -3.529 ; -4.083 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; -3.407 ; -3.896 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; -3.296 ; -3.778 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; -3.282 ; -3.768 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; -3.041 ; -3.526 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; -3.044 ; -3.537 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; -3.030 ; -3.522 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 7.004 ; 7.069 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 7.004 ; 7.069 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 6.882 ; 6.755 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 4.954 ; 4.908 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 4.954 ; 4.908 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 5.291 ; 5.346 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 3.733 ; 3.645 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 3.700 ; 3.596 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 3.732 ; 3.645 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 3.589 ; 3.523 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 3.733 ; 3.638 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 3.576 ; 3.509 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 3.527 ; 3.439 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 3.575 ; 3.472 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 3.357 ; 3.274 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 3.532 ; 3.433 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 3.594 ; 3.493 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 3.515 ; 3.425 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 3.381 ; 3.299 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 3.540 ; 3.449 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 3.624 ; 3.533 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 3.569 ; 3.489 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 3.685 ; 3.582 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 7.764 ; 7.387 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 5.853 ; 5.686 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 5.923 ; 5.772 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 5.841 ; 5.703 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 7.764 ; 7.387 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 5.747 ; 5.603 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 5.667 ; 5.552 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 6.210 ; 6.073 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 5.690 ; 5.589 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 5.631 ; 5.599 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 5.178 ; 5.147 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 5.631 ; 5.557 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 5.436 ; 5.269 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 5.663 ; 5.519 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 5.466 ; 5.409 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 6.063 ; 5.900 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 5.624 ; 5.492 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 3.597 ; 3.540 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 3.733 ; 3.650 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 3.431 ; 3.340 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 5.576 ; 5.291 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -0.575 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -0.703 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 6.707 ; 6.581 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 6.825 ; 6.882 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 6.707 ; 6.581 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 4.856 ; 4.807 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 4.856 ; 4.807 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 5.175 ; 5.233 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 2.922 ; 2.838 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 3.251 ; 3.147 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 3.283 ; 3.195 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 3.146 ; 3.077 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 3.283 ; 3.187 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 3.133 ; 3.064 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 3.085 ; 2.996 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 3.132 ; 3.029 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 2.922 ; 2.838 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 3.090 ; 2.989 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 3.150 ; 3.048 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 3.074 ; 2.982 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 2.945 ; 2.861 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 3.098 ; 3.006 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 3.179 ; 3.087 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 3.125 ; 3.044 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 3.236 ; 3.132 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 3.781 ; 3.692 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 4.426 ; 4.325 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 4.302 ; 4.232 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 4.235 ; 4.172 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 6.143 ; 5.835 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 4.933 ; 4.852 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 4.418 ; 4.365 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 4.586 ; 4.522 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 4.454 ; 4.407 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 4.187 ; 4.101 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 4.369 ; 4.307 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 4.773 ; 4.673 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 4.165 ; 4.074 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.781 ; 3.692 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 4.341 ; 4.260 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 4.381 ; 4.264 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 4.156 ; 4.070 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 3.153 ; 3.092 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 3.282 ; 3.197 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 2.994 ; 2.900 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 5.132 ; 4.844 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -0.948 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -1.075 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Output Enable Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 3.158 ; 3.158 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.158 ; 3.158 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.664 ; 3.664 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.674 ; 3.674 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.461 ; 3.461 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.863 ; 3.863 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.664 ; 3.664 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.883 ; 3.883 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.847 ; 3.847 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.170 ; 3.170 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.170 ; 3.170 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.178 ; 3.178 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.160 ; 3.160 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.168 ; 3.168 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.178 ; 3.178 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.158 ; 3.158 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.863 ; 3.863 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.449 ; 2.449 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.449 ; 2.449 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.935 ; 2.935 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.945 ; 2.945 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.739 ; 2.739 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.126 ; 3.126 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.935 ; 2.935 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.146 ; 3.146 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.111 ; 3.111 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.461 ; 2.461 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.461 ; 2.461 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.469 ; 2.469 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.451 ; 2.451 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.459 ; 2.459 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.469 ; 2.469 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.449 ; 2.449 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.126 ; 3.126 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Output Disable Times ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 3.085 ; 3.187 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.085 ; 3.187 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.605 ; 3.707 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.615 ; 3.717 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.406 ; 3.508 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.802 ; 3.904 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.605 ; 3.707 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.822 ; 3.924 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.796 ; 3.898 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.104 ; 3.206 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.104 ; 3.206 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.105 ; 3.207 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.094 ; 3.196 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.095 ; 3.197 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.105 ; 3.207 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.085 ; 3.187 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.802 ; 3.904 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.477 ; 2.573 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.477 ; 2.573 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.976 ; 3.072 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.986 ; 3.082 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.785 ; 2.881 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.165 ; 3.261 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.976 ; 3.072 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.185 ; 3.281 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.159 ; 3.255 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.496 ; 2.592 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.496 ; 2.592 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.497 ; 2.593 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.486 ; 2.582 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.487 ; 2.583 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.497 ; 2.593 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.477 ; 2.573 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.165 ; 3.261 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ + + +---------------- +; MTBF Summary ; +---------------- +Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 40 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 11.051 ns + +Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 + + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Worst-Case MTBF (Years) ; Typical MTBF (Years) ; Included in Design MTBF ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.051 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; ; ; ; 7.249 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; ; ; ; 3.802 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.254 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; ; ; ; 6.970 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; ; ; ; 4.284 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.326 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; ; ; ; 7.252 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; ; ; ; 4.074 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.397 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; ; ; ; 7.105 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; ; ; ; 4.292 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.434 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; ; ; ; 6.899 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; ; ; ; 4.535 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.441 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; ; ; ; 7.105 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; ; ; ; 4.336 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.471 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; ; ; ; 7.252 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; ; ; ; 4.219 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.502 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; ; ; ; 7.249 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; ; ; ; 4.253 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.552 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; ; ; ; 6.898 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; ; ; ; 4.654 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.577 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; ; ; ; 7.107 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; ; ; ; 4.470 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.605 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; ; ; ; 7.105 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; ; ; ; 4.500 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.628 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; ; ; ; 7.103 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; ; ; ; 4.525 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.632 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; ; ; ; 7.250 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; ; ; ; 4.382 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.636 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; ; ; ; 7.105 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; ; ; ; 4.531 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.670 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; ; ; ; 7.253 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; ; ; ; 4.417 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.684 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; ; ; ; 7.106 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; ; ; ; 4.578 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.709 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; ; ; ; 6.901 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; ; ; ; 4.808 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.717 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; ; ; ; 6.902 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; ; ; ; 4.815 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.748 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; ; ; ; 7.109 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; ; ; ; 4.639 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.765 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; ; ; ; 7.252 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; ; ; ; 4.513 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.790 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; ; ; ; 6.773 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; ; ; ; 5.017 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.795 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; ; ; ; 7.104 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; ; ; ; 4.691 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.838 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ; ; ; 6.985 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; ; ; ; 4.853 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.840 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ; ; ; 6.984 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; ; ; ; 4.856 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.862 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; ; ; ; 6.905 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; ; ; ; 4.957 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.886 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; ; ; ; 7.108 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; ; ; ; 4.778 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.896 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; ; ; ; 7.251 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; ; ; ; 4.645 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.906 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; ; ; ; 6.662 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; ; ; ; 5.244 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.918 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; ; ; ; 7.251 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; ; ; ; 4.667 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.991 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; ; ; ; 6.902 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; ; ; ; 5.089 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.005 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; ; ; ; 7.265 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; ; ; ; 4.740 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.055 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; ; ; ; 7.250 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; ; ; ; 4.805 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.215 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; ; ; ; 7.251 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; ; ; ; 4.964 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.246 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; ; ; ; 7.253 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; ; ; ; 4.993 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.358 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; ; ; ; 7.254 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; ; ; ; 5.104 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.397 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; ; ; ; 7.105 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; ; ; ; 5.292 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.525 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; ; ; ; 7.251 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; ; ; ; 5.274 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.641 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; ; ; ; 7.253 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; ; ; ; 5.388 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.733 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; ; ; ; 7.267 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; ; ; ; 5.466 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.873 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; ; ; ; 7.126 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; ; ; ; 5.747 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + ++-------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Fmax Summary ; ++------------+-----------------+-----------------------------------------------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+-----------------------------------------------------+------+ +; 193.87 MHz ; 193.87 MHz ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; +; 231.32 MHz ; 231.32 MHz ; CLOCK_50 ; ; ++------------+-----------------+-----------------------------------------------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup Summary ; ++-----------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+--------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.053 ; 0.000 ; +; CLOCK_50 ; 15.677 ; 0.000 ; ++-----------------------------------------------------+--------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.190 ; 0.000 ; +; CLOCK_50 ; 0.312 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Recovery Summary ; ++-----------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+--------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.843 ; -150.984 ; +; CLOCK_50 ; 15.539 ; 0.000 ; ++-----------------------------------------------------+--------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Removal Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; CLOCK_50 ; 1.477 ; 0.000 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.638 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.741 ; 0.000 ; +; CLOCK_50 ; 9.561 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; 0.053 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.908 ; 2.054 ; +; 0.053 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.908 ; 2.054 ; +; 0.053 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.908 ; 2.054 ; +; 0.080 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.893 ; 2.042 ; +; 0.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.879 ; 2.026 ; +; 0.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.879 ; 2.026 ; +; 0.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.879 ; 2.026 ; +; 0.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 2.004 ; +; 0.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 2.004 ; +; 0.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 2.004 ; +; 0.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 2.004 ; +; 0.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 1.960 ; +; 0.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 1.960 ; +; 0.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 1.960 ; +; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 1.935 ; +; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 1.935 ; +; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 1.935 ; +; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 1.935 ; +; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 1.935 ; +; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 1.935 ; +; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 1.935 ; +; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 1.935 ; +; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 1.935 ; +; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 1.935 ; +; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 1.935 ; +; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 1.935 ; +; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 1.935 ; +; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 1.935 ; +; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.887 ; 1.935 ; +; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.895 ; 1.904 ; +; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.895 ; 1.904 ; +; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.895 ; 1.904 ; +; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.895 ; 1.904 ; +; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.895 ; 1.904 ; +; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.895 ; 1.904 ; +; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.895 ; 1.904 ; +; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.895 ; 1.904 ; +; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.895 ; 1.904 ; +; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.895 ; 1.904 ; +; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.895 ; 1.904 ; +; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.895 ; 1.904 ; +; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.895 ; 1.904 ; +; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.895 ; 1.904 ; +; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.895 ; 1.904 ; +; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.890 ; 1.906 ; +; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.890 ; 1.906 ; +; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.890 ; 1.906 ; +; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.890 ; 1.906 ; +; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.890 ; 1.906 ; +; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.890 ; 1.906 ; +; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.890 ; 1.906 ; +; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.890 ; 1.906 ; +; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.890 ; 1.906 ; +; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.890 ; 1.906 ; +; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.890 ; 1.906 ; +; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.890 ; 1.906 ; +; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.890 ; 1.906 ; +; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.890 ; 1.906 ; +; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.890 ; 1.906 ; +; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.889 ; 1.778 ; +; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.889 ; 1.778 ; +; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.889 ; 1.778 ; +; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.889 ; 1.778 ; +; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.889 ; 1.778 ; +; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.889 ; 1.778 ; +; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.889 ; 1.778 ; +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.914 ; 1.743 ; +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.914 ; 1.743 ; +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.914 ; 1.743 ; +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.914 ; 1.743 ; +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.914 ; 1.743 ; +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.914 ; 1.743 ; +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.914 ; 1.743 ; +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.914 ; 1.743 ; +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.914 ; 1.743 ; +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.914 ; 1.743 ; +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.914 ; 1.743 ; +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.914 ; 1.743 ; +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.914 ; 1.743 ; +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.914 ; 1.743 ; +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.914 ; 1.743 ; +; 2.842 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.076 ; 5.097 ; +; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.083 ; 5.055 ; +; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.083 ; 5.055 ; +; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.083 ; 5.055 ; +; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.083 ; 5.055 ; +; 2.898 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.083 ; 5.034 ; +; 2.898 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.083 ; 5.034 ; +; 2.898 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.083 ; 5.034 ; +; 2.914 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.076 ; 5.025 ; +; 2.919 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.076 ; 5.020 ; +; 2.931 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.256 ; 5.340 ; +; 2.949 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.083 ; 4.983 ; +; 2.949 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.083 ; 4.983 ; +; 2.949 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.083 ; 4.983 ; +; 2.949 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.083 ; 4.983 ; +; 2.954 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.083 ; 4.978 ; +; 2.954 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.083 ; 4.978 ; +; 2.954 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.083 ; 4.978 ; +; 2.954 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.083 ; 4.978 ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'CLOCK_50' ; ++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 15.677 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.285 ; +; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.169 ; +; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.169 ; +; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.169 ; +; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.169 ; +; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.169 ; +; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.169 ; +; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.169 ; +; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.169 ; +; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.169 ; +; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.169 ; +; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.169 ; +; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.169 ; +; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.169 ; +; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.160 ; +; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.160 ; +; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.160 ; +; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.160 ; +; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.160 ; +; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.160 ; +; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.160 ; +; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.160 ; +; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.160 ; +; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.160 ; +; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.160 ; +; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.160 ; +; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.160 ; +; 15.875 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.087 ; +; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.069 ; +; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.069 ; +; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.069 ; +; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.069 ; +; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.069 ; +; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.069 ; +; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.069 ; +; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.069 ; +; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.069 ; +; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.069 ; +; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.069 ; +; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.069 ; +; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.069 ; +; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.069 ; +; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.069 ; +; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.080 ; +; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.080 ; +; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.080 ; +; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.080 ; +; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.080 ; +; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.080 ; +; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.080 ; +; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.080 ; +; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.080 ; +; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.080 ; +; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.080 ; +; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.080 ; +; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.080 ; +; 15.910 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.065 ; +; 15.919 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 4.056 ; +; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 4.048 ; +; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 4.048 ; +; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 4.048 ; +; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 4.048 ; +; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 4.048 ; +; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 4.048 ; +; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 4.048 ; +; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 4.048 ; +; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 4.048 ; +; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 4.048 ; +; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 4.048 ; +; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 4.048 ; +; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 4.048 ; +; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 4.048 ; +; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 4.048 ; +; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 4.048 ; +; 15.951 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.011 ; +; 15.952 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.053 ; 4.010 ; +; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 4.007 ; +; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 4.007 ; +; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 4.007 ; +; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 4.007 ; +; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 4.007 ; +; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 4.007 ; +; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 4.007 ; +; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 4.007 ; +; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 4.007 ; +; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 4.007 ; +; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 4.007 ; +; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 4.007 ; +; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 4.007 ; +; 15.999 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 3.976 ; +; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 3.953 ; +; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 3.953 ; +; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 3.953 ; +; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 3.953 ; +; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 3.953 ; +; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 3.953 ; +; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 3.953 ; +; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 3.953 ; +; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 3.953 ; +; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 3.953 ; ++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; 0.190 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.383 ; 0.717 ; +; 0.205 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.383 ; 0.732 ; +; 0.295 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.383 ; 0.822 ; +; 0.296 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.383 ; 0.823 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.301 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 0.530 ; +; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.519 ; +; 0.321 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.519 ; +; 0.321 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.519 ; +; 0.324 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.535 ; +; 0.325 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.537 ; +; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.538 ; +; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.538 ; +; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.538 ; +; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.387 ; 0.857 ; +; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.387 ; 0.857 ; +; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.538 ; +; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.537 ; +; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.538 ; +; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.539 ; +; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.538 ; +; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.539 ; +; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.538 ; +; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.539 ; +; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.539 ; +; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.540 ; +; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.540 ; +; 0.331 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.841 ; +; 0.331 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.529 ; +; 0.332 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.543 ; +; 0.336 ; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|WRITEA ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.535 ; +; 0.337 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.536 ; +; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.340 ; 0.847 ; +; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 0.548 ; +; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.537 ; +; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[18] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.537 ; +; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.537 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.538 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.538 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[19] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.537 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.538 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.538 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.538 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'CLOCK_50' ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.511 ; +; 0.320 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.519 ; +; 0.333 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.511 ; +; 0.341 ; DE0_D5M:inst|rClk[0] ; DE0_D5M:inst|rClk[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.519 ; +; 0.346 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.545 ; +; 0.347 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.546 ; +; 0.347 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.546 ; +; 0.466 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.665 ; +; 0.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.671 ; +; 0.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.694 ; +; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.699 ; +; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.699 ; +; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.698 ; +; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.698 ; +; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.698 ; +; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.700 ; +; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.700 ; +; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.699 ; +; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.701 ; +; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.701 ; +; 0.502 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.700 ; +; 0.502 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.700 ; +; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.702 ; +; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.702 ; +; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.702 ; +; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.701 ; +; 0.503 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.701 ; +; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.703 ; +; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.702 ; +; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.702 ; +; 0.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.703 ; +; 0.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.703 ; +; 0.505 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.703 ; +; 0.506 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.705 ; +; 0.506 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.704 ; +; 0.511 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.710 ; +; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.710 ; +; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.710 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.710 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.710 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.710 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.712 ; +; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.712 ; +; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.711 ; +; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.711 ; +; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.711 ; +; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.711 ; +; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.712 ; +; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.711 ; +; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.711 ; +; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.711 ; +; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.712 ; +; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.712 ; +; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.712 ; +; 0.514 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.712 ; +; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.712 ; +; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.713 ; +; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.713 ; +; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.713 ; +; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.713 ; +; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.714 ; +; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.713 ; +; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.713 ; +; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.713 ; +; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.714 ; +; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.714 ; +; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.714 ; +; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.714 ; +; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.714 ; +; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.716 ; +; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.715 ; +; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.715 ; +; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.715 ; +; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.716 ; +; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.715 ; +; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.716 ; +; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.716 ; +; 0.518 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.716 ; +; 0.518 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.716 ; +; 0.521 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.719 ; +; 0.525 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.724 ; +; 0.525 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.723 ; +; 0.526 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.725 ; +; 0.540 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.739 ; +; 0.638 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.837 ; +; 0.639 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.838 ; +; 0.640 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.839 ; +; 0.741 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.939 ; +; 0.744 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.943 ; +; 0.744 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.942 ; +; 0.744 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.942 ; +; 0.745 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.944 ; +; 0.745 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.944 ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.817 ; +; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.817 ; +; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.817 ; +; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.817 ; +; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.817 ; +; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.817 ; +; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.817 ; +; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.817 ; +; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.817 ; +; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.817 ; +; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.817 ; +; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.817 ; +; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.817 ; +; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.817 ; +; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.817 ; +; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.817 ; +; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.820 ; +; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.820 ; +; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.820 ; +; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.820 ; +; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.820 ; +; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.820 ; +; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.820 ; +; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.820 ; +; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.820 ; +; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.820 ; +; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.820 ; +; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.820 ; +; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.820 ; +; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.820 ; +; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.820 ; +; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.820 ; +; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.982 ; 2.857 ; +; -0.796 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.976 ; 2.860 ; +; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.497 ; +; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.497 ; +; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.497 ; +; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.497 ; +; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.497 ; +; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.497 ; +; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.497 ; +; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.497 ; +; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.497 ; +; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.497 ; +; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.497 ; +; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.497 ; +; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.497 ; +; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.497 ; +; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.497 ; +; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.497 ; +; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.497 ; +; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.202 ; 2.500 ; +; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.202 ; 2.500 ; +; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.202 ; 2.500 ; +; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.202 ; 2.500 ; +; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.202 ; 2.500 ; +; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.202 ; 2.500 ; +; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.202 ; 2.500 ; +; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.202 ; 2.500 ; +; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.202 ; 2.500 ; +; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.202 ; 2.500 ; +; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.202 ; 2.500 ; +; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.204 ; 2.497 ; +; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.203 ; 2.498 ; +; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.203 ; 2.498 ; +; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.203 ; 2.498 ; +; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.203 ; 2.498 ; +; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.204 ; 2.497 ; +; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.203 ; 2.498 ; +; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.204 ; 2.497 ; +; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.204 ; 2.497 ; +; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.204 ; 2.497 ; +; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.204 ; 2.497 ; +; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.204 ; 2.497 ; +; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.204 ; 2.497 ; +; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.204 ; 2.497 ; +; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.204 ; 2.497 ; +; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.204 ; 2.497 ; +; -0.685 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.203 ; 2.497 ; +; -0.685 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.203 ; 2.497 ; +; -0.685 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.203 ; 2.497 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.203 ; 2.496 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.203 ; 2.496 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.203 ; 2.496 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.203 ; 2.496 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.203 ; 2.496 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.203 ; 2.496 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.203 ; 2.496 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 2.485 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 2.485 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 2.485 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 2.485 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 2.485 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.488 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 2.485 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.488 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.488 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.488 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.488 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 2.485 ; ++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Recovery: 'CLOCK_50' ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 15.539 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.082 ; 4.558 ; +; 15.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.082 ; 4.549 ; +; 15.628 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.082 ; 4.469 ; +; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.315 ; +; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.315 ; +; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.315 ; +; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.315 ; +; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.315 ; +; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.315 ; +; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.315 ; +; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.315 ; +; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.315 ; +; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.315 ; +; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.315 ; +; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.315 ; +; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.315 ; +; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.315 ; +; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.315 ; +; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.315 ; +; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.306 ; +; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.306 ; +; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.306 ; +; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.306 ; +; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.306 ; +; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.306 ; +; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.306 ; +; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.306 ; +; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.306 ; +; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.306 ; +; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.306 ; +; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.306 ; +; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.306 ; +; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.306 ; +; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.306 ; +; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.306 ; +; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.070 ; 4.396 ; +; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.226 ; +; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.226 ; +; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.226 ; +; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.226 ; +; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.226 ; +; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.226 ; +; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.226 ; +; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.226 ; +; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.226 ; +; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.226 ; +; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.226 ; +; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.226 ; +; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.226 ; +; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.226 ; +; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.226 ; +; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.226 ; +; 15.755 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.082 ; 4.342 ; +; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.153 ; +; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.153 ; +; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.153 ; +; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.153 ; +; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.153 ; +; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.153 ; +; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.153 ; +; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.153 ; +; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.153 ; +; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.153 ; +; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.153 ; +; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.153 ; +; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.153 ; +; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.153 ; +; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.153 ; +; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.153 ; +; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.070 ; 4.270 ; +; 15.818 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.070 ; 4.267 ; +; 15.824 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.070 ; 4.261 ; +; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.099 ; +; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.099 ; +; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.099 ; +; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.099 ; +; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.099 ; +; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.099 ; +; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.099 ; +; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.099 ; +; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.099 ; +; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.099 ; +; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.099 ; +; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.099 ; +; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.099 ; +; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.099 ; +; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.099 ; +; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.099 ; +; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.070 ; 4.190 ; +; 15.902 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.070 ; 4.183 ; +; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.027 ; +; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.027 ; +; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.027 ; +; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.027 ; +; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.027 ; +; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.027 ; +; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.027 ; +; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.027 ; +; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.027 ; +; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.027 ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Removal: 'CLOCK_50' ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.666 ; +; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.666 ; +; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.666 ; +; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.666 ; +; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.666 ; +; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.666 ; +; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.666 ; +; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.666 ; +; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.666 ; +; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.666 ; +; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.666 ; +; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.666 ; +; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.666 ; +; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.666 ; +; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.666 ; +; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.666 ; +; 1.534 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.222 ; 1.900 ; +; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.765 ; +; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.765 ; +; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.765 ; +; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.765 ; +; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.765 ; +; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.765 ; +; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.765 ; +; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.765 ; +; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.765 ; +; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.765 ; +; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.765 ; +; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.765 ; +; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.765 ; +; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.765 ; +; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.765 ; +; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.045 ; 1.765 ; +; 1.632 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.222 ; 1.998 ; +; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.407 ; +; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.407 ; +; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.407 ; +; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.407 ; +; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.407 ; +; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.407 ; +; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.407 ; +; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.407 ; +; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.407 ; +; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.407 ; +; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.407 ; +; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.407 ; +; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.407 ; +; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.407 ; +; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.407 ; +; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.407 ; +; 2.262 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.235 ; 2.641 ; +; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.050 ; 2.707 ; +; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.050 ; 2.707 ; +; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.050 ; 2.707 ; +; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.050 ; 2.707 ; +; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.050 ; 2.707 ; +; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.050 ; 2.707 ; +; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.050 ; 2.707 ; +; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.050 ; 2.707 ; +; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.050 ; 2.707 ; +; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.050 ; 2.707 ; +; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.050 ; 2.707 ; +; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.050 ; 2.707 ; +; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.050 ; 2.707 ; +; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.721 ; +; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.721 ; +; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.721 ; +; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.721 ; +; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.723 ; +; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.723 ; +; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.723 ; +; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.723 ; +; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.723 ; +; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.723 ; +; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.723 ; +; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.723 ; +; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.723 ; +; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.723 ; +; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.723 ; +; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.723 ; +; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.723 ; +; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.723 ; +; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.721 ; +; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.721 ; +; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.721 ; +; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.721 ; +; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.721 ; +; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.721 ; +; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.721 ; +; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.721 ; +; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.721 ; +; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.721 ; +; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.721 ; +; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.721 ; +; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.733 ; +; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.733 ; +; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.733 ; +; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.733 ; +; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.733 ; +; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.058 ; 2.733 ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.438 ; 2.344 ; +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.438 ; 2.344 ; +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.438 ; 2.344 ; +; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.445 ; 2.338 ; +; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.445 ; 2.338 ; +; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.445 ; 2.338 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.448 ; 2.336 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.448 ; 2.336 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.448 ; 2.336 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.448 ; 2.336 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.448 ; 2.336 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.448 ; 2.336 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.448 ; 2.336 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.448 ; 2.336 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.448 ; 2.336 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.448 ; 2.336 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.443 ; 2.342 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.442 ; 2.343 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.442 ; 2.343 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.442 ; 2.343 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.444 ; 2.341 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.444 ; 2.341 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.444 ; 2.341 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.444 ; 2.341 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.444 ; 2.341 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.444 ; 2.341 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.444 ; 2.341 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.444 ; 2.341 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.444 ; 2.341 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.444 ; 2.341 ; +; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.343 ; +; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.343 ; +; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.343 ; +; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.343 ; +; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.343 ; +; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.343 ; +; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.343 ; +; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.343 ; +; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.343 ; +; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.343 ; +; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.444 ; 2.345 ; +; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.444 ; 2.345 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.445 ; 2.345 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.445 ; 2.345 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.445 ; 2.345 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.445 ; 2.345 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.445 ; 2.345 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.445 ; 2.345 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.445 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.338 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.338 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.338 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.338 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.338 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.338 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.338 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.338 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.455 ; 2.336 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.338 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.338 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.455 ; 2.336 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.345 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.455 ; 2.336 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.455 ; 2.336 ; +; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.455 ; 2.336 ; +; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.450 ; 2.343 ; +; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.451 ; 2.342 ; +; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.451 ; 2.342 ; +; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.451 ; 2.342 ; +; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.451 ; 2.342 ; +; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.451 ; 2.342 ; +; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.451 ; 2.342 ; +; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.451 ; 2.342 ; +; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.451 ; 2.342 ; +; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.451 ; 2.342 ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; 3.742 ; 3.972 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0 ; +; 3.742 ; 3.972 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg ; +; 3.742 ; 3.972 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0 ; +; 3.742 ; 3.972 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg ; +; 3.742 ; 3.958 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; +; 3.742 ; 3.958 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; 3.742 ; 3.958 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; 3.742 ; 3.958 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; +; 3.742 ; 3.958 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9] ; +; 3.744 ; 3.960 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_RD ; +; 3.744 ; 3.960 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_WR ; +; 3.744 ; 3.974 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0 ; +; 3.744 ; 3.974 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0 ; +; 3.744 ; 3.960 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[16] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; 3.746 ; 3.962 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; +; 3.746 ; 3.962 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; +; 3.746 ; 3.962 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; +; 3.746 ; 3.962 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; +; 3.746 ; 3.962 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; +; 3.746 ; 3.962 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; +; 3.746 ; 3.962 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; +; 3.746 ; 3.962 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; +; 3.746 ; 3.962 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0] ; +; 3.746 ; 3.962 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1] ; +; 3.746 ; 3.962 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; 3.748 ; 3.964 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[0] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[2] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[5] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; ++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ; ++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+ +; 9.561 ; 9.745 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|rClk[0] ; +; 9.585 ; 9.769 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; +; 9.585 ; 9.769 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_1 ; +; 9.585 ; 9.769 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; +; 9.586 ; 9.770 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; +; 9.713 ; 9.713 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; 9.713 ; 9.713 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; 9.713 ; 9.713 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|observablevcoout ; +; 9.721 ; 9.721 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst|rClk[0]|clk ; ++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; 3.589 ; 4.163 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; 3.589 ; 4.163 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; 2.854 ; 3.325 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; 3.848 ; 4.345 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.848 ; 4.345 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.647 ; 4.124 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.508 ; 3.941 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.418 ; 3.842 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.402 ; 3.831 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.177 ; 3.607 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.182 ; 3.617 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.163 ; 3.604 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; -1.293 ; -1.708 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; -1.317 ; -1.789 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; -1.293 ; -1.708 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; -2.565 ; -2.993 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; -3.235 ; -3.721 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; -3.030 ; -3.492 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; -2.908 ; -3.334 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; -2.811 ; -3.222 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; -2.795 ; -3.211 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; -2.579 ; -2.996 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; -2.584 ; -3.006 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; -2.565 ; -2.993 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 6.617 ; 6.571 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 6.617 ; 6.571 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 6.491 ; 6.343 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 4.764 ; 4.656 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 4.764 ; 4.656 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 5.013 ; 5.130 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 3.730 ; 3.594 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 3.702 ; 3.557 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 3.727 ; 3.594 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 3.587 ; 3.487 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 3.730 ; 3.586 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 3.574 ; 3.450 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 3.533 ; 3.425 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 3.580 ; 3.438 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 3.373 ; 3.272 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 3.536 ; 3.389 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 3.591 ; 3.458 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 3.526 ; 3.393 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 3.389 ; 3.273 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 3.546 ; 3.427 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 3.618 ; 3.475 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 3.558 ; 3.446 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 3.685 ; 3.523 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 7.526 ; 7.148 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 5.603 ; 5.452 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 5.676 ; 5.541 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 5.607 ; 5.466 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 7.526 ; 7.148 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 5.522 ; 5.349 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 5.454 ; 5.296 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 5.944 ; 5.827 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 5.487 ; 5.303 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 5.446 ; 5.300 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 5.017 ; 4.898 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 5.452 ; 5.289 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 5.233 ; 5.055 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 5.444 ; 5.305 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 5.296 ; 5.162 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 5.806 ; 5.636 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 5.414 ; 5.226 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 3.587 ; 3.493 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 3.721 ; 3.601 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 3.442 ; 3.301 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 5.583 ; 5.252 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -0.448 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -0.595 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 6.336 ; 6.187 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 6.455 ; 6.406 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 6.336 ; 6.187 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 4.676 ; 4.567 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 4.676 ; 4.567 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 4.910 ; 5.026 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 2.989 ; 2.887 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 3.304 ; 3.159 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 3.329 ; 3.197 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 3.194 ; 3.093 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 3.330 ; 3.187 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 3.182 ; 3.058 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 3.141 ; 3.032 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 3.187 ; 3.046 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 2.989 ; 2.887 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 3.144 ; 2.999 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 3.198 ; 3.065 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 3.135 ; 3.003 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 3.004 ; 2.888 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 3.155 ; 3.036 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 3.225 ; 3.082 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 3.166 ; 3.053 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 3.286 ; 3.126 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 3.770 ; 3.622 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 4.360 ; 4.187 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 4.249 ; 4.128 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 4.187 ; 4.056 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 6.096 ; 5.728 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 4.828 ; 4.689 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 4.355 ; 4.245 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 4.512 ; 4.404 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 4.402 ; 4.261 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 4.140 ; 3.977 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 4.300 ; 4.168 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 4.675 ; 4.504 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 4.112 ; 3.961 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.770 ; 3.622 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 4.276 ; 4.132 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 4.316 ; 4.129 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 4.112 ; 3.947 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 3.193 ; 3.098 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 3.321 ; 3.201 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 3.055 ; 2.915 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 5.190 ; 4.858 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -0.777 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -0.922 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Output Enable Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 3.119 ; 3.106 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.121 ; 3.108 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.591 ; 3.578 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.601 ; 3.588 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.404 ; 3.391 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.777 ; 3.764 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.591 ; 3.578 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.797 ; 3.784 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.766 ; 3.753 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.129 ; 3.116 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.129 ; 3.116 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.141 ; 3.128 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.119 ; 3.106 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.131 ; 3.118 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.141 ; 3.128 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.121 ; 3.108 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.777 ; 3.764 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.251 ; 2.251 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.252 ; 2.252 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.704 ; 2.704 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.714 ; 2.714 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.525 ; 2.525 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.882 ; 2.882 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.704 ; 2.704 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.902 ; 2.902 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.872 ; 2.872 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.261 ; 2.261 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.261 ; 2.261 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.272 ; 2.272 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.251 ; 2.251 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.262 ; 2.262 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.272 ; 2.272 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.252 ; 2.252 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.882 ; 2.882 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Output Disable Times ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 3.126 ; 3.126 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.126 ; 3.126 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.591 ; 3.591 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.601 ; 3.601 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.413 ; 3.413 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.769 ; 3.769 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.591 ; 3.591 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.789 ; 3.789 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.763 ; 3.763 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.140 ; 3.140 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.140 ; 3.140 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.146 ; 3.146 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.130 ; 3.130 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.136 ; 3.136 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.146 ; 3.146 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.126 ; 3.126 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.769 ; 3.769 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.257 ; 2.445 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.257 ; 2.445 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.704 ; 2.892 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.714 ; 2.902 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.533 ; 2.721 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.875 ; 3.063 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.704 ; 2.892 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.895 ; 3.083 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.869 ; 3.057 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.272 ; 2.460 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.272 ; 2.460 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.277 ; 2.465 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.262 ; 2.450 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.267 ; 2.455 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.277 ; 2.465 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.257 ; 2.445 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.875 ; 3.063 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ + + +---------------- +; MTBF Summary ; +---------------- +Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 40 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 11.581 ns + +Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 + + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Worst-Case MTBF (Years) ; Typical MTBF (Years) ; Included in Design MTBF ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.581 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; ; ; ; 7.335 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; ; ; ; 4.246 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.772 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; ; ; ; 7.080 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; ; ; ; 4.692 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.831 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; ; ; ; 7.338 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; ; ; ; 4.493 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.874 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; ; ; ; 7.198 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; ; ; ; 4.676 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.896 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; ; ; ; 7.022 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; ; ; ; 4.874 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.906 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; ; ; ; 7.198 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; ; ; ; 4.708 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.975 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; ; ; ; 7.335 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; ; ; ; 4.640 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.978 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; ; ; ; 7.021 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; ; ; ; 4.957 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.982 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; ; ; ; 7.339 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; ; ; ; 4.643 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.986 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; ; ; ; 7.199 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; ; ; ; 4.787 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.061 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; ; ; ; 7.198 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; ; ; ; 4.863 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.083 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; ; ; ; 7.196 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; ; ; ; 4.887 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.090 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; ; ; ; 7.198 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; ; ; ; 4.892 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.119 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; ; ; ; 7.338 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; ; ; ; 4.781 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.133 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; ; ; ; 7.198 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; ; ; ; 4.935 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.134 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; ; ; ; 7.018 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; ; ; ; 5.116 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.135 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; ; ; ; 7.019 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; ; ; ; 5.116 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.148 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; ; ; ; 7.339 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; ; ; ; 4.809 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.187 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; ; ; ; 7.201 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; ; ; ; 4.986 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.217 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; ; ; ; 7.339 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; ; ; ; 4.878 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.247 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; ; ; ; 7.197 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; ; ; ; 5.050 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.261 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; ; ; ; 6.920 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; ; ; ; 5.341 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.263 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; ; ; ; 7.022 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; ; ; ; 5.241 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.279 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ; ; ; 7.100 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; ; ; ; 5.179 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.286 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; ; ; ; 7.200 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; ; ; ; 5.086 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.291 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ; ; ; 7.097 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; ; ; ; 5.194 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.324 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; ; ; ; 6.808 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; ; ; ; 5.516 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.345 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; ; ; ; 7.337 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; ; ; ; 5.008 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.347 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; ; ; ; 7.337 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; ; ; ; 5.010 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.358 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; ; ; ; 7.019 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; ; ; ; 5.339 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.445 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; ; ; ; 7.350 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; ; ; ; 5.095 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.483 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; ; ; ; 7.337 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; ; ; ; 5.146 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.587 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; ; ; ; 7.337 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; ; ; ; 5.250 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.646 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; ; ; ; 7.339 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; ; ; ; 5.307 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.740 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; ; ; ; 7.340 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; ; ; ; 5.400 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.768 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; ; ; ; 7.198 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; ; ; ; 5.570 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.901 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; ; ; ; 7.337 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; ; ; ; 5.564 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.982 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; ; ; ; 7.339 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; ; ; ; 5.643 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.070 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; ; ; ; 7.352 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; ; ; ; 5.718 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.198 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; ; ; ; 7.222 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; ; ; ; 5.976 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + ++------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup Summary ; ++-----------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+--------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 1.424 ; 0.000 ; +; CLOCK_50 ; 17.244 ; 0.000 ; ++-----------------------------------------------------+--------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.116 ; 0.000 ; +; CLOCK_50 ; 0.187 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Recovery Summary ; ++-----------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+--------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.773 ; 0.000 ; +; CLOCK_50 ; 17.090 ; 0.000 ; ++-----------------------------------------------------+--------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Removal Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; CLOCK_50 ; 0.904 ; 0.000 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 2.414 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.748 ; 0.000 ; +; CLOCK_50 ; 9.265 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; 1.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.313 ; 1.270 ; +; 1.445 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.319 ; 1.243 ; +; 1.445 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.319 ; 1.243 ; +; 1.445 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.319 ; 1.243 ; +; 1.462 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.307 ; 1.238 ; +; 1.462 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.307 ; 1.238 ; +; 1.462 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.307 ; 1.238 ; +; 1.462 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.307 ; 1.238 ; +; 1.481 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.303 ; 1.223 ; +; 1.481 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.303 ; 1.223 ; +; 1.481 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.303 ; 1.223 ; +; 1.485 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.307 ; 1.215 ; +; 1.485 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.307 ; 1.215 ; +; 1.485 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.307 ; 1.215 ; +; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.183 ; +; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.183 ; +; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.183 ; +; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.183 ; +; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.183 ; +; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.183 ; +; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.183 ; +; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.183 ; +; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.183 ; +; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.183 ; +; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.183 ; +; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.183 ; +; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.183 ; +; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.183 ; +; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.183 ; +; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.186 ; +; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.186 ; +; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.186 ; +; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.186 ; +; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.186 ; +; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.186 ; +; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.186 ; +; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.186 ; +; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.186 ; +; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.186 ; +; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.186 ; +; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.186 ; +; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.186 ; +; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.186 ; +; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.186 ; +; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.179 ; +; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.179 ; +; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.179 ; +; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.179 ; +; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.179 ; +; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.179 ; +; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.179 ; +; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.179 ; +; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.179 ; +; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.179 ; +; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.179 ; +; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.179 ; +; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.179 ; +; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.179 ; +; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.179 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.325 ; 1.069 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.325 ; 1.069 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.325 ; 1.069 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.325 ; 1.069 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.325 ; 1.069 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.325 ; 1.069 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.325 ; 1.069 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.325 ; 1.069 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.325 ; 1.069 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.325 ; 1.069 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.325 ; 1.069 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.325 ; 1.069 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.325 ; 1.069 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.325 ; 1.069 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.325 ; 1.069 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.084 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.084 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.084 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.084 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.084 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.084 ; +; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.310 ; 1.084 ; +; 4.705 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.044 ; 3.258 ; +; 4.712 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.150 ; 3.445 ; +; 4.733 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.048 ; 3.226 ; +; 4.733 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.048 ; 3.226 ; +; 4.733 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.048 ; 3.226 ; +; 4.733 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.048 ; 3.226 ; +; 4.739 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.146 ; 3.414 ; +; 4.739 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.146 ; 3.414 ; +; 4.739 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.146 ; 3.414 ; +; 4.739 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.146 ; 3.414 ; +; 4.748 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.146 ; 3.405 ; +; 4.748 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.146 ; 3.405 ; +; 4.748 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.146 ; 3.405 ; +; 4.750 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.044 ; 3.213 ; +; 4.756 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.048 ; 3.203 ; +; 4.756 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.048 ; 3.203 ; +; 4.756 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.048 ; 3.203 ; +; 4.757 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.044 ; 3.206 ; +; 4.764 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.044 ; 3.199 ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'CLOCK_50' ; ++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 17.244 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.034 ; 2.729 ; +; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.684 ; +; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.684 ; +; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.684 ; +; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.684 ; +; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.684 ; +; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.684 ; +; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.684 ; +; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.684 ; +; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.684 ; +; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.684 ; +; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.684 ; +; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.684 ; +; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.684 ; +; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.681 ; +; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.681 ; +; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.681 ; +; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.681 ; +; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.681 ; +; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.681 ; +; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.681 ; +; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.681 ; +; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.681 ; +; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.681 ; +; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.681 ; +; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.681 ; +; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.681 ; +; 17.340 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.640 ; +; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.631 ; +; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.631 ; +; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.631 ; +; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.631 ; +; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.631 ; +; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.631 ; +; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.631 ; +; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.631 ; +; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.631 ; +; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.631 ; +; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.631 ; +; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.631 ; +; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.631 ; +; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.631 ; +; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.631 ; +; 17.343 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.637 ; +; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.031 ; 2.618 ; +; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.031 ; 2.618 ; +; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.031 ; 2.618 ; +; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.031 ; 2.618 ; +; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.031 ; 2.618 ; +; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.031 ; 2.618 ; +; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.031 ; 2.618 ; +; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.031 ; 2.618 ; +; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.031 ; 2.618 ; +; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.031 ; 2.618 ; +; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.031 ; 2.618 ; +; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.031 ; 2.618 ; +; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.031 ; 2.618 ; +; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.031 ; 2.618 ; +; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.031 ; 2.618 ; +; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.031 ; 2.618 ; +; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.619 ; +; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.619 ; +; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.619 ; +; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.619 ; +; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.619 ; +; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.619 ; +; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.619 ; +; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.619 ; +; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.619 ; +; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.619 ; +; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.619 ; +; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.619 ; +; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.619 ; +; 17.382 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.034 ; 2.591 ; +; 17.405 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.575 ; +; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.562 ; +; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.562 ; +; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.562 ; +; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.562 ; +; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.562 ; +; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.562 ; +; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.562 ; +; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.562 ; +; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.562 ; +; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.562 ; +; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.562 ; +; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.562 ; +; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.562 ; +; 17.432 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.034 ; 2.541 ; +; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.546 ; +; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.546 ; +; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.546 ; +; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.546 ; +; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.546 ; +; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.546 ; +; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.546 ; +; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.546 ; +; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.546 ; +; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.546 ; +; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 2.546 ; ++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; 0.116 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.233 ; 0.433 ; +; 0.123 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.233 ; 0.440 ; +; 0.162 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.487 ; +; 0.164 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.233 ; 0.481 ; +; 0.165 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.233 ; 0.482 ; +; 0.172 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.496 ; +; 0.173 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.497 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.183 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.233 ; 0.500 ; +; 0.183 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.233 ; 0.500 ; +; 0.186 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.313 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.314 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.314 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.314 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.314 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.314 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.314 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.314 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.314 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.314 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.313 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.313 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.314 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.315 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.189 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.316 ; +; 0.189 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.316 ; +; 0.190 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.233 ; 0.507 ; +; 0.192 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.319 ; +; 0.193 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.313 ; +; 0.193 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[19] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.313 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.313 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[18] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.313 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.313 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[21] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.313 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.315 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'CLOCK_50' ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.187 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.307 ; +; 0.195 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.314 ; +; 0.199 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.319 ; +; 0.201 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.022 ; 0.307 ; +; 0.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.325 ; +; 0.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.325 ; +; 0.208 ; DE0_D5M:inst|rClk[0] ; DE0_D5M:inst|rClk[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.022 ; 0.314 ; +; 0.268 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.388 ; +; 0.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.391 ; +; 0.294 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.413 ; +; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.417 ; +; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.417 ; +; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.417 ; +; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.417 ; +; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.418 ; +; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.418 ; +; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.418 ; +; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.418 ; +; 0.298 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.418 ; +; 0.298 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.418 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.420 ; +; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.420 ; +; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.420 ; +; 0.300 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.420 ; +; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.424 ; +; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.424 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.428 ; +; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.427 ; +; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.427 ; +; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.427 ; +; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.427 ; +; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.428 ; +; 0.309 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.428 ; +; 0.310 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.430 ; +; 0.311 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.431 ; +; 0.313 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.433 ; +; 0.314 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.434 ; +; 0.325 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.445 ; +; 0.369 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.489 ; +; 0.370 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.490 ; +; 0.377 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.497 ; +; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.555 ; +; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.555 ; +; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.555 ; +; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.555 ; +; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.555 ; +; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.555 ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.842 ; +; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.842 ; +; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.842 ; +; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.842 ; +; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.842 ; +; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.842 ; +; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.842 ; +; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.842 ; +; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.842 ; +; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.842 ; +; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.842 ; +; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.842 ; +; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.842 ; +; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.842 ; +; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.842 ; +; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.842 ; +; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.846 ; +; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.846 ; +; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.846 ; +; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.846 ; +; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.846 ; +; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.846 ; +; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.846 ; +; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.846 ; +; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.846 ; +; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.846 ; +; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.846 ; +; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.846 ; +; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.846 ; +; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.846 ; +; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.846 ; +; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.846 ; +; 0.809 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.860 ; +; 0.811 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.864 ; +; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.652 ; +; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.652 ; +; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.652 ; +; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.652 ; +; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.652 ; +; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.652 ; +; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.652 ; +; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.651 ; +; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.651 ; +; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.651 ; +; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.651 ; +; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.651 ; +; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.651 ; +; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.651 ; +; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.651 ; +; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.651 ; +; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.651 ; +; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.655 ; +; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.655 ; +; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.655 ; +; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.655 ; +; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.655 ; +; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.655 ; +; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.655 ; +; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.655 ; +; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.655 ; +; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.655 ; +; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.498 ; 1.654 ; +; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.498 ; 1.654 ; +; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.498 ; 1.654 ; +; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.498 ; 1.654 ; +; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.498 ; 1.654 ; +; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.655 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.498 ; 1.653 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.498 ; 1.653 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.498 ; 1.653 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.498 ; 1.653 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.498 ; 1.653 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.498 ; 1.653 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.498 ; 1.653 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.498 ; 1.653 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.498 ; 1.653 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.498 ; 1.653 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.498 ; 1.653 ; +; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.496 ; 1.653 ; +; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.496 ; 1.653 ; +; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.496 ; 1.653 ; +; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.496 ; 1.653 ; +; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.496 ; 1.653 ; +; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.496 ; 1.653 ; +; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.496 ; 1.653 ; +; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.496 ; 1.653 ; +; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.496 ; 1.653 ; +; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.496 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.504 ; 1.643 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.504 ; 1.643 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.646 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.646 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.504 ; 1.643 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.646 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.646 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.646 ; +; 0.861 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.643 ; +; 0.861 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.643 ; +; 0.861 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.643 ; +; 0.861 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.643 ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Recovery: 'CLOCK_50' ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 17.090 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.061 ; 2.978 ; +; 17.093 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.061 ; 2.975 ; +; 17.155 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.061 ; 2.913 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.796 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.796 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.796 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.796 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.796 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.796 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.796 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.796 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.796 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.796 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.796 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.796 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.796 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.796 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.796 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.796 ; +; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.793 ; +; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.793 ; +; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.793 ; +; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.793 ; +; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.793 ; +; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.793 ; +; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.793 ; +; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.793 ; +; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.793 ; +; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.793 ; +; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.793 ; +; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.793 ; +; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.793 ; +; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.793 ; +; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.793 ; +; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.793 ; +; 17.204 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.053 ; 2.856 ; +; 17.228 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.061 ; 2.840 ; +; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.731 ; +; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.731 ; +; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.731 ; +; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.731 ; +; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.731 ; +; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.731 ; +; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.731 ; +; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.731 ; +; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.731 ; +; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.731 ; +; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.731 ; +; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.731 ; +; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.731 ; +; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.731 ; +; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.731 ; +; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.731 ; +; 17.285 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.053 ; 2.775 ; +; 17.288 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.053 ; 2.772 ; +; 17.288 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.053 ; 2.772 ; +; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.674 ; +; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.674 ; +; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.674 ; +; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.674 ; +; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.674 ; +; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.674 ; +; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.674 ; +; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.674 ; +; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.674 ; +; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.674 ; +; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.674 ; +; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.674 ; +; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.674 ; +; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.674 ; +; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.674 ; +; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.674 ; +; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.658 ; +; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.658 ; +; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.658 ; +; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.658 ; +; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.658 ; +; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.658 ; +; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.658 ; +; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.658 ; +; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.658 ; +; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.658 ; +; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.658 ; +; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.658 ; +; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.658 ; +; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.658 ; +; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.658 ; +; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.658 ; +; 17.348 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.053 ; 2.712 ; +; 17.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; 0.053 ; 2.710 ; +; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.593 ; +; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.593 ; +; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.593 ; +; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.593 ; +; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.593 ; +; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.593 ; +; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.593 ; +; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.593 ; +; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.593 ; +; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.040 ; 2.593 ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Removal: 'CLOCK_50' ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.019 ; +; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.019 ; +; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.019 ; +; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.019 ; +; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.019 ; +; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.019 ; +; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.019 ; +; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.019 ; +; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.019 ; +; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.019 ; +; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.019 ; +; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.019 ; +; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.019 ; +; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.019 ; +; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.019 ; +; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.019 ; +; 0.933 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.157 ; 1.174 ; +; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.101 ; +; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.101 ; +; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.101 ; +; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.101 ; +; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.101 ; +; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.101 ; +; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.101 ; +; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.101 ; +; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.101 ; +; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.101 ; +; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.101 ; +; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.101 ; +; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.101 ; +; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.101 ; +; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.101 ; +; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.031 ; 1.101 ; +; 1.015 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.157 ; 1.256 ; +; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.473 ; +; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.473 ; +; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.473 ; +; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.473 ; +; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.473 ; +; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.473 ; +; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.473 ; +; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.473 ; +; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.473 ; +; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.473 ; +; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.473 ; +; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.473 ; +; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.473 ; +; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.473 ; +; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.473 ; +; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.473 ; +; 1.379 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.165 ; 1.628 ; +; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.635 ; +; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.635 ; +; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.635 ; +; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.635 ; +; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.635 ; +; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.635 ; +; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.635 ; +; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.635 ; +; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.635 ; +; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.635 ; +; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.635 ; +; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.635 ; +; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.635 ; +; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.635 ; +; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.635 ; +; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.635 ; +; 1.541 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.165 ; 1.790 ; +; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.698 ; +; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.698 ; +; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.698 ; +; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.698 ; +; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.698 ; +; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.698 ; +; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.698 ; +; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.698 ; +; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.698 ; +; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.698 ; +; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.698 ; +; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.698 ; +; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.698 ; +; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.698 ; +; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.698 ; +; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 1.698 ; +; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.714 ; +; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.714 ; +; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.714 ; +; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.714 ; +; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.714 ; +; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.714 ; +; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.714 ; +; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.714 ; +; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.714 ; +; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.714 ; +; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.714 ; +; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.714 ; +; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.714 ; +; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.714 ; +; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.714 ; +; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.714 ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; 2.414 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.009 ; 1.489 ; +; 2.414 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.009 ; 1.489 ; +; 2.414 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.009 ; 1.489 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.487 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.487 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.487 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.487 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.487 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.487 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.487 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.487 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.487 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.487 ; +; 2.416 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.005 ; 1.495 ; +; 2.416 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.005 ; 1.495 ; +; 2.416 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.005 ; 1.495 ; +; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.006 ; 1.495 ; +; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.007 ; 1.496 ; +; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.007 ; 1.496 ; +; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.007 ; 1.496 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.487 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.487 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.487 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.487 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.487 ; +; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.492 ; +; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.492 ; +; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.492 ; +; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.492 ; +; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.492 ; +; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.492 ; +; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.492 ; +; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.492 ; +; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.492 ; +; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.492 ; +; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.011 ; 1.495 ; +; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.494 ; +; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.494 ; +; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.494 ; +; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.494 ; +; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.494 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.495 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.495 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.495 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.495 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.495 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.495 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.495 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.495 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.495 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.495 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.495 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.495 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.495 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.495 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.495 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.013 ; 1.495 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.011 ; 1.497 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.011 ; 1.497 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.011 ; 1.497 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.011 ; 1.497 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.011 ; 1.497 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.011 ; 1.497 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.011 ; 1.497 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.011 ; 1.497 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.011 ; 1.497 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; +; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.494 ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0 ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0 ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; +; 3.750 ; 3.980 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0 ; +; 3.751 ; 3.981 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0 ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; +; 3.782 ; 3.966 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0] ; +; 3.782 ; 3.966 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1] ; ++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ; ++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+ +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_1 ; +; 9.265 ; 9.449 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; +; 9.279 ; 9.463 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|rClk[0] ; +; 9.357 ; 9.541 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; +; 9.425 ; 9.425 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; 9.425 ; 9.425 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; 9.425 ; 9.425 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|observablevcoout ; +; 9.441 ; 9.441 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; CLOCK_50~input|o ; ++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; 2.203 ; 3.113 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; 2.203 ; 3.113 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; 1.819 ; 2.590 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; 2.569 ; 3.369 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.569 ; 3.369 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.420 ; 3.241 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.344 ; 3.086 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.289 ; 3.048 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.279 ; 3.037 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.147 ; 2.890 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.153 ; 2.902 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.137 ; 2.886 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; -0.819 ; -1.598 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; -0.859 ; -1.656 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; -0.819 ; -1.598 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; -1.744 ; -2.479 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; -2.164 ; -2.955 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; -2.015 ; -2.819 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; -1.949 ; -2.683 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; -1.891 ; -2.635 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; -1.881 ; -2.624 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; -1.754 ; -2.483 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; -1.760 ; -2.494 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; -1.744 ; -2.479 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 4.186 ; 4.306 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 4.186 ; 4.306 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 4.118 ; 4.091 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 2.959 ; 2.978 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 2.959 ; 2.978 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 3.218 ; 3.178 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 2.268 ; 2.285 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 2.233 ; 2.237 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 2.268 ; 2.285 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 2.192 ; 2.204 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 2.244 ; 2.273 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 2.168 ; 2.172 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 2.145 ; 2.152 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 2.161 ; 2.163 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 2.060 ; 2.058 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 2.125 ; 2.133 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 2.167 ; 2.176 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 2.142 ; 2.137 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 2.057 ; 2.060 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 2.156 ; 2.162 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 2.183 ; 2.200 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 2.140 ; 2.153 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 2.205 ; 2.203 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 5.019 ; 4.759 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.533 ; 3.460 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.588 ; 3.529 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.549 ; 3.512 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 5.019 ; 4.759 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.466 ; 3.449 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.426 ; 3.430 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.769 ; 3.755 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.438 ; 3.426 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.339 ; 3.455 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.129 ; 3.157 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.327 ; 3.428 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.279 ; 3.193 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.442 ; 3.391 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.224 ; 3.315 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.656 ; 3.619 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.402 ; 3.371 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 2.164 ; 2.170 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 2.250 ; 2.268 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 2.082 ; 2.069 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 3.681 ; 3.498 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -1.313 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -1.366 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 4.014 ; 3.986 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 4.082 ; 4.194 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 4.014 ; 3.986 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 2.902 ; 2.917 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 2.902 ; 2.917 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 3.148 ; 3.113 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 1.797 ; 1.796 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 1.967 ; 1.967 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 2.000 ; 2.014 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 1.929 ; 1.937 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 1.977 ; 2.002 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 1.904 ; 1.905 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 1.882 ; 1.886 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 1.897 ; 1.896 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 1.802 ; 1.796 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 1.862 ; 1.866 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 1.903 ; 1.908 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 1.880 ; 1.872 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 1.797 ; 1.796 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 1.892 ; 1.895 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 1.918 ; 1.931 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 1.876 ; 1.885 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 1.938 ; 1.933 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 2.265 ; 2.279 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.617 ; 2.649 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.573 ; 2.625 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.537 ; 2.592 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.994 ; 3.818 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.916 ; 2.995 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.630 ; 2.706 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.743 ; 2.822 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.644 ; 2.702 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.505 ; 2.533 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.610 ; 2.654 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.815 ; 2.798 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.486 ; 2.520 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.265 ; 2.279 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.582 ; 2.618 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.580 ; 2.619 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.469 ; 2.493 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 1.900 ; 1.903 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 1.982 ; 1.996 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 1.822 ; 1.806 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 3.418 ; 3.230 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -1.537 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -1.591 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Output Enable Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.588 ; 2.569 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.588 ; 2.569 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.878 ; 2.859 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.888 ; 2.869 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.774 ; 2.755 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.984 ; 2.965 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.878 ; 2.859 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.004 ; 2.985 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.981 ; 2.962 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.605 ; 2.586 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.605 ; 2.586 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.608 ; 2.589 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.595 ; 2.576 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.598 ; 2.579 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.608 ; 2.589 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.588 ; 2.569 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.984 ; 2.965 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 1.468 ; 1.468 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 1.468 ; 1.468 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 1.746 ; 1.746 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 1.756 ; 1.756 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 1.646 ; 1.646 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 1.848 ; 1.848 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 1.746 ; 1.746 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 1.868 ; 1.868 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 1.845 ; 1.845 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 1.486 ; 1.486 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 1.486 ; 1.486 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 1.488 ; 1.488 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 1.476 ; 1.476 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 1.478 ; 1.478 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 1.488 ; 1.488 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 1.468 ; 1.468 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 1.848 ; 1.848 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Output Disable Times ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.632 ; 2.632 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.632 ; 2.632 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.966 ; 2.966 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.976 ; 2.976 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.841 ; 2.841 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.081 ; 3.081 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.966 ; 2.966 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.101 ; 3.101 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.083 ; 3.083 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.651 ; 2.651 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.651 ; 2.651 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.652 ; 2.652 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.641 ; 2.641 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.642 ; 2.642 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.652 ; 2.652 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.632 ; 2.632 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.081 ; 3.081 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 1.510 ; 1.642 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 1.510 ; 1.642 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 1.831 ; 1.963 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 1.841 ; 1.973 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 1.711 ; 1.843 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 1.941 ; 2.073 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 1.831 ; 1.963 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 1.961 ; 2.093 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 1.943 ; 2.075 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 1.529 ; 1.661 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 1.529 ; 1.661 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 1.530 ; 1.662 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 1.519 ; 1.651 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 1.520 ; 1.652 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 1.530 ; 1.662 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 1.510 ; 1.642 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 1.941 ; 2.073 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ + + +---------------- +; MTBF Summary ; +---------------- +Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 40 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 13.232 ns + +Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 + + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Worst-Case MTBF (Years) ; Typical MTBF (Years) ; Included in Design MTBF ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.232 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; ; ; ; 7.589 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; ; ; ; 5.643 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.350 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; ; ; ; 7.443 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; ; ; ; 5.907 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.383 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; ; ; ; 7.593 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; ; ; ; 5.790 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.435 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; ; ; ; 7.400 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; ; ; ; 6.035 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.440 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; ; ; ; 7.524 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; ; ; ; 5.916 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.456 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; ; ; ; 7.524 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; ; ; ; 5.932 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.483 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; ; ; ; 7.588 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; ; ; ; 5.895 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.493 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; ; ; ; 7.591 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; ; ; ; 5.902 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.503 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; ; ; ; 7.401 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; ; ; ; 6.102 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.535 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; ; ; ; 7.526 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; ; ; ; 6.009 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.536 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; ; ; ; 7.525 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; ; ; ; 6.011 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.577 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; ; ; ; 7.401 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; ; ; ; 6.176 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.581 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; ; ; ; 7.590 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; ; ; ; 5.991 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.585 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; ; ; ; 7.402 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; ; ; ; 6.183 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.594 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; ; ; ; 7.522 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; ; ; ; 6.072 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.596 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; ; ; ; 7.593 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; ; ; ; 6.003 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.602 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; ; ; ; 7.525 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; ; ; ; 6.077 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.615 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; ; ; ; 7.527 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; ; ; ; 6.088 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.626 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; ; ; ; 7.524 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; ; ; ; 6.102 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.653 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ; ; ; 7.451 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; ; ; ; 6.202 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.659 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; ; ; ; 7.592 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; ; ; ; 6.067 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.664 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; ; ; ; 7.404 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; ; ; ; 6.260 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.672 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; ; ; ; 7.325 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; ; ; ; 6.347 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.689 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; ; ; ; 7.523 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; ; ; ; 6.166 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.691 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; ; ; ; 7.527 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; ; ; ; 6.164 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.702 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ; ; ; 7.450 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; ; ; ; 6.252 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.721 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; ; ; ; 7.249 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; ; ; ; 6.472 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.734 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; ; ; ; 7.592 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; ; ; ; 6.142 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.735 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; ; ; ; 7.590 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; ; ; ; 6.145 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.736 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; ; ; ; 7.402 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; ; ; ; 6.334 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.793 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; ; ; ; 7.599 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; ; ; ; 6.194 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.821 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; ; ; ; 7.591 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; ; ; ; 6.230 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.899 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; ; ; ; 7.591 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; ; ; ; 6.308 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.926 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; ; ; ; 7.593 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; ; ; ; 6.333 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.971 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; ; ; ; 7.593 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; ; ; ; 6.378 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.024 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; ; ; ; 7.527 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; ; ; ; 6.497 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.082 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; ; ; ; 7.592 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; ; ; ; 6.490 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.127 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; ; ; ; 7.592 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; ; ; ; 6.535 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.191 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; ; ; ; 7.600 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; ; ; ; 6.591 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.273 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; ; ; ; 7.526 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; ; ; ; 6.747 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + ++-------------------------------------------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------------------------------------------+---------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------------------------------------------+---------+-------+----------+---------+---------------------+ +; Worst-case Slack ; -0.454 ; 0.116 ; -1.497 ; 0.904 ; 3.736 ; +; CLOCK_50 ; 15.170 ; 0.187 ; 14.980 ; 0.904 ; 9.265 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.454 ; 0.116 ; -1.497 ; 2.414 ; 3.736 ; +; Design-wide TNS ; -22.246 ; 0.0 ; -338.162 ; 0.0 ; 0.0 ; +; CLOCK_50 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -22.246 ; 0.000 ; -338.162 ; 0.000 ; 0.000 ; ++------------------------------------------------------+---------+-------+----------+---------+---------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; 4.050 ; 4.731 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; 4.050 ; 4.731 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; 3.252 ; 3.792 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; 4.454 ; 5.044 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 4.454 ; 5.044 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 4.228 ; 4.804 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 4.088 ; 4.586 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.985 ; 4.485 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.971 ; 4.476 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.720 ; 4.223 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.722 ; 4.235 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.708 ; 4.219 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; -0.819 ; -1.598 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; -0.859 ; -1.656 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; -0.819 ; -1.598 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; -1.744 ; -2.479 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; -2.164 ; -2.955 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; -2.015 ; -2.819 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; -1.949 ; -2.683 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; -1.891 ; -2.635 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; -1.881 ; -2.624 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; -1.754 ; -2.483 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; -1.760 ; -2.494 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; -1.744 ; -2.479 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 7.004 ; 7.069 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 7.004 ; 7.069 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 6.882 ; 6.755 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 4.954 ; 4.908 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 4.954 ; 4.908 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 5.291 ; 5.346 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 3.733 ; 3.645 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 3.702 ; 3.596 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 3.732 ; 3.645 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 3.589 ; 3.523 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 3.733 ; 3.638 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 3.576 ; 3.509 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 3.533 ; 3.439 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 3.580 ; 3.472 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 3.373 ; 3.274 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 3.536 ; 3.433 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 3.594 ; 3.493 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 3.526 ; 3.425 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 3.389 ; 3.299 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 3.546 ; 3.449 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 3.624 ; 3.533 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 3.569 ; 3.489 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 3.685 ; 3.582 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 7.764 ; 7.387 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 5.853 ; 5.686 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 5.923 ; 5.772 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 5.841 ; 5.703 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 7.764 ; 7.387 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 5.747 ; 5.603 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 5.667 ; 5.552 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 6.210 ; 6.073 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 5.690 ; 5.589 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 5.631 ; 5.599 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 5.178 ; 5.147 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 5.631 ; 5.557 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 5.436 ; 5.269 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 5.663 ; 5.519 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 5.466 ; 5.409 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 6.063 ; 5.900 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 5.624 ; 5.492 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 3.597 ; 3.540 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 3.733 ; 3.650 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 3.442 ; 3.340 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 5.583 ; 5.291 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -0.448 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -0.595 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 4.014 ; 3.986 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 4.082 ; 4.194 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 4.014 ; 3.986 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 2.902 ; 2.917 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 2.902 ; 2.917 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 3.148 ; 3.113 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 1.797 ; 1.796 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 1.967 ; 1.967 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 2.000 ; 2.014 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 1.929 ; 1.937 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 1.977 ; 2.002 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 1.904 ; 1.905 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 1.882 ; 1.886 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 1.897 ; 1.896 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 1.802 ; 1.796 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 1.862 ; 1.866 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 1.903 ; 1.908 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 1.880 ; 1.872 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 1.797 ; 1.796 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 1.892 ; 1.895 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 1.918 ; 1.931 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 1.876 ; 1.885 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 1.938 ; 1.933 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 2.265 ; 2.279 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.617 ; 2.649 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.573 ; 2.625 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.537 ; 2.592 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.994 ; 3.818 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.916 ; 2.995 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.630 ; 2.706 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.743 ; 2.822 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.644 ; 2.702 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.505 ; 2.533 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.610 ; 2.654 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.815 ; 2.798 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.486 ; 2.520 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.265 ; 2.279 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.582 ; 2.618 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.580 ; 2.619 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.469 ; 2.493 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 1.900 ; 1.903 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 1.982 ; 1.996 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 1.822 ; 1.806 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 3.418 ; 3.230 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -1.537 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -1.591 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; DRAM_LDQM ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_UDQM ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_BA_1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_BA_0 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_CAS_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_CKE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_CS_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_RAS_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_WE_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_CLK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_CLK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_HS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_VS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_B[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_B[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_B[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_B[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_G[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_G[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_G[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_G[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_R[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_R[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_R[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_R[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[31] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[30] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[29] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[28] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[27] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[26] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[25] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[24] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[23] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[22] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[21] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[20] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[19] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[18] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[17] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[16] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; GPIO_1_CLKIN[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[15] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[14] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[13] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[12] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[11] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[31] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[30] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[29] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[28] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[27] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[26] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[25] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[24] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[23] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[22] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[21] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[20] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[19] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[18] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[17] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[16] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[15] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[14] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[13] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[12] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[11] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1_CLKIN[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; KEY[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; KEY[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; KEY[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow Corner Signal Integrity Metrics ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; DRAM_LDQM ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_UDQM ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_BA_1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_BA_0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_CAS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_CKE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_CS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_RAS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_WE_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.08 V ; -0.00596 V ; 0.305 V ; 0.266 V ; 5.3e-09 s ; 4.39e-09 s ; Yes ; Yes ; 3.08 V ; 3.08e-06 V ; 3.08 V ; -0.00596 V ; 0.305 V ; 0.266 V ; 5.3e-09 s ; 4.39e-09 s ; Yes ; Yes ; +; DRAM_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; VGA_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; VGA_HS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_VS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; DRAM_ADDR[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; LEDG[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.08 V ; -0.00513 V ; 0.274 V ; 0.267 V ; 5.67e-09 s ; 4.62e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.08 V ; -0.00513 V ; 0.274 V ; 0.267 V ; 5.67e-09 s ; 4.62e-09 s ; No ; Yes ; +; LEDG[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_B[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_B[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_B[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_B[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_G[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_G[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_G[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_G[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_R[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_R[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_R[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_R[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; DRAM_DQ[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.08 V ; -0.00596 V ; 0.305 V ; 0.266 V ; 5.3e-09 s ; 4.39e-09 s ; Yes ; Yes ; 3.08 V ; 3.08e-06 V ; 3.08 V ; -0.00596 V ; 0.305 V ; 0.266 V ; 5.3e-09 s ; 4.39e-09 s ; Yes ; Yes ; +; DRAM_DQ[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[31] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[30] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[29] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[28] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[27] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[26] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[25] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[24] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[23] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[22] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[21] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[20] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[19] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[18] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.02e-06 V ; 3.14 V ; -0.0402 V ; 0.146 V ; 0.156 V ; 4.62e-10 s ; 4.36e-10 s ; Yes ; Yes ; 3.08 V ; 1.02e-06 V ; 3.14 V ; -0.0402 V ; 0.146 V ; 0.156 V ; 4.62e-10 s ; 4.36e-10 s ; Yes ; Yes ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast Corner Signal Integrity Metrics ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; DRAM_LDQM ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_UDQM ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_BA_1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_BA_0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_CAS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_CKE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_CS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_RAS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_WE_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.48 V ; -0.0142 V ; 0.362 V ; 0.291 V ; 3.89e-09 s ; 3.25e-09 s ; No ; No ; 3.46 V ; 1.9e-07 V ; 3.48 V ; -0.0142 V ; 0.362 V ; 0.291 V ; 3.89e-09 s ; 3.25e-09 s ; No ; No ; +; DRAM_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; VGA_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; VGA_HS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_VS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; DRAM_ADDR[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; LEDG[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.346 V ; 4.12e-09 s ; 3.34e-09 s ; No ; Yes ; 3.46 V ; 1.29e-07 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.346 V ; 4.12e-09 s ; 3.34e-09 s ; No ; Yes ; +; LEDG[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_B[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_B[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_B[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_B[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_G[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_G[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_G[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_G[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_R[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_R[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_R[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_R[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; DRAM_DQ[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.48 V ; -0.0142 V ; 0.362 V ; 0.291 V ; 3.89e-09 s ; 3.25e-09 s ; No ; No ; 3.46 V ; 1.9e-07 V ; 3.48 V ; -0.0142 V ; 0.362 V ; 0.291 V ; 3.89e-09 s ; 3.25e-09 s ; No ; No ; +; DRAM_DQ[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[31] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[30] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[29] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[28] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[27] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[26] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[25] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[24] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[23] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[22] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[21] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[20] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[19] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[18] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.52e-08 V ; 3.58 V ; -0.064 V ; 0.234 V ; 0.085 V ; 2.93e-10 s ; 3.07e-10 s ; Yes ; Yes ; 3.46 V ; 6.52e-08 V ; 3.58 V ; -0.064 V ; 0.234 V ; 0.085 V ; 2.93e-10 s ; 3.07e-10 s ; Yes ; Yes ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup Transfers ; ++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 3186 ; 0 ; 0 ; 0 ; +; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 141 ; 0 ; 0 ; 0 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 11681 ; 0 ; 0 ; 0 ; ++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold Transfers ; ++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 3186 ; 0 ; 0 ; 0 ; +; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 141 ; 0 ; 0 ; 0 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 11681 ; 0 ; 0 ; 0 ; ++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++--------------------------------------------------------------------------------------------------------------+ +; Recovery Transfers ; ++------------+-----------------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+-----------------------------------------------------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 519 ; 0 ; 0 ; 0 ; +; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 302 ; 0 ; 0 ; 0 ; ++------------+-----------------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++--------------------------------------------------------------------------------------------------------------+ +; Removal Transfers ; ++------------+-----------------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+-----------------------------------------------------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 519 ; 0 ; 0 ; 0 ; +; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 302 ; 0 ; 0 ; 0 ; ++------------+-----------------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 3 ; 3 ; +; Unconstrained Input Ports ; 29 ; 29 ; +; Unconstrained Input Port Paths ; 102 ; 102 ; +; Unconstrained Output Ports ; 94 ; 94 ; +; Unconstrained Output Port Paths ; 472 ; 472 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer + Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version + Info: Processing started: Mon Mar 17 10:02:46 2014 +Info: Command: quartus_sta DE0_D5M -c DE0_D5M +Info: qsta_default_script.tcl version: #1 +Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (332164): Evaluating HDL-embedded SDC commands + Info (332165): Entity dcfifo_v5o1 + Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* + Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* +Info (332104): Reading SDC File: 'DE0_D5M.sdc' +Info (332110): Deriving PLL clocks + Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[0]} {inst|u6|altpll_component|auto_generated|pll1|clk[0]} + Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[1]} {inst|u6|altpll_component|auto_generated|pll1|clk[1]} +Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment. +Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. + Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold) + Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) + Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1200mV 85C Model +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. +Info (332146): Worst-case setup slack is -0.454 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -0.454 -22.246 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 15.170 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.214 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.214 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.358 0.000 CLOCK_50 +Info (332146): Worst-case recovery slack is -1.497 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -1.497 -338.162 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 14.980 0.000 CLOCK_50 +Info (332146): Worst-case removal slack is 1.616 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 1.616 0.000 CLOCK_50 + Info (332119): 4.132 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case minimum pulse width slack is 3.736 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 3.736 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.580 0.000 CLOCK_50 +Info (332114): Report Metastability: Found 40 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 40 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 11.051 ns + Info (332114): + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment. +Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. + Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold) + Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) + Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) +Info (332146): Worst-case setup slack is 0.053 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.053 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 15.677 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.190 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.190 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.312 0.000 CLOCK_50 +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. +Info (332146): Worst-case recovery slack is -0.843 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -0.843 -150.984 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 15.539 0.000 CLOCK_50 +Info (332146): Worst-case removal slack is 1.477 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 1.477 0.000 CLOCK_50 + Info (332119): 3.638 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case minimum pulse width slack is 3.741 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 3.741 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.561 0.000 CLOCK_50 +Info (332114): Report Metastability: Found 40 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 40 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 11.581 ns + Info (332114): + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 +Info: Analyzing Fast 1200mV 0C Model +Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment. +Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. + Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold) + Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) + Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) +Info (332146): Worst-case setup slack is 1.424 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 1.424 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 17.244 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.116 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.116 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.187 0.000 CLOCK_50 +Info (332146): Worst-case recovery slack is 0.773 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.773 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 17.090 0.000 CLOCK_50 +Info (332146): Worst-case removal slack is 0.904 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.904 0.000 CLOCK_50 + Info (332119): 2.414 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case minimum pulse width slack is 3.748 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 3.748 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.265 0.000 CLOCK_50 +Info (332114): Report Metastability: Found 40 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 40 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 13.232 ns + Info (332114): + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 23 warnings + Info: Peak virtual memory: 549 megabytes + Info: Processing ended: Mon Mar 17 10:02:50 2014 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:03 + + |