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Diffstat (limited to 'student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt')
| -rw-r--r-- | student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt | 10440 |
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diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt new file mode 100644 index 0000000..436046b --- /dev/null +++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt @@ -0,0 +1,10440 @@ +TimeQuest Timing Analyzer report for DE0_D5M +Tue Mar 08 16:24:59 2016 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. SDC File List + 5. Clocks + 6. Slow 1200mV 85C Model Fmax Summary + 7. Timing Closure Recommendations + 8. Slow 1200mV 85C Model Setup Summary + 9. Slow 1200mV 85C Model Hold Summary + 10. Slow 1200mV 85C Model Recovery Summary + 11. Slow 1200mV 85C Model Removal Summary + 12. Slow 1200mV 85C Model Minimum Pulse Width Summary + 13. Slow 1200mV 85C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 14. Slow 1200mV 85C Model Setup: 'CLOCK_50' + 15. Slow 1200mV 85C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 16. Slow 1200mV 85C Model Hold: 'CLOCK_50' + 17. Slow 1200mV 85C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 18. Slow 1200mV 85C Model Recovery: 'CLOCK_50' + 19. Slow 1200mV 85C Model Removal: 'CLOCK_50' + 20. Slow 1200mV 85C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 21. Slow 1200mV 85C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 22. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' + 23. Setup Times + 24. Hold Times + 25. Clock to Output Times + 26. Minimum Clock to Output Times + 27. Propagation Delay + 28. Minimum Propagation Delay + 29. Output Enable Times + 30. Minimum Output Enable Times + 31. Output Disable Times + 32. Minimum Output Disable Times + 33. MTBF Summary + 34. Synchronizer Summary + 35. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years + 36. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years + 37. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years + 38. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years + 39. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years + 40. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years + 41. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years + 42. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years + 43. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years + 44. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years + 45. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years + 46. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years + 47. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years + 48. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years + 49. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years + 50. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years + 51. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years + 52. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years + 53. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years + 54. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years + 55. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years + 56. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years + 57. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years + 58. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years + 59. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years + 60. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years + 61. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years + 62. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years + 63. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years + 64. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years + 65. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years + 66. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years + 67. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years + 68. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years + 69. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years + 70. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years + 71. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years + 72. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years + 73. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years + 74. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years + 75. Slow 1200mV 0C Model Fmax Summary + 76. Slow 1200mV 0C Model Setup Summary + 77. Slow 1200mV 0C Model Hold Summary + 78. Slow 1200mV 0C Model Recovery Summary + 79. Slow 1200mV 0C Model Removal Summary + 80. Slow 1200mV 0C Model Minimum Pulse Width Summary + 81. Slow 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 82. Slow 1200mV 0C Model Setup: 'CLOCK_50' + 83. Slow 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 84. Slow 1200mV 0C Model Hold: 'CLOCK_50' + 85. Slow 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 86. Slow 1200mV 0C Model Recovery: 'CLOCK_50' + 87. Slow 1200mV 0C Model Removal: 'CLOCK_50' + 88. Slow 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 89. Slow 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 90. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' + 91. Setup Times + 92. Hold Times + 93. Clock to Output Times + 94. Minimum Clock to Output Times + 95. Propagation Delay + 96. Minimum Propagation Delay + 97. Output Enable Times + 98. Minimum Output Enable Times + 99. Output Disable Times +100. Minimum Output Disable Times +101. MTBF Summary +102. Synchronizer Summary +103. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +104. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years +105. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years +106. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years +107. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years +108. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years +109. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years +110. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years +111. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years +112. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years +113. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years +114. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years +115. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years +116. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years +117. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years +118. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years +119. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years +120. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years +121. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years +122. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years +123. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years +124. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years +125. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years +126. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years +127. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years +128. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years +129. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years +130. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years +131. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years +132. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years +133. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years +134. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years +135. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years +136. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years +137. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years +138. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years +139. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years +140. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years +141. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years +142. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years +143. Fast 1200mV 0C Model Setup Summary +144. Fast 1200mV 0C Model Hold Summary +145. Fast 1200mV 0C Model Recovery Summary +146. Fast 1200mV 0C Model Removal Summary +147. Fast 1200mV 0C Model Minimum Pulse Width Summary +148. Fast 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' +149. Fast 1200mV 0C Model Setup: 'CLOCK_50' +150. Fast 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' +151. Fast 1200mV 0C Model Hold: 'CLOCK_50' +152. Fast 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' +153. Fast 1200mV 0C Model Recovery: 'CLOCK_50' +154. Fast 1200mV 0C Model Removal: 'CLOCK_50' +155. Fast 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' +156. Fast 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' +157. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' +158. Setup Times +159. Hold Times +160. Clock to Output Times +161. Minimum Clock to Output Times +162. Propagation Delay +163. Minimum Propagation Delay +164. Output Enable Times +165. Minimum Output Enable Times +166. Output Disable Times +167. Minimum Output Disable Times +168. MTBF Summary +169. Synchronizer Summary +170. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +171. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years +172. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years +173. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years +174. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years +175. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years +176. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years +177. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years +178. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years +179. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years +180. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years +181. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years +182. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years +183. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years +184. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years +185. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years +186. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years +187. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years +188. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years +189. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years +190. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years +191. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years +192. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years +193. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years +194. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years +195. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years +196. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years +197. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years +198. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years +199. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years +200. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years +201. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years +202. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years +203. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years +204. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years +205. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years +206. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years +207. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years +208. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years +209. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years +210. Multicorner Timing Analysis Summary +211. Setup Times +212. Hold Times +213. Clock to Output Times +214. Minimum Clock to Output Times +215. Progagation Delay +216. Minimum Progagation Delay +217. Board Trace Model Assignments +218. Input Transition Times +219. Slow Corner Signal Integrity Metrics +220. Fast Corner Signal Integrity Metrics +221. Setup Transfers +222. Hold Transfers +223. Recovery Transfers +224. Removal Transfers +225. Report TCCS +226. Report RSKM +227. Unconstrained Paths +228. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+--------------------------------------------------------------------+ +; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version ; +; Revision Name ; DE0_D5M ; +; Device Family ; Cyclone III ; +; Device Name ; EP3C16F484C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++--------------------+--------------------------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; < 0.1% ; +; Processors 5-8 ; 0.0% ; ++----------------------------+-------------+ + + ++---------------------------------------------------+ +; SDC File List ; ++---------------+--------+--------------------------+ +; SDC File Path ; Status ; Read at ; ++---------------+--------+--------------------------+ +; DE0_D5M.sdc ; OK ; Tue Mar 08 16:24:52 2016 ; ++---------------+--------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+ +; CLOCK_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8.000 ; 125.0 MHz ; 0.000 ; 4.000 ; 50.00 ; 2 ; 5 ; ; ; ; ; false ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|inclk[0] ; { inst|u6|altpll_component|auto_generated|pll1|clk[0] } ; +; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 8.000 ; 125.0 MHz ; -2.600 ; 1.400 ; 50.00 ; 2 ; 5 ; -117.0 ; ; ; ; false ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|inclk[0] ; { inst|u6|altpll_component|auto_generated|pll1|clk[1] } ; ++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++------------+-----------------+-----------------------------------------------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+-----------------------------------------------------+------+ +; 167.25 MHz ; 167.25 MHz ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; +; 174.46 MHz ; 174.46 MHz ; CLOCK_50 ; ; ++------------+-----------------+-----------------------------------------------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + ++------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup Summary ; ++-----------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+--------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.837 ; -39.407 ; +; CLOCK_50 ; 14.268 ; 0.000 ; ++-----------------------------------------------------+--------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.331 ; 0.000 ; +; CLOCK_50 ; 0.358 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Recovery Summary ; ++-----------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+--------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -1.488 ; -368.986 ; +; CLOCK_50 ; 12.673 ; 0.000 ; ++-----------------------------------------------------+--------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Removal Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; CLOCK_50 ; 1.559 ; 0.000 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.115 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.734 ; 0.000 ; +; CLOCK_50 ; 9.580 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; -0.837 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.317 ; +; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.278 ; +; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.278 ; +; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.278 ; +; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.278 ; +; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.278 ; +; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.278 ; +; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.278 ; +; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.278 ; +; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.278 ; +; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.278 ; +; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.278 ; +; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.278 ; +; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.278 ; +; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.278 ; +; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.278 ; +; -0.760 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.239 ; +; -0.760 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.239 ; +; -0.760 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.239 ; +; -0.760 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.239 ; +; -0.760 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.239 ; +; -0.760 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.239 ; +; -0.760 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.239 ; +; -0.747 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.536 ; 2.226 ; +; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.046 ; +; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.046 ; +; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.046 ; +; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.046 ; +; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.046 ; +; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.046 ; +; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.046 ; +; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.046 ; +; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.046 ; +; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.046 ; +; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.046 ; +; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.046 ; +; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.046 ; +; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.046 ; +; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.046 ; +; -0.533 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.535 ; 2.013 ; +; -0.451 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.181 ; 2.285 ; +; -0.451 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.181 ; 2.285 ; +; -0.451 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.181 ; 2.285 ; +; -0.451 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.181 ; 2.285 ; +; -0.439 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.186 ; 2.268 ; +; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 1.901 ; +; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 1.901 ; +; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 1.901 ; +; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 1.901 ; +; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 1.901 ; +; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 1.901 ; +; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 1.901 ; +; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 1.901 ; +; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 1.901 ; +; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 1.901 ; +; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 1.901 ; +; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 1.901 ; +; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 1.901 ; +; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 1.901 ; +; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 1.901 ; +; -0.339 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.167 ; +; -0.339 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.167 ; +; -0.339 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.167 ; +; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 1.937 ; +; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 1.937 ; +; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 1.937 ; +; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 1.937 ; +; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 1.937 ; +; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 1.937 ; +; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 1.937 ; +; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 1.937 ; +; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 1.937 ; +; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 1.937 ; +; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 1.937 ; +; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 1.937 ; +; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 1.937 ; +; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 1.937 ; +; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 1.937 ; +; 0.017 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.186 ; 1.812 ; +; 0.017 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.186 ; 1.812 ; +; 0.017 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.186 ; 1.812 ; +; 2.021 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.413 ; 5.581 ; +; 2.036 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.425 ; 5.554 ; +; 2.045 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.425 ; 5.545 ; +; 2.103 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.414 ; 5.498 ; +; 2.103 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.414 ; 5.498 ; +; 2.103 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.414 ; 5.498 ; +; 2.103 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.414 ; 5.498 ; +; 2.103 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.414 ; 5.498 ; +; 2.103 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.414 ; 5.498 ; +; 2.103 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.414 ; 5.498 ; +; 2.105 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.414 ; 5.496 ; +; 2.117 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.413 ; 5.485 ; +; 2.123 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.425 ; 5.467 ; +; 2.146 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.425 ; 5.444 ; +; 2.159 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.413 ; 5.443 ; +; 2.178 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.414 ; 5.423 ; +; 2.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.066 ; 5.754 ; +; 2.199 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.414 ; 5.402 ; +; 2.199 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.414 ; 5.402 ; ++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'CLOCK_50' ; ++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 14.268 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 4.952 ; +; 14.302 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 4.918 ; +; 14.469 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 4.751 ; +; 14.553 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 4.667 ; +; 14.618 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 4.602 ; +; 14.760 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 4.460 ; +; 14.868 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 4.352 ; +; 14.922 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 4.298 ; +; 14.982 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 4.238 ; +; 15.048 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 4.172 ; +; 15.105 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 4.115 ; +; 15.132 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 4.088 ; +; 15.203 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 4.017 ; +; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.559 ; +; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.559 ; +; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.559 ; +; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.559 ; +; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.559 ; +; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.559 ; +; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.559 ; +; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.559 ; +; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.559 ; +; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.559 ; +; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.559 ; +; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.559 ; +; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.559 ; +; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.550 ; +; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.550 ; +; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.550 ; +; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.550 ; +; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.550 ; +; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.550 ; +; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.550 ; +; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.550 ; +; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.550 ; +; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.550 ; +; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.550 ; +; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.550 ; +; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.550 ; +; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.454 ; +; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.454 ; +; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.454 ; +; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.454 ; +; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.454 ; +; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.454 ; +; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.454 ; +; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.454 ; +; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.454 ; +; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.454 ; +; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.454 ; +; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.454 ; +; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.454 ; +; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.414 ; +; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.406 ; +; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.406 ; +; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.406 ; +; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.406 ; +; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.406 ; +; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.406 ; +; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.406 ; +; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.406 ; +; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.406 ; +; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.406 ; +; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.406 ; +; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.406 ; +; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.406 ; +; 15.628 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 3.592 ; +; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.316 ; +; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.316 ; +; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.316 ; +; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.316 ; +; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.316 ; +; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.316 ; +; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.316 ; +; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.316 ; +; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.316 ; +; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.316 ; +; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.316 ; +; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.316 ; +; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 4.316 ; +; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.260 ; +; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.260 ; +; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.260 ; +; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.260 ; +; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.260 ; +; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.260 ; +; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.260 ; +; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.260 ; +; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.260 ; +; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.260 ; +; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.260 ; +; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.260 ; +; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.260 ; +; 15.697 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.259 ; +; 15.697 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.259 ; +; 15.697 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.259 ; +; 15.697 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.259 ; +; 15.697 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.259 ; +; 15.697 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.259 ; +; 15.697 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.259 ; ++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; 0.331 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.376 ; 0.894 ; +; 0.336 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.901 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.905 ; +; 0.341 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.376 ; 0.904 ; +; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.577 ; +; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.577 ; +; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.577 ; +; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.577 ; +; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.393 ; 0.894 ; +; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.353 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.918 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.593 ; +; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.593 ; +; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.580 ; +; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.580 ; +; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.580 ; +; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.594 ; +; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.593 ; +; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.591 ; +; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.592 ; +; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.592 ; +; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.592 ; +; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.592 ; +; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.592 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_done ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CAS_N ; DE0_D5M:inst|Sdram_Control_4Port:u7|CAS_N ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|RAS_N ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[16] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[14] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.594 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.594 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.593 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.594 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.594 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.594 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[12] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.594 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.594 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.594 ; +; 0.376 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.595 ; +; 0.376 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.594 ; +; 0.376 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.595 ; +; 0.379 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_initial ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CS_N[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.598 ; +; 0.383 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.602 ; +; 0.383 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.602 ; +; 0.384 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.616 ; +; 0.390 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.608 ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'CLOCK_50' ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.577 ; +; 0.361 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.580 ; +; 0.362 ; ps2:inst6|clk_div[0] ; ps2:inst6|clk_div[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.580 ; +; 0.375 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.593 ; +; 0.382 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.600 ; +; 0.385 ; DE0_D5M:inst|rClk[0] ; DE0_D5M:inst|rClk[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.038 ; 0.580 ; +; 0.390 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.609 ; +; 0.408 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.627 ; +; 0.523 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.741 ; +; 0.551 ; ps2:inst6|clk_div[6] ; ps2:inst6|clk_div[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.769 ; +; 0.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.769 ; +; 0.554 ; ps2:inst6|clk_div[2] ; ps2:inst6|clk_div[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.772 ; +; 0.554 ; ps2:inst6|clk_div[4] ; ps2:inst6|clk_div[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.772 ; +; 0.555 ; ps2:inst6|clk_div[7] ; ps2:inst6|clk_div[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.773 ; +; 0.556 ; ps2:inst6|clk_div[3] ; ps2:inst6|clk_div[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.774 ; +; 0.556 ; ps2:inst6|clk_div[5] ; ps2:inst6|clk_div[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.774 ; +; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.775 ; +; 0.557 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.776 ; +; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.775 ; +; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.775 ; +; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.776 ; +; 0.558 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.777 ; +; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.776 ; +; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.776 ; +; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.777 ; +; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.777 ; +; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.777 ; +; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.777 ; +; 0.559 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.778 ; +; 0.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.777 ; +; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.778 ; +; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.779 ; +; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.779 ; +; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.779 ; +; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.779 ; +; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.779 ; +; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.780 ; +; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.780 ; +; 0.562 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.781 ; +; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.780 ; +; 0.563 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.782 ; +; 0.567 ; ps2:inst6|clk_div[0] ; ps2:inst6|clk_div[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.785 ; +; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.788 ; +; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.788 ; +; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.788 ; +; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.788 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.788 ; +; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.788 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.789 ; +; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.789 ; +; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.789 ; +; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.791 ; +; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.791 ; +; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.791 ; +; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.791 ; +; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.791 ; +; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.790 ; +; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.790 ; +; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.791 ; +; 0.573 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.792 ; +; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.791 ; +; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.791 ; +; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.791 ; +; 0.574 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.793 ; +; 0.574 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.793 ; +; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.792 ; +; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.793 ; +; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.793 ; +; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.793 ; +; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.794 ; +; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.793 ; +; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.793 ; +; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.793 ; +; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.793 ; +; 0.580 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.799 ; +; 0.582 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.800 ; +; 0.587 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.806 ; +; 0.588 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.807 ; +; 0.591 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.810 ; +; 0.594 ; ps2:inst6|clk_div[8] ; ps2:inst6|clk_div[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.038 ; 0.789 ; +; 0.611 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.830 ; +; 0.659 ; ps2:inst6|clk_div[7] ; ps2:inst6|clk_div[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.244 ; 1.060 ; +; 0.699 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.918 ; +; 0.699 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.918 ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.281 ; 3.156 ; +; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.281 ; 3.156 ; +; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.281 ; 3.156 ; +; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.281 ; 3.156 ; +; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.281 ; 3.156 ; +; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.281 ; 3.156 ; +; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.281 ; 3.156 ; +; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.281 ; 3.156 ; +; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.281 ; 3.156 ; +; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.281 ; 3.156 ; +; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.281 ; 3.156 ; +; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.281 ; 3.156 ; +; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.281 ; 3.156 ; +; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.281 ; 3.156 ; +; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.281 ; 3.156 ; +; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.281 ; 3.156 ; +; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.155 ; +; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.155 ; +; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.155 ; +; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.155 ; +; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.155 ; +; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.155 ; +; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.155 ; +; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.155 ; +; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.155 ; +; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.155 ; +; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.155 ; +; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.155 ; +; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.155 ; +; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.155 ; +; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.155 ; +; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.280 ; 3.155 ; +; -1.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.278 ; 3.198 ; +; -1.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.277 ; 3.197 ; +; -1.334 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.550 ; 2.799 ; +; -1.334 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.550 ; 2.799 ; +; -1.334 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.550 ; 2.799 ; +; -1.334 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.550 ; 2.799 ; +; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.541 ; 2.798 ; +; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.541 ; 2.798 ; +; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.541 ; 2.798 ; +; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.541 ; 2.798 ; +; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.541 ; 2.798 ; +; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.541 ; 2.798 ; +; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.541 ; 2.798 ; +; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.541 ; 2.798 ; +; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.541 ; 2.798 ; +; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.541 ; 2.797 ; +; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.541 ; 2.797 ; +; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.541 ; 2.797 ; +; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.541 ; 2.797 ; +; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.542 ; 2.796 ; +; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.542 ; 2.796 ; +; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.541 ; 2.797 ; +; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.542 ; 2.796 ; +; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.549 ; 2.789 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.533 ; 2.804 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.533 ; 2.804 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.533 ; 2.804 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.533 ; 2.804 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.805 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.533 ; 2.804 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.533 ; 2.804 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.533 ; 2.804 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.533 ; 2.804 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.533 ; 2.804 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.533 ; 2.804 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.533 ; 2.804 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.533 ; 2.804 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.533 ; 2.804 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.805 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.805 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.805 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.805 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.805 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.805 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.805 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.805 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.805 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.533 ; 2.804 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.805 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.805 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.794 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.794 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.794 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.794 ; +; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.794 ; +; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 2.802 ; +; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 2.802 ; +; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 2.802 ; +; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.804 ; +; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.804 ; +; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.804 ; +; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.804 ; +; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.804 ; +; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.804 ; +; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.804 ; +; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.804 ; +; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.534 ; 2.802 ; +; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.532 ; 2.804 ; ++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Recovery: 'CLOCK_50' ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 12.673 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 6.547 ; +; 12.682 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 6.538 ; +; 12.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 6.442 ; +; 12.825 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.796 ; 6.394 ; +; 12.916 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 6.304 ; +; 12.971 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.796 ; 6.248 ; +; 12.972 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.796 ; 6.247 ; +; 12.981 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.796 ; 6.238 ; +; 13.065 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.796 ; 6.154 ; +; 13.077 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.796 ; 6.142 ; +; 13.201 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.796 ; 6.018 ; +; 13.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.796 ; 6.014 ; +; 13.210 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.796 ; 6.009 ; +; 13.214 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.796 ; 6.005 ; +; 13.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.796 ; 5.914 ; +; 13.444 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.796 ; 5.775 ; +; 13.911 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 5.309 ; +; 14.011 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 5.209 ; +; 14.027 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.801 ; 5.187 ; +; 14.188 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 5.032 ; +; 14.197 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 5.023 ; +; 14.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 4.976 ; +; 14.294 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 4.926 ; +; 14.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 4.870 ; +; 14.431 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 4.789 ; +; 14.532 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.795 ; 4.688 ; +; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.747 ; +; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.747 ; +; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.747 ; +; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.747 ; +; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.747 ; +; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.747 ; +; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.747 ; +; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.747 ; +; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.747 ; +; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.747 ; +; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.747 ; +; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.747 ; +; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.747 ; +; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.747 ; +; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.747 ; +; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.747 ; +; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.738 ; +; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.738 ; +; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.738 ; +; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.738 ; +; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.738 ; +; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.738 ; +; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.738 ; +; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.738 ; +; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.738 ; +; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.738 ; +; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.738 ; +; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.738 ; +; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.738 ; +; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.738 ; +; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.738 ; +; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.738 ; +; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.642 ; +; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.642 ; +; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.642 ; +; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.642 ; +; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.642 ; +; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.642 ; +; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.642 ; +; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.642 ; +; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.642 ; +; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.642 ; +; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.642 ; +; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.642 ; +; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.642 ; +; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.642 ; +; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.642 ; +; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.642 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.594 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.594 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.594 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.594 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.594 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.594 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.594 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.594 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.594 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.594 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.594 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.594 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.594 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.594 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.594 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.594 ; +; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.504 ; +; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.504 ; +; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.504 ; +; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.504 ; +; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.504 ; +; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.504 ; +; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.504 ; +; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.504 ; +; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.504 ; +; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.061 ; 4.504 ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Removal: 'CLOCK_50' ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.778 ; +; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.778 ; +; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.778 ; +; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.778 ; +; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.778 ; +; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.778 ; +; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.778 ; +; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.778 ; +; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.778 ; +; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.778 ; +; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.778 ; +; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.778 ; +; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.778 ; +; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.778 ; +; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.778 ; +; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.778 ; +; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.882 ; +; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.882 ; +; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.882 ; +; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.882 ; +; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.882 ; +; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.882 ; +; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.882 ; +; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.882 ; +; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.882 ; +; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.882 ; +; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.882 ; +; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.882 ; +; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.882 ; +; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.882 ; +; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.882 ; +; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 1.882 ; +; 2.109 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 2.336 ; +; 2.109 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 2.336 ; +; 2.109 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 2.336 ; +; 2.109 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 2.336 ; +; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 2.350 ; +; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 2.350 ; +; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 2.350 ; +; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 2.350 ; +; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 2.350 ; +; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 2.350 ; +; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 2.350 ; +; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 2.350 ; +; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 2.350 ; +; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 2.350 ; +; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 2.350 ; +; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 2.350 ; +; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 2.350 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 2.644 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 2.644 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 2.644 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 2.644 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 2.644 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 2.644 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 2.644 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 2.644 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 2.644 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 2.644 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 2.644 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 2.644 ; +; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.687 ; +; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.687 ; +; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.687 ; +; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.687 ; +; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.687 ; +; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.687 ; +; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.687 ; +; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.687 ; +; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.687 ; +; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.687 ; +; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.687 ; +; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.687 ; +; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.687 ; +; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.687 ; +; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.687 ; +; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.687 ; +; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.696 ; +; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.696 ; +; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.696 ; +; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.696 ; +; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.696 ; +; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.696 ; +; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.696 ; +; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.696 ; +; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.696 ; +; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.696 ; +; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.696 ; +; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.696 ; +; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.696 ; +; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.696 ; +; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.696 ; +; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.696 ; +; 2.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.792 ; +; 2.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.792 ; +; 2.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.792 ; +; 2.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.792 ; +; 2.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.792 ; +; 2.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.792 ; +; 2.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.792 ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; 4.115 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.671 ; 2.601 ; +; 4.131 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.682 ; 2.606 ; +; 4.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.605 ; +; 4.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.605 ; +; 4.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.605 ; +; 4.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.605 ; +; 4.139 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.596 ; +; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.601 ; +; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.601 ; +; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.688 ; 2.609 ; +; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.608 ; +; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.608 ; +; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.601 ; +; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.601 ; +; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.601 ; +; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.601 ; +; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.601 ; +; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.601 ; +; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.609 ; +; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.609 ; +; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.609 ; +; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.609 ; +; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.609 ; +; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.609 ; +; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.609 ; +; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.693 ; 2.605 ; +; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.693 ; 2.605 ; +; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.693 ; 2.605 ; +; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.693 ; 2.605 ; +; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.693 ; 2.605 ; +; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.693 ; 2.605 ; +; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.693 ; 2.605 ; +; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.693 ; 2.605 ; +; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.693 ; 2.605 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.601 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.601 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.699 ; 2.602 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.601 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.601 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.601 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.699 ; 2.602 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.601 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.601 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.699 ; 2.602 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.601 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.601 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.601 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.699 ; 2.602 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.699 ; 2.602 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.601 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.601 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.699 ; 2.602 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.699 ; 2.602 ; +; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.601 ; +; 4.154 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.703 ; 2.608 ; +; 4.154 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.703 ; 2.608 ; +; 4.154 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.703 ; 2.608 ; +; 4.154 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.703 ; 2.608 ; +; 4.154 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.703 ; 2.608 ; +; 4.154 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.703 ; 2.608 ; +; 4.154 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.703 ; 2.608 ; +; 4.166 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.728 ; 2.595 ; +; 4.166 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.728 ; 2.595 ; +; 4.166 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.728 ; 2.595 ; +; 4.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.713 ; 2.612 ; +; 4.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.713 ; 2.612 ; +; 4.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.713 ; 2.612 ; +; 4.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.713 ; 2.612 ; +; 4.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.713 ; 2.612 ; +; 4.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.713 ; 2.612 ; +; 4.170 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.722 ; 2.605 ; +; 4.170 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.722 ; 2.605 ; +; 4.170 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.722 ; 2.605 ; +; 4.170 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.722 ; 2.605 ; +; 4.170 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.722 ; 2.605 ; +; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.721 ; 2.607 ; +; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.721 ; 2.607 ; +; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.721 ; 2.607 ; +; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.721 ; 2.607 ; +; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.721 ; 2.607 ; +; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.721 ; 2.607 ; +; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.721 ; 2.607 ; +; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.721 ; 2.607 ; +; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.721 ; 2.607 ; +; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.728 ; 2.600 ; +; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.721 ; 2.607 ; +; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.728 ; 2.600 ; +; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.728 ; 2.600 ; +; 4.173 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.728 ; 2.602 ; +; 4.173 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.728 ; 2.602 ; +; 4.173 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.728 ; 2.602 ; +; 4.173 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.728 ; 2.602 ; +; 4.173 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.728 ; 2.602 ; +; 4.173 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.728 ; 2.602 ; +; 4.173 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.728 ; 2.602 ; +; 4.175 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.726 ; 2.606 ; +; 4.175 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.726 ; 2.606 ; +; 4.175 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.726 ; 2.606 ; +; 4.175 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.726 ; 2.606 ; +; 4.175 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.726 ; 2.606 ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 3.734 ; 3.964 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; +; 3.734 ; 3.964 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0 ; +; 3.734 ; 3.964 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg ; +; 3.735 ; 3.965 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; +; 3.735 ; 3.965 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0 ; +; 3.735 ; 3.965 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; +; 3.753 ; 3.969 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; +; 3.753 ; 3.969 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; +; 3.753 ; 3.969 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; +; 3.753 ; 3.969 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; 3.753 ; 3.969 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; 3.753 ; 3.969 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[0] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[10] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[11] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[12] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[13] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[14] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[15] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[1] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[2] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[3] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[4] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[5] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[6] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[7] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[8] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[9] ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3] ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6] ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; ++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' ; ++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+ +; 9.580 ; 9.764 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[0] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[1] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[2] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[3] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[4] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[5] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[6] ; +; 9.591 ; 9.775 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[7] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_1 ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; ++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; 4.175 ; 4.835 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; 4.175 ; 4.835 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; 3.570 ; 4.128 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; 4.346 ; 4.882 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.719 ; 4.304 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.888 ; 4.403 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.837 ; 4.347 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 4.081 ; 4.605 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.797 ; 4.328 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.695 ; 4.207 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 4.048 ; 4.575 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.537 ; 4.045 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.682 ; 4.211 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.737 ; 4.250 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.742 ; 4.251 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.421 ; 3.933 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.713 ; 4.225 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.625 ; 4.168 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 4.346 ; 4.882 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; -1.845 ; -2.405 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; -1.845 ; -2.427 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; -1.884 ; -2.405 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; -2.726 ; -3.218 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; -3.015 ; -3.577 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; -3.213 ; -3.718 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; -3.164 ; -3.665 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; -3.400 ; -3.914 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; -3.085 ; -3.597 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; -3.015 ; -3.508 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; -3.367 ; -3.884 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; -2.835 ; -3.324 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; -2.987 ; -3.507 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; -3.057 ; -3.551 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; -3.061 ; -3.551 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; -2.726 ; -3.218 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; -3.034 ; -3.526 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; -2.925 ; -3.447 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; -3.653 ; -4.179 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 7.926 ; 7.746 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 6.149 ; 6.132 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 7.926 ; 7.746 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 6.407 ; 6.287 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 6.407 ; 6.287 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 5.330 ; 5.394 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 3.444 ; 3.336 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 3.223 ; 3.114 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 3.394 ; 3.270 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 3.393 ; 3.273 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 3.194 ; 3.089 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 3.242 ; 3.141 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 2.965 ; 2.870 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 3.035 ; 2.936 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 3.444 ; 3.336 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 3.208 ; 3.095 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 3.424 ; 3.303 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 3.007 ; 2.910 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 2.990 ; 2.893 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 2.996 ; 2.900 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 3.000 ; 2.907 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 2.965 ; 2.866 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 3.315 ; 3.195 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 6.815 ; 6.557 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 5.037 ; 4.853 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 5.167 ; 4.959 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 5.229 ; 5.016 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 6.815 ; 6.557 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 5.405 ; 5.227 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 5.223 ; 5.014 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 5.360 ; 5.203 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 5.549 ; 5.513 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 5.131 ; 5.050 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 4.801 ; 4.763 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 5.067 ; 4.895 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 4.775 ; 4.677 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 4.893 ; 4.820 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 5.056 ; 4.954 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 4.932 ; 4.824 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 5.289 ; 5.224 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 3.211 ; 3.112 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 3.148 ; 3.043 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 3.560 ; 3.464 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 5.206 ; 4.875 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -0.575 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -0.703 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 6.003 ; 5.982 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 6.003 ; 5.982 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 7.711 ; 7.532 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 6.251 ; 6.130 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 6.251 ; 6.130 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 5.211 ; 5.277 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 2.545 ; 2.449 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 2.794 ; 2.684 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 2.958 ; 2.834 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 2.957 ; 2.837 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 2.765 ; 2.659 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 2.812 ; 2.711 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 2.545 ; 2.449 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 2.613 ; 2.514 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 3.007 ; 2.897 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 2.779 ; 2.665 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 2.987 ; 2.865 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 2.586 ; 2.488 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 2.570 ; 2.472 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 2.575 ; 2.479 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 2.580 ; 2.486 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 2.544 ; 2.445 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 2.880 ; 2.760 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 3.652 ; 3.513 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.652 ; 3.514 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.941 ; 3.843 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 4.014 ; 3.921 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 5.754 ; 5.423 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 4.173 ; 4.062 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.997 ; 3.903 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.966 ; 3.855 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 4.167 ; 4.084 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.879 ; 3.786 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.663 ; 3.513 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.978 ; 3.869 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.828 ; 3.736 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.788 ; 3.664 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 4.177 ; 4.091 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.763 ; 3.612 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 4.126 ; 3.964 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 2.782 ; 2.681 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 2.721 ; 2.615 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 3.117 ; 3.020 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 4.777 ; 4.446 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -0.948 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -1.075 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++------------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+--------+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+--------+--------+ +; SW[4] ; VGA_B[0] ; 8.826 ; 8.684 ; 9.435 ; 9.293 ; +; SW[4] ; VGA_B[1] ; 9.179 ; 9.016 ; 9.739 ; 9.533 ; +; SW[4] ; VGA_B[2] ; 8.250 ; 8.155 ; 8.832 ; 8.739 ; +; SW[4] ; VGA_B[3] ; 8.364 ; 8.243 ; 8.973 ; 8.852 ; +; SW[4] ; VGA_G[0] ; 9.485 ; 9.420 ; 10.061 ; 9.947 ; +; SW[4] ; VGA_G[1] ; 8.548 ; 8.524 ; 9.170 ; 9.146 ; +; SW[4] ; VGA_G[2] ; 8.898 ; 8.839 ; 9.483 ; 9.352 ; +; SW[4] ; VGA_G[3] ; 8.888 ; 8.793 ; 9.498 ; 9.407 ; +; SW[4] ; VGA_R[0] ; 9.747 ; 9.647 ; 10.341 ; 10.272 ; +; SW[4] ; VGA_R[1] ; 9.114 ; 8.972 ; 9.685 ; 9.510 ; +; SW[4] ; VGA_R[2] ; 8.692 ; 8.534 ; 9.241 ; 9.092 ; +; SW[4] ; VGA_R[3] ; 8.517 ; 8.427 ; 9.113 ; 9.023 ; +; SW[5] ; VGA_B[0] ; 8.458 ; 8.316 ; 9.069 ; 8.927 ; +; SW[5] ; VGA_B[1] ; 8.540 ; 8.377 ; 9.057 ; 8.894 ; +; SW[5] ; VGA_B[2] ; 8.138 ; 8.045 ; 8.672 ; 8.553 ; +; SW[5] ; VGA_B[3] ; 7.996 ; 7.875 ; 8.606 ; 8.485 ; +; SW[5] ; VGA_G[0] ; 8.837 ; 8.772 ; 9.396 ; 9.326 ; +; SW[5] ; VGA_G[1] ; 8.195 ; 8.171 ; 8.754 ; 8.730 ; +; SW[5] ; VGA_G[2] ; 8.330 ; 8.252 ; 8.870 ; 8.783 ; +; SW[5] ; VGA_G[3] ; 8.527 ; 8.427 ; 9.130 ; 9.039 ; +; SW[5] ; VGA_R[0] ; 9.391 ; 9.296 ; 9.924 ; 9.857 ; +; SW[5] ; VGA_R[1] ; 8.481 ; 8.339 ; 9.004 ; 8.854 ; +; SW[5] ; VGA_R[2] ; 8.101 ; 7.943 ; 8.629 ; 8.475 ; +; SW[5] ; VGA_R[3] ; 8.269 ; 8.189 ; 8.912 ; 8.822 ; ++------------+-------------+-------+-------+--------+--------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; SW[4] ; VGA_B[0] ; 8.505 ; 8.371 ; 9.099 ; 8.956 ; +; SW[4] ; VGA_B[1] ; 8.308 ; 8.149 ; 8.909 ; 8.691 ; +; SW[4] ; VGA_B[2] ; 8.029 ; 7.903 ; 8.567 ; 8.441 ; +; SW[4] ; VGA_B[3] ; 7.809 ; 7.683 ; 8.354 ; 8.267 ; +; SW[4] ; VGA_G[0] ; 9.056 ; 8.936 ; 9.698 ; 9.551 ; +; SW[4] ; VGA_G[1] ; 7.538 ; 7.459 ; 8.104 ; 8.016 ; +; SW[4] ; VGA_G[2] ; 8.515 ; 8.402 ; 9.121 ; 9.001 ; +; SW[4] ; VGA_G[3] ; 7.770 ; 7.674 ; 8.371 ; 8.200 ; +; SW[4] ; VGA_R[0] ; 9.357 ; 9.236 ; 9.971 ; 9.823 ; +; SW[4] ; VGA_R[1] ; 8.194 ; 8.022 ; 8.761 ; 8.580 ; +; SW[4] ; VGA_R[2] ; 8.350 ; 8.200 ; 8.920 ; 8.761 ; +; SW[4] ; VGA_R[3] ; 7.815 ; 7.795 ; 8.447 ; 8.280 ; +; SW[5] ; VGA_B[0] ; 7.485 ; 7.350 ; 8.004 ; 7.899 ; +; SW[5] ; VGA_B[1] ; 8.252 ; 8.083 ; 8.766 ; 8.588 ; +; SW[5] ; VGA_B[2] ; 7.423 ; 7.363 ; 8.002 ; 7.863 ; +; SW[5] ; VGA_B[3] ; 7.717 ; 7.604 ; 8.306 ; 8.184 ; +; SW[5] ; VGA_G[0] ; 7.526 ; 7.382 ; 8.048 ; 7.936 ; +; SW[5] ; VGA_G[1] ; 7.862 ; 7.809 ; 8.431 ; 8.333 ; +; SW[5] ; VGA_G[2] ; 7.578 ; 7.443 ; 8.106 ; 7.962 ; +; SW[5] ; VGA_G[3] ; 8.201 ; 8.100 ; 8.810 ; 8.650 ; +; SW[5] ; VGA_R[0] ; 7.685 ; 7.540 ; 8.208 ; 8.095 ; +; SW[5] ; VGA_R[1] ; 8.250 ; 8.079 ; 8.756 ; 8.591 ; +; SW[5] ; VGA_R[2] ; 7.806 ; 7.645 ; 8.316 ; 8.215 ; +; SW[5] ; VGA_R[3] ; 7.928 ; 7.894 ; 8.507 ; 8.436 ; ++------------+-------------+-------+-------+-------+-------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Output Enable Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 3.126 ; 3.126 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.734 ; 3.734 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.372 ; 3.372 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.382 ; 3.382 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.652 ; 3.652 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.126 ; 3.126 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.372 ; 3.372 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.146 ; 3.146 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.333 ; 3.333 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.748 ; 3.748 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.748 ; 3.748 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.754 ; 3.754 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.738 ; 3.738 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.744 ; 3.744 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.754 ; 3.754 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.734 ; 3.734 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.126 ; 3.126 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.419 ; 2.419 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.002 ; 3.002 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.655 ; 2.655 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.665 ; 2.665 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.924 ; 2.924 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.419 ; 2.419 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.655 ; 2.655 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.439 ; 2.439 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.617 ; 2.617 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.016 ; 3.016 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.016 ; 3.016 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.022 ; 3.022 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.006 ; 3.006 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.012 ; 3.012 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.022 ; 3.022 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.002 ; 3.002 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.419 ; 2.419 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Output Disable Times ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 3.054 ; 3.156 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.701 ; 3.803 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.285 ; 3.387 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.295 ; 3.397 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.569 ; 3.671 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.054 ; 3.156 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.285 ; 3.387 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.074 ; 3.176 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.246 ; 3.348 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.716 ; 3.818 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.716 ; 3.818 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.721 ; 3.823 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.706 ; 3.808 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.711 ; 3.813 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.721 ; 3.823 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.701 ; 3.803 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.054 ; 3.156 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.448 ; 2.544 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.069 ; 3.165 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.670 ; 2.766 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.680 ; 2.776 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.942 ; 3.038 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.448 ; 2.544 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.670 ; 2.766 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.468 ; 2.564 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.632 ; 2.728 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.084 ; 3.180 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.084 ; 3.180 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.089 ; 3.185 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.074 ; 3.170 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.079 ; 3.175 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.089 ; 3.185 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.069 ; 3.165 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.448 ; 2.544 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ + + +---------------- +; MTBF Summary ; +---------------- +Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 40 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 11.193 ns + +Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 + + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Worst-Case MTBF (Years) ; Typical MTBF (Years) ; Included in Design MTBF ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.193 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; ; ; ; 6.588 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; ; ; ; 4.605 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.280 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; ; ; ; 7.106 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; ; ; ; 4.174 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.322 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; ; ; ; 7.252 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; ; ; ; 4.070 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.469 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; ; ; ; 6.322 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; ; ; ; 5.147 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.517 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; ; ; ; 6.523 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; ; ; ; 4.994 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.541 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; ; ; ; 6.440 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; ; ; ; 5.101 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.550 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; ; ; ; 7.250 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; ; ; ; 4.300 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.569 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; ; ; ; 6.354 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; ; ; ; 5.215 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.612 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; ; ; ; 6.676 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; ; ; ; 4.936 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.676 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; ; ; ; 6.301 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; ; ; ; 5.375 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.691 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; ; ; ; 6.649 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; ; ; ; 5.042 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.721 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; ; ; ; 6.833 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; ; ; ; 4.888 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.746 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; ; ; ; 6.490 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; ; ; ; 5.256 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.748 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; ; ; ; 6.951 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; ; ; ; 4.797 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.772 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; ; ; ; 6.771 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; ; ; ; 5.001 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.846 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; ; ; ; 7.100 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; ; ; ; 4.746 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.870 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; ; ; ; 7.252 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; ; ; ; 4.618 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.977 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; ; ; ; 6.897 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; ; ; ; 5.080 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.004 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; ; ; ; 7.253 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; ; ; ; 4.751 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.012 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; ; ; ; 6.465 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; ; ; ; 5.547 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.025 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; ; ; ; 6.954 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; ; ; ; 5.071 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.088 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; ; ; ; 6.313 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; ; ; ; 5.775 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.113 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; ; ; ; 7.128 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; ; ; ; 4.985 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.128 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ; ; ; 6.972 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; ; ; ; 5.156 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.139 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; ; ; ; 7.123 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; ; ; ; 5.016 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.160 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; ; ; ; 6.972 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; ; ; ; 5.188 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.202 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; ; ; ; 6.680 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; ; ; ; 5.522 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.258 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; ; ; ; 7.262 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; ; ; ; 4.996 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.267 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; ; ; ; 7.118 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; ; ; ; 5.149 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.273 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; ; ; ; 7.121 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; ; ; ; 5.152 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.287 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; ; ; ; 7.147 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; ; ; ; 5.140 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.360 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; ; ; ; 7.264 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; ; ; ; 5.096 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.365 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; ; ; ; 7.267 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; ; ; ; 5.098 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.415 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; ; ; ; 7.120 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; ; ; ; 5.295 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.429 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; ; ; ; 6.969 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; ; ; ; 5.460 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.446 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ; ; ; 7.120 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; ; ; ; 5.326 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.522 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; ; ; ; 7.108 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; ; ; ; 5.414 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.522 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; ; ; ; 6.797 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; ; ; ; 5.725 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.575 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; ; ; ; 7.126 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; ; ; ; 5.449 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.060 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; ; ; ; 7.265 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; ; ; ; 5.795 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + ++------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Fmax Summary ; ++-----------+-----------------+-----------------------------------------------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+-----------------------------------------------------+------+ +; 186.6 MHz ; 186.6 MHz ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; +; 193.5 MHz ; 193.5 MHz ; CLOCK_50 ; ; ++-----------+-----------------+-----------------------------------------------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup Summary ; ++-----------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+--------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.283 ; -5.821 ; +; CLOCK_50 ; 14.832 ; 0.000 ; ++-----------------------------------------------------+--------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.298 ; 0.000 ; +; CLOCK_50 ; 0.312 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Recovery Summary ; ++-----------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+--------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.835 ; -178.452 ; +; CLOCK_50 ; 13.489 ; 0.000 ; ++-----------------------------------------------------+--------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Removal Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; CLOCK_50 ; 1.418 ; 0.000 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.617 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.739 ; 0.000 ; +; CLOCK_50 ; 9.561 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; -0.283 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 2.101 ; +; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.199 ; 2.057 ; +; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.199 ; 2.057 ; +; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.199 ; 2.057 ; +; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.199 ; 2.057 ; +; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.199 ; 2.057 ; +; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.199 ; 2.057 ; +; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.199 ; 2.057 ; +; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.199 ; 2.057 ; +; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.199 ; 2.057 ; +; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.199 ; 2.057 ; +; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.199 ; 2.057 ; +; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.199 ; 2.057 ; +; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.199 ; 2.057 ; +; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.199 ; 2.057 ; +; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.199 ; 2.057 ; +; -0.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.018 ; +; -0.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.018 ; +; -0.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.018 ; +; -0.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.018 ; +; -0.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.018 ; +; -0.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.018 ; +; -0.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.018 ; +; -0.185 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.199 ; 2.001 ; +; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.840 ; +; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.840 ; +; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.840 ; +; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.840 ; +; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.840 ; +; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.840 ; +; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.840 ; +; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.840 ; +; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.840 ; +; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.840 ; +; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.840 ; +; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.840 ; +; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.840 ; +; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.840 ; +; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.840 ; +; -0.001 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.819 ; +; 0.078 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.879 ; 2.058 ; +; 0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.875 ; 2.056 ; +; 0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.875 ; 2.056 ; +; 0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.875 ; 2.056 ; +; 0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.875 ; 2.056 ; +; 0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.733 ; +; 0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.733 ; +; 0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.733 ; +; 0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.733 ; +; 0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.733 ; +; 0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.733 ; +; 0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.733 ; +; 0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.733 ; +; 0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.733 ; +; 0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.733 ; +; 0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.733 ; +; 0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.733 ; +; 0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.733 ; +; 0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.733 ; +; 0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 1.733 ; +; 0.156 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.979 ; +; 0.156 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.979 ; +; 0.156 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.979 ; +; 0.359 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.899 ; 1.757 ; +; 0.359 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.899 ; 1.757 ; +; 0.359 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.899 ; 1.757 ; +; 0.359 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.899 ; 1.757 ; +; 0.359 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.899 ; 1.757 ; +; 0.359 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.899 ; 1.757 ; +; 0.359 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.899 ; 1.757 ; +; 0.359 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.899 ; 1.757 ; +; 0.359 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.899 ; 1.757 ; +; 0.359 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.899 ; 1.757 ; +; 0.359 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.899 ; 1.757 ; +; 0.359 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.899 ; 1.757 ; +; 0.359 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.899 ; 1.757 ; +; 0.359 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.899 ; 1.757 ; +; 0.359 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.899 ; 1.757 ; +; 0.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.879 ; 1.639 ; +; 0.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.879 ; 1.639 ; +; 0.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.879 ; 1.639 ; +; 2.641 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.372 ; 5.002 ; +; 2.659 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.372 ; 4.984 ; +; 2.683 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.386 ; 4.946 ; +; 2.706 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.386 ; 4.923 ; +; 2.723 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.373 ; 4.919 ; +; 2.723 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.373 ; 4.919 ; +; 2.723 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.373 ; 4.919 ; +; 2.723 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.373 ; 4.919 ; +; 2.723 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.373 ; 4.919 ; +; 2.723 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.373 ; 4.919 ; +; 2.723 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.373 ; 4.919 ; +; 2.733 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.372 ; 4.910 ; +; 2.737 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.374 ; 4.904 ; +; 2.741 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.373 ; 4.901 ; +; 2.741 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.373 ; 4.901 ; +; 2.741 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.373 ; 4.901 ; +; 2.741 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.373 ; 4.901 ; +; 2.741 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.373 ; 4.901 ; +; 2.741 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.373 ; 4.901 ; ++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'CLOCK_50' ; ++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 14.832 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 4.490 ; +; 14.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 4.457 ; +; 15.015 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 4.307 ; +; 15.090 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 4.232 ; +; 15.132 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 4.190 ; +; 15.273 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 4.049 ; +; 15.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 3.948 ; +; 15.429 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 3.893 ; +; 15.476 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 3.846 ; +; 15.552 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 3.770 ; +; 15.601 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 3.721 ; +; 15.629 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 3.693 ; +; 15.701 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 3.621 ; +; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.098 ; +; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.098 ; +; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.098 ; +; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.098 ; +; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.098 ; +; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.098 ; +; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.098 ; +; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.098 ; +; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.098 ; +; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.098 ; +; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.098 ; +; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.098 ; +; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.098 ; +; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.090 ; +; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.090 ; +; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.090 ; +; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.090 ; +; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.090 ; +; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.090 ; +; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.090 ; +; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.090 ; +; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.090 ; +; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.090 ; +; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.090 ; +; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.090 ; +; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.090 ; +; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.019 ; +; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.019 ; +; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.019 ; +; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.019 ; +; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.019 ; +; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.019 ; +; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.019 ; +; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.019 ; +; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.019 ; +; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.019 ; +; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.019 ; +; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.019 ; +; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 4.019 ; +; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.951 ; +; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.951 ; +; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.951 ; +; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.951 ; +; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.951 ; +; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.951 ; +; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.951 ; +; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.951 ; +; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.951 ; +; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.951 ; +; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.951 ; +; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.951 ; +; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.951 ; +; 16.028 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 3.942 ; +; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 3.924 ; +; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 3.924 ; +; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 3.924 ; +; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 3.924 ; +; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 3.924 ; +; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 3.924 ; +; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 3.924 ; +; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 3.924 ; +; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 3.924 ; +; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 3.924 ; +; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 3.924 ; +; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 3.924 ; +; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.051 ; 3.924 ; +; 16.078 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 3.244 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; +; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.052 ; 3.826 ; ++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; 0.298 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 0.511 ; +; 0.298 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.301 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 0.511 ; +; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.315 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.355 ; 0.814 ; +; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.519 ; +; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.519 ; +; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.519 ; +; 0.325 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.338 ; 0.832 ; +; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.538 ; +; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.539 ; +; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.539 ; +; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.336 ; 0.832 ; +; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 0.538 ; +; 0.331 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.336 ; 0.836 ; +; 0.332 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.338 ; 0.839 ; +; 0.333 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.531 ; +; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.537 ; +; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.537 ; +; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_initial ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CS_N[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.537 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.538 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_done ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.538 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.538 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.538 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.538 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.539 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.538 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.538 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.338 ; 0.847 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CAS_N ; DE0_D5M:inst|Sdram_Control_4Port:u7|CAS_N ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|RAS_N ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[16] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[14] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[12] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.341 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.540 ; +; 0.341 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.552 ; +; 0.341 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.540 ; +; 0.341 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.540 ; +; 0.341 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.540 ; +; 0.342 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.541 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.545 ; +; 0.348 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.547 ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'CLOCK_50' ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.312 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.511 ; +; 0.320 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.519 ; +; 0.321 ; ps2:inst6|clk_div[0] ; ps2:inst6|clk_div[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.519 ; +; 0.341 ; DE0_D5M:inst|rClk[0] ; DE0_D5M:inst|rClk[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.519 ; +; 0.341 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.539 ; +; 0.345 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.543 ; +; 0.347 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.546 ; +; 0.364 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.563 ; +; 0.471 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.669 ; +; 0.495 ; ps2:inst6|clk_div[6] ; ps2:inst6|clk_div[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.693 ; +; 0.495 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.694 ; +; 0.498 ; ps2:inst6|clk_div[2] ; ps2:inst6|clk_div[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.696 ; +; 0.498 ; ps2:inst6|clk_div[4] ; ps2:inst6|clk_div[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.696 ; +; 0.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.697 ; +; 0.500 ; ps2:inst6|clk_div[3] ; ps2:inst6|clk_div[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.698 ; +; 0.500 ; ps2:inst6|clk_div[5] ; ps2:inst6|clk_div[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.698 ; +; 0.500 ; ps2:inst6|clk_div[7] ; ps2:inst6|clk_div[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.698 ; +; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.698 ; +; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.698 ; +; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.699 ; +; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.699 ; +; 0.501 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.700 ; +; 0.501 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.700 ; +; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.699 ; +; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.700 ; +; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.700 ; +; 0.502 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.701 ; +; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.701 ; +; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.701 ; +; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.701 ; +; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.701 ; +; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.702 ; +; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.702 ; +; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.702 ; +; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.702 ; +; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.703 ; +; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.703 ; +; 0.505 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.704 ; +; 0.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.703 ; +; 0.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.704 ; +; 0.506 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.704 ; +; 0.511 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.710 ; +; 0.511 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.710 ; +; 0.511 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.710 ; +; 0.511 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.710 ; +; 0.511 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.710 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; ps2:inst6|clk_div[0] ; ps2:inst6|clk_div[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.710 ; +; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.712 ; +; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.712 ; +; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.712 ; +; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.712 ; +; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.712 ; +; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.712 ; +; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.713 ; +; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.713 ; +; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.713 ; +; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.713 ; +; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.713 ; +; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.713 ; +; 0.514 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.713 ; +; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.714 ; +; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.714 ; +; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.714 ; +; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.714 ; +; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.714 ; +; 0.516 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.715 ; +; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.715 ; +; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.715 ; +; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.715 ; +; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.716 ; +; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.716 ; +; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.715 ; +; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.716 ; +; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.716 ; +; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.716 ; +; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.716 ; +; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.716 ; +; 0.521 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.719 ; +; 0.524 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.723 ; +; 0.526 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.725 ; +; 0.529 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.728 ; +; 0.532 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.731 ; +; 0.533 ; ps2:inst6|clk_div[8] ; ps2:inst6|clk_div[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.711 ; +; 0.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.747 ; +; 0.557 ; ps2:inst6|clk_div[7] ; ps2:inst6|clk_div[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.246 ; 0.947 ; +; 0.636 ; ps2:inst6|clk_div[6] ; ps2:inst6|clk_div[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.246 ; 1.026 ; +; 0.637 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.836 ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.815 ; +; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.815 ; +; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.815 ; +; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.815 ; +; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.815 ; +; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.815 ; +; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.815 ; +; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.815 ; +; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.815 ; +; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.815 ; +; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.815 ; +; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.815 ; +; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.815 ; +; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.815 ; +; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.815 ; +; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.978 ; 2.815 ; +; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.976 ; 2.816 ; +; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.976 ; 2.816 ; +; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.976 ; 2.816 ; +; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.976 ; 2.816 ; +; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.976 ; 2.816 ; +; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.976 ; 2.816 ; +; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.976 ; 2.816 ; +; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.976 ; 2.816 ; +; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.976 ; 2.816 ; +; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.976 ; 2.816 ; +; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.976 ; 2.816 ; +; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.976 ; 2.816 ; +; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.976 ; 2.816 ; +; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.976 ; 2.816 ; +; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.976 ; 2.816 ; +; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.976 ; 2.816 ; +; -0.791 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.976 ; 2.855 ; +; -0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.974 ; 2.856 ; +; -0.694 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.214 ; 2.495 ; +; -0.694 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.214 ; 2.495 ; +; -0.694 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.214 ; 2.495 ; +; -0.694 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.214 ; 2.495 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.205 ; 2.494 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.205 ; 2.494 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.205 ; 2.494 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.205 ; 2.494 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.205 ; 2.494 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.205 ; 2.494 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.206 ; 2.493 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.205 ; 2.494 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.206 ; 2.493 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.206 ; 2.493 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.205 ; 2.494 ; +; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.205 ; 2.494 ; +; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.205 ; 2.493 ; +; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.205 ; 2.493 ; +; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.205 ; 2.493 ; +; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.205 ; 2.493 ; +; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.205 ; 2.493 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 2.499 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 2.499 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 2.499 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 2.499 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 2.499 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 2.499 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 2.499 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 2.499 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.204 ; 2.492 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.212 ; 2.484 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 2.499 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 2.499 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 2.499 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 2.499 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 2.499 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.198 ; 2.498 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 2.498 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 2.498 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.197 ; 2.498 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.195 ; 2.500 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.195 ; 2.500 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.195 ; 2.500 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.195 ; 2.500 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.195 ; 2.500 ; +; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.195 ; 2.500 ; ++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Recovery: 'CLOCK_50' ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 13.489 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.692 ; 5.834 ; +; 13.498 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.692 ; 5.825 ; +; 13.578 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.692 ; 5.745 ; +; 13.635 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 5.687 ; +; 13.705 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.692 ; 5.618 ; +; 13.760 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 5.562 ; +; 13.760 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 5.562 ; +; 13.769 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 5.553 ; +; 13.837 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 5.485 ; +; 13.848 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 5.474 ; +; 13.962 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 5.360 ; +; 13.967 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 5.355 ; +; 13.971 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 5.351 ; +; 13.974 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 5.348 ; +; 14.048 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 5.274 ; +; 14.178 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.693 ; 5.144 ; +; 14.568 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.692 ; 4.755 ; +; 14.622 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.698 ; 4.695 ; +; 14.673 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.692 ; 4.650 ; +; 14.834 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.692 ; 4.489 ; +; 14.842 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.692 ; 4.481 ; +; 14.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.692 ; 4.449 ; +; 14.923 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.692 ; 4.400 ; +; 14.969 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.692 ; 4.354 ; +; 15.048 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.692 ; 4.275 ; +; 15.124 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.692 ; 4.199 ; +; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.234 ; +; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.234 ; +; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.234 ; +; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.234 ; +; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.234 ; +; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.234 ; +; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.234 ; +; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.234 ; +; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.234 ; +; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.234 ; +; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.234 ; +; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.234 ; +; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.234 ; +; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.234 ; +; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.234 ; +; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.234 ; +; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.225 ; +; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.225 ; +; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.225 ; +; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.225 ; +; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.225 ; +; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.225 ; +; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.225 ; +; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.225 ; +; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.225 ; +; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.225 ; +; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.225 ; +; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.225 ; +; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.225 ; +; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.225 ; +; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.225 ; +; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.225 ; +; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.145 ; +; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.145 ; +; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.145 ; +; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.145 ; +; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.145 ; +; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.145 ; +; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.145 ; +; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.145 ; +; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.145 ; +; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.145 ; +; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.145 ; +; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.145 ; +; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.145 ; +; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.145 ; +; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.145 ; +; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.145 ; +; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.087 ; +; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.087 ; +; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.087 ; +; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.087 ; +; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.087 ; +; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.087 ; +; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.087 ; +; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.087 ; +; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.087 ; +; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.087 ; +; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.087 ; +; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.087 ; +; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.087 ; +; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.087 ; +; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.087 ; +; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.087 ; +; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.018 ; +; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.018 ; +; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.018 ; +; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.018 ; +; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.018 ; +; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.018 ; +; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.018 ; +; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.018 ; +; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.018 ; +; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.018 ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Removal: 'CLOCK_50' ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.618 ; +; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.618 ; +; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.618 ; +; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.618 ; +; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.618 ; +; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.618 ; +; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.618 ; +; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.618 ; +; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.618 ; +; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.618 ; +; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.618 ; +; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.618 ; +; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.618 ; +; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.618 ; +; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.618 ; +; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.618 ; +; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.688 ; +; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.688 ; +; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.688 ; +; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.688 ; +; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.688 ; +; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.688 ; +; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.688 ; +; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.688 ; +; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.688 ; +; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.688 ; +; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.688 ; +; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.688 ; +; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.688 ; +; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.688 ; +; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.688 ; +; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 1.688 ; +; 1.948 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 2.153 ; +; 1.948 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 2.153 ; +; 1.948 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 2.153 ; +; 1.948 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 2.153 ; +; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.168 ; +; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.168 ; +; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.168 ; +; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.168 ; +; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.168 ; +; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.168 ; +; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.168 ; +; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.168 ; +; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.168 ; +; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.168 ; +; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.168 ; +; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.168 ; +; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 2.168 ; +; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.432 ; +; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.432 ; +; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.432 ; +; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.432 ; +; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.432 ; +; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.432 ; +; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.432 ; +; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.432 ; +; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.432 ; +; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.432 ; +; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.432 ; +; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.432 ; +; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.433 ; +; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.433 ; +; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.433 ; +; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.433 ; +; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.433 ; +; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.433 ; +; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.433 ; +; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.433 ; +; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.433 ; +; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.433 ; +; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.433 ; +; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.433 ; +; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.433 ; +; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.433 ; +; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.433 ; +; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.433 ; +; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.448 ; +; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.448 ; +; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.448 ; +; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.448 ; +; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.448 ; +; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.448 ; +; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.448 ; +; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.448 ; +; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.448 ; +; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.448 ; +; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.448 ; +; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.448 ; +; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.448 ; +; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.448 ; +; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.448 ; +; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.448 ; +; 2.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.538 ; +; 2.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.538 ; +; 2.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.538 ; +; 2.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.538 ; +; 2.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.538 ; +; 2.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.538 ; +; 2.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.056 ; 2.538 ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; 3.617 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.427 ; 2.334 ; +; 3.627 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.436 ; 2.335 ; +; 3.637 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.327 ; +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.441 ; 2.341 ; +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.441 ; 2.341 ; +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.441 ; 2.341 ; +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.441 ; 2.341 ; +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.441 ; 2.341 ; +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.441 ; 2.341 ; +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.441 ; 2.341 ; +; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.331 ; +; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.331 ; +; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.447 ; 2.336 ; +; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.447 ; 2.336 ; +; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.331 ; +; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.331 ; +; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.331 ; +; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.331 ; +; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.331 ; +; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.331 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.338 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.338 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.338 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.338 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.448 ; 2.336 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.448 ; 2.336 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.448 ; 2.336 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.448 ; 2.336 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.448 ; 2.336 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.448 ; 2.336 ; +; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.448 ; 2.336 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.445 ; 2.340 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.445 ; 2.340 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.445 ; 2.340 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.454 ; 2.331 ; +; 3.653 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.457 ; 2.340 ; +; 3.653 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.457 ; 2.340 ; +; 3.653 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.457 ; 2.340 ; +; 3.653 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.457 ; 2.340 ; +; 3.653 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.457 ; 2.340 ; +; 3.653 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.457 ; 2.340 ; +; 3.653 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.457 ; 2.340 ; +; 3.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.480 ; 2.327 ; +; 3.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.480 ; 2.327 ; +; 3.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.480 ; 2.327 ; +; 3.667 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.481 ; 2.330 ; +; 3.667 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.481 ; 2.330 ; +; 3.667 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.481 ; 2.330 ; +; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.473 ; 2.339 ; +; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.473 ; 2.339 ; +; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.473 ; 2.339 ; +; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.473 ; 2.339 ; +; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.473 ; 2.339 ; +; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.473 ; 2.339 ; +; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.473 ; 2.339 ; +; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.473 ; 2.339 ; +; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.473 ; 2.339 ; +; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.473 ; 2.339 ; +; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.470 ; 2.343 ; +; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.470 ; 2.343 ; +; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.470 ; 2.343 ; +; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.470 ; 2.343 ; +; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.476 ; 2.337 ; +; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.476 ; 2.337 ; +; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.476 ; 2.337 ; +; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.476 ; 2.337 ; +; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.476 ; 2.337 ; +; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.470 ; 2.343 ; +; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.470 ; 2.343 ; +; 3.671 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.481 ; 2.334 ; +; 3.671 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.481 ; 2.334 ; +; 3.671 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.481 ; 2.334 ; +; 3.671 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.481 ; 2.334 ; +; 3.671 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.481 ; 2.334 ; +; 3.671 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.481 ; 2.334 ; +; 3.671 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.481 ; 2.334 ; +; 3.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.479 ; 2.338 ; +; 3.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.479 ; 2.338 ; +; 3.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.479 ; 2.338 ; +; 3.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.479 ; 2.338 ; +; 3.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.479 ; 2.338 ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 3.739 ; 3.955 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; 3.739 ; 3.955 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; 3.739 ; 3.955 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; 3.739 ; 3.955 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; 3.739 ; 3.955 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; 3.740 ; 3.970 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; +; 3.740 ; 3.970 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; +; 3.741 ; 3.971 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; +; 3.741 ; 3.971 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; 3.742 ; 3.958 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; +; 3.742 ; 3.958 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; 3.742 ; 3.958 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; +; 3.742 ; 3.958 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; +; 3.742 ; 3.958 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; +; 3.742 ; 3.958 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; +; 3.742 ; 3.958 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; +; 3.742 ; 3.958 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; +; 3.742 ; 3.958 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; +; 3.742 ; 3.958 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; +; 3.742 ; 3.972 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0 ; +; 3.742 ; 3.958 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; 3.742 ; 3.958 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; 3.742 ; 3.958 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; 3.743 ; 3.973 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0 ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[0] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[13] ; +; 3.750 ; 3.966 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; 3.750 ; 3.966 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; 3.750 ; 3.966 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ; ++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+ +; 9.561 ; 9.745 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; +; 9.584 ; 9.768 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|rClk[0] ; +; 9.584 ; 9.768 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[8] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[0] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[1] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[2] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[3] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[4] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[5] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[6] ; +; 9.587 ; 9.771 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[7] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; ++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; 3.696 ; 4.224 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; 3.696 ; 4.224 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; 3.167 ; 3.642 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; 3.754 ; 4.201 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.172 ; 3.670 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.318 ; 3.772 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.273 ; 3.722 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.502 ; 3.956 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.251 ; 3.690 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.149 ; 3.584 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.474 ; 3.928 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.005 ; 3.435 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.146 ; 3.592 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.188 ; 3.625 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.184 ; 3.626 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.899 ; 3.344 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.171 ; 3.606 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.089 ; 3.553 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.754 ; 4.201 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; -1.554 ; -2.058 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; -1.554 ; -2.072 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; -1.633 ; -2.058 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; -2.286 ; -2.717 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; -2.551 ; -3.034 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; -2.724 ; -3.169 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; -2.682 ; -3.122 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; -2.902 ; -3.347 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; -2.623 ; -3.050 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; -2.551 ; -2.973 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; -2.875 ; -3.321 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; -2.387 ; -2.805 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; -2.535 ; -2.972 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; -2.590 ; -3.013 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; -2.586 ; -3.014 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; -2.286 ; -2.717 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; -2.573 ; -2.995 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; -2.473 ; -2.921 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; -3.144 ; -3.582 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 7.443 ; 7.283 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 5.824 ; 5.753 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 7.443 ; 7.283 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 6.089 ; 5.925 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 6.089 ; 5.925 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 5.055 ; 5.138 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 3.447 ; 3.308 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 3.257 ; 3.115 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 3.414 ; 3.253 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 3.413 ; 3.264 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 3.225 ; 3.093 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 3.268 ; 3.137 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 3.008 ; 2.891 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 3.073 ; 2.949 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 3.447 ; 3.308 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 3.235 ; 3.084 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 3.429 ; 3.275 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 3.048 ; 2.930 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 3.030 ; 2.910 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 3.035 ; 2.917 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 3.038 ; 2.923 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 3.004 ; 2.884 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 3.343 ; 3.182 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 6.693 ; 6.389 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 4.860 ; 4.672 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 4.972 ; 4.764 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 5.039 ; 4.844 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 6.693 ; 6.389 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 5.204 ; 5.004 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 5.033 ; 4.836 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 5.159 ; 4.973 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 5.378 ; 5.243 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 4.992 ; 4.867 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 4.674 ; 4.602 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 4.892 ; 4.717 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 4.613 ; 4.514 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 4.770 ; 4.635 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 4.877 ; 4.758 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 4.802 ; 4.627 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 5.131 ; 4.996 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 3.240 ; 3.114 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 3.182 ; 3.050 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 3.559 ; 3.430 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 5.236 ; 4.872 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -0.448 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -0.595 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 5.693 ; 5.620 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 5.693 ; 5.620 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 7.249 ; 7.089 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 5.947 ; 5.785 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 5.947 ; 5.785 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 4.950 ; 5.034 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 2.638 ; 2.521 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 2.877 ; 2.736 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 3.029 ; 2.869 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 3.028 ; 2.879 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 2.847 ; 2.715 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 2.889 ; 2.758 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 2.638 ; 2.521 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 2.701 ; 2.577 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 3.060 ; 2.921 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 2.855 ; 2.706 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 3.043 ; 2.890 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 2.677 ; 2.559 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 2.659 ; 2.539 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 2.664 ; 2.546 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 2.667 ; 2.552 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 2.633 ; 2.513 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 2.958 ; 2.799 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 3.638 ; 3.475 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.638 ; 3.475 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.906 ; 3.762 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.983 ; 3.854 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 5.728 ; 5.385 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 4.132 ; 3.977 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.973 ; 3.834 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.934 ; 3.769 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 4.127 ; 3.977 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.846 ; 3.735 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.653 ; 3.504 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.944 ; 3.805 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.798 ; 3.689 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.773 ; 3.639 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 4.117 ; 4.001 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.754 ; 3.577 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 4.087 ; 3.895 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 2.860 ; 2.733 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 2.804 ; 2.673 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 3.166 ; 3.037 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 4.857 ; 4.494 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -0.777 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -0.922 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; SW[4] ; VGA_B[0] ; 8.165 ; 7.985 ; 8.668 ; 8.488 ; +; SW[4] ; VGA_B[1] ; 8.501 ; 8.282 ; 8.985 ; 8.720 ; +; SW[4] ; VGA_B[2] ; 7.664 ; 7.519 ; 8.155 ; 8.015 ; +; SW[4] ; VGA_B[3] ; 7.757 ; 7.589 ; 8.277 ; 8.109 ; +; SW[4] ; VGA_G[0] ; 8.739 ; 8.624 ; 9.277 ; 9.079 ; +; SW[4] ; VGA_G[1] ; 7.921 ; 7.834 ; 8.446 ; 8.359 ; +; SW[4] ; VGA_G[2] ; 8.245 ; 8.097 ; 8.740 ; 8.523 ; +; SW[4] ; VGA_G[3] ; 8.251 ; 8.079 ; 8.757 ; 8.603 ; +; SW[4] ; VGA_R[0] ; 9.036 ; 8.850 ; 9.540 ; 9.374 ; +; SW[4] ; VGA_R[1] ; 8.457 ; 8.277 ; 8.940 ; 8.729 ; +; SW[4] ; VGA_R[2] ; 8.062 ; 7.851 ; 8.524 ; 8.321 ; +; SW[4] ; VGA_R[3] ; 7.892 ; 7.767 ; 8.411 ; 8.286 ; +; SW[5] ; VGA_B[0] ; 7.839 ; 7.659 ; 8.328 ; 8.148 ; +; SW[5] ; VGA_B[1] ; 7.920 ; 7.697 ; 8.375 ; 8.144 ; +; SW[5] ; VGA_B[2] ; 7.552 ; 7.412 ; 8.017 ; 7.853 ; +; SW[5] ; VGA_B[3] ; 7.427 ; 7.259 ; 7.937 ; 7.769 ; +; SW[5] ; VGA_G[0] ; 8.203 ; 8.047 ; 8.677 ; 8.513 ; +; SW[5] ; VGA_G[1] ; 7.592 ; 7.505 ; 8.070 ; 7.983 ; +; SW[5] ; VGA_G[2] ; 7.739 ; 7.564 ; 8.209 ; 8.026 ; +; SW[5] ; VGA_G[3] ; 7.925 ; 7.751 ; 8.416 ; 8.262 ; +; SW[5] ; VGA_R[0] ; 8.705 ; 8.521 ; 9.166 ; 9.000 ; +; SW[5] ; VGA_R[1] ; 7.877 ; 7.695 ; 8.329 ; 8.139 ; +; SW[5] ; VGA_R[2] ; 7.525 ; 7.317 ; 7.989 ; 7.786 ; +; SW[5] ; VGA_R[3] ; 7.670 ; 7.563 ; 8.211 ; 8.086 ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; SW[4] ; VGA_B[0] ; 7.911 ; 7.732 ; 8.368 ; 8.183 ; +; SW[4] ; VGA_B[1] ; 7.735 ; 7.516 ; 8.240 ; 7.972 ; +; SW[4] ; VGA_B[2] ; 7.468 ; 7.300 ; 7.925 ; 7.757 ; +; SW[4] ; VGA_B[3] ; 7.262 ; 7.095 ; 7.728 ; 7.596 ; +; SW[4] ; VGA_G[0] ; 8.400 ; 8.242 ; 8.918 ; 8.731 ; +; SW[4] ; VGA_G[1] ; 7.023 ; 6.887 ; 7.502 ; 7.360 ; +; SW[4] ; VGA_G[2] ; 7.912 ; 7.722 ; 8.414 ; 8.213 ; +; SW[4] ; VGA_G[3] ; 7.228 ; 7.085 ; 7.743 ; 7.540 ; +; SW[4] ; VGA_R[0] ; 8.688 ; 8.528 ; 9.168 ; 8.979 ; +; SW[4] ; VGA_R[1] ; 7.633 ; 7.426 ; 8.112 ; 7.899 ; +; SW[4] ; VGA_R[2] ; 7.764 ; 7.564 ; 8.237 ; 8.031 ; +; SW[4] ; VGA_R[3] ; 7.272 ; 7.212 ; 7.816 ; 7.625 ; +; SW[5] ; VGA_B[0] ; 6.968 ; 6.787 ; 7.407 ; 7.254 ; +; SW[5] ; VGA_B[1] ; 7.675 ; 7.441 ; 8.120 ; 7.880 ; +; SW[5] ; VGA_B[2] ; 6.912 ; 6.808 ; 7.420 ; 7.238 ; +; SW[5] ; VGA_B[3] ; 7.184 ; 7.024 ; 7.673 ; 7.507 ; +; SW[5] ; VGA_G[0] ; 7.004 ; 6.819 ; 7.445 ; 7.289 ; +; SW[5] ; VGA_G[1] ; 7.305 ; 7.189 ; 7.799 ; 7.635 ; +; SW[5] ; VGA_G[2] ; 7.064 ; 6.849 ; 7.525 ; 7.304 ; +; SW[5] ; VGA_G[3] ; 7.637 ; 7.490 ; 8.116 ; 7.920 ; +; SW[5] ; VGA_R[0] ; 7.154 ; 6.967 ; 7.597 ; 7.439 ; +; SW[5] ; VGA_R[1] ; 7.675 ; 7.468 ; 8.112 ; 7.911 ; +; SW[5] ; VGA_R[2] ; 7.264 ; 7.057 ; 7.706 ; 7.553 ; +; SW[5] ; VGA_R[3] ; 7.371 ; 7.295 ; 7.858 ; 7.747 ; ++------------+-------------+-------+-------+-------+-------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Output Enable Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 3.088 ; 3.075 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.649 ; 3.636 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.313 ; 3.300 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.323 ; 3.310 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.567 ; 3.554 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.088 ; 3.075 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.313 ; 3.300 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.108 ; 3.095 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.282 ; 3.269 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.663 ; 3.650 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.663 ; 3.650 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.669 ; 3.656 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.653 ; 3.640 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.659 ; 3.646 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.669 ; 3.656 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.649 ; 3.636 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.088 ; 3.075 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.221 ; 2.221 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.760 ; 2.760 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.437 ; 2.437 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.447 ; 2.447 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.682 ; 2.682 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.221 ; 2.221 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.437 ; 2.437 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.241 ; 2.241 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.408 ; 2.408 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.775 ; 2.775 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.775 ; 2.775 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.780 ; 2.780 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.765 ; 2.765 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.770 ; 2.770 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.780 ; 2.780 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.760 ; 2.760 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.221 ; 2.221 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Output Disable Times ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 3.096 ; 3.096 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.676 ; 3.676 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.303 ; 3.303 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.313 ; 3.313 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.553 ; 3.553 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.096 ; 3.096 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.303 ; 3.303 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.116 ; 3.116 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.263 ; 3.263 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.688 ; 3.688 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.688 ; 3.688 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.696 ; 3.696 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.678 ; 3.678 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.686 ; 3.686 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.696 ; 3.696 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.676 ; 3.676 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.096 ; 3.096 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.229 ; 2.417 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.786 ; 2.974 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.428 ; 2.616 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.438 ; 2.626 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.668 ; 2.856 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.229 ; 2.417 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.428 ; 2.616 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.249 ; 2.437 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.390 ; 2.578 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.798 ; 2.986 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.798 ; 2.986 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.806 ; 2.994 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.788 ; 2.976 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.796 ; 2.984 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.806 ; 2.994 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.786 ; 2.974 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.229 ; 2.417 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ + + +---------------- +; MTBF Summary ; +---------------- +Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 40 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 11.719 ns + +Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 + + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Worst-Case MTBF (Years) ; Typical MTBF (Years) ; Included in Design MTBF ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.719 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; ; ; ; 6.738 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; ; ; ; 4.981 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.770 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; ; ; ; 7.197 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; ; ; ; 4.573 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.810 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; ; ; ; 7.337 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; ; ; ; 4.473 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.947 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; ; ; ; 6.501 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; ; ; ; 5.446 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.997 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; ; ; ; 6.603 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; ; ; ; 5.394 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.009 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; ; ; ; 6.687 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; ; ; ; 5.322 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.012 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; ; ; ; 7.336 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; ; ; ; 4.676 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.042 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; ; ; ; 6.525 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; ; ; ; 5.517 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.055 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; ; ; ; 6.814 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; ; ; ; 5.241 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.120 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; ; ; ; 6.470 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; ; ; ; 5.650 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.160 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; ; ; ; 6.963 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; ; ; ; 5.197 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.161 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; ; ; ; 6.794 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; ; ; ; 5.367 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.183 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; ; ; ; 7.060 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; ; ; ; 5.123 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.207 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; ; ; ; 6.659 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; ; ; ; 5.548 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.239 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; ; ; ; 6.911 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; ; ; ; 5.328 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.273 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; ; ; ; 7.337 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; ; ; ; 4.936 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.276 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; ; ; ; 7.200 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; ; ; ; 5.076 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.375 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; ; ; ; 7.023 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; ; ; ; 5.352 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.410 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; ; ; ; 6.634 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; ; ; ; 5.776 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.420 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; ; ; ; 7.339 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; ; ; ; 5.081 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.428 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; ; ; ; 7.062 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; ; ; ; 5.366 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.490 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; ; ; ; 6.469 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; ; ; ; 6.021 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.534 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ; ; ; 7.079 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; ; ; ; 5.455 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.542 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; ; ; ; 7.233 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; ; ; ; 5.309 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.548 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; ; ; ; 7.213 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; ; ; ; 5.335 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.570 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; ; ; ; 7.080 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; ; ; ; 5.490 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.576 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; ; ; ; 6.818 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; ; ; ; 5.758 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.658 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; ; ; ; 7.209 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; ; ; ; 5.449 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.661 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; ; ; ; 7.211 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; ; ; ; 5.450 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.672 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; ; ; ; 7.347 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; ; ; ; 5.325 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.692 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; ; ; ; 7.246 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; ; ; ; 5.446 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.732 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; ; ; ; 7.348 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; ; ; ; 5.384 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.747 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; ; ; ; 7.351 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; ; ; ; 5.396 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.783 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; ; ; ; 7.210 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; ; ; ; 5.573 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.802 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; ; ; ; 7.077 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; ; ; ; 5.725 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.830 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ; ; ; 7.212 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; ; ; ; 5.618 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.894 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; ; ; ; 6.935 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; ; ; ; 5.959 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.898 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; ; ; ; 7.216 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; ; ; ; 5.682 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.903 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; ; ; ; 7.223 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; ; ; ; 5.680 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.346 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; ; ; ; 7.349 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; ; ; ; 5.997 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + ++------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup Summary ; ++-----------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+--------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 1.209 ; 0.000 ; +; CLOCK_50 ; 16.656 ; 0.000 ; ++-----------------------------------------------------+--------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.169 ; 0.000 ; +; CLOCK_50 ; 0.187 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Recovery Summary ; ++-----------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+--------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.780 ; 0.000 ; +; CLOCK_50 ; 15.649 ; 0.000 ; ++-----------------------------------------------------+--------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Removal Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; CLOCK_50 ; 0.849 ; 0.000 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 2.409 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.746 ; 0.000 ; +; CLOCK_50 ; 9.266 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; 1.209 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.305 ; +; 1.257 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.255 ; +; 1.257 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.255 ; +; 1.257 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.255 ; +; 1.257 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.255 ; +; 1.257 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.255 ; +; 1.257 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.255 ; +; 1.257 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.255 ; +; 1.269 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.243 ; +; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.242 ; +; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.242 ; +; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.242 ; +; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.242 ; +; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.242 ; +; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.242 ; +; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.242 ; +; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.242 ; +; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.242 ; +; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.242 ; +; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.242 ; +; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.242 ; +; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.242 ; +; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.242 ; +; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.495 ; 1.242 ; +; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.124 ; +; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.124 ; +; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.124 ; +; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.124 ; +; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.124 ; +; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.124 ; +; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.124 ; +; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.124 ; +; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.124 ; +; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.124 ; +; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.124 ; +; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.124 ; +; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.124 ; +; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.124 ; +; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.124 ; +; 1.403 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.110 ; +; 1.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.276 ; +; 1.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.302 ; 1.272 ; +; 1.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.302 ; 1.272 ; +; 1.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.302 ; 1.272 ; +; 1.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.302 ; 1.272 ; +; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.018 ; +; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.018 ; +; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.018 ; +; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.018 ; +; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.018 ; +; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.018 ; +; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.018 ; +; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.018 ; +; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.018 ; +; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.018 ; +; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.018 ; +; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.018 ; +; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.018 ; +; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.018 ; +; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.018 ; +; 1.527 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.174 ; +; 1.527 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.174 ; +; 1.527 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.174 ; +; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.079 ; +; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.079 ; +; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.079 ; +; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.079 ; +; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.079 ; +; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.079 ; +; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.079 ; +; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.079 ; +; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.079 ; +; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.079 ; +; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.079 ; +; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.079 ; +; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.079 ; +; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.079 ; +; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.079 ; +; 1.714 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 0.988 ; +; 1.714 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 0.988 ; +; 1.714 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 0.988 ; +; 4.524 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.232 ; 3.251 ; +; 4.537 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.232 ; 3.238 ; +; 4.575 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.232 ; 3.200 ; +; 4.597 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.232 ; 3.178 ; +; 4.618 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.218 ; 3.171 ; +; 4.623 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.036 ; 3.348 ; +; 4.629 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.038 ; 3.340 ; +; 4.636 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.036 ; 3.335 ; +; 4.642 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.038 ; 3.327 ; +; 4.653 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.220 ; 3.134 ; +; 4.653 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.220 ; 3.134 ; +; 4.653 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.220 ; 3.134 ; +; 4.653 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.220 ; 3.134 ; +; 4.653 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.220 ; 3.134 ; +; 4.653 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.220 ; 3.134 ; +; 4.653 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.220 ; 3.134 ; +; 4.661 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.220 ; 3.126 ; +; 4.674 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.036 ; 3.297 ; +; 4.680 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.038 ; 3.289 ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'CLOCK_50' ; ++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 16.656 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 2.859 ; +; 16.664 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 2.851 ; +; 16.767 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 2.748 ; +; 16.789 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 2.726 ; +; 16.805 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 2.710 ; +; 16.879 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 2.636 ; +; 16.944 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 2.571 ; +; 16.975 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 2.540 ; +; 17.015 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 2.500 ; +; 17.044 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 2.471 ; +; 17.081 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 2.434 ; +; 17.098 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 2.417 ; +; 17.133 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 2.382 ; +; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.030 ; 2.684 ; +; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.622 ; +; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.622 ; +; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.622 ; +; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.622 ; +; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.622 ; +; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.622 ; +; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.622 ; +; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.622 ; +; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.622 ; +; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.622 ; +; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.622 ; +; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.622 ; +; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.622 ; +; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.619 ; +; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.619 ; +; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.619 ; +; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.619 ; +; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.619 ; +; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.619 ; +; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.619 ; +; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.619 ; +; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.619 ; +; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.619 ; +; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.619 ; +; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.619 ; +; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.619 ; +; 17.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 2.157 ; +; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.557 ; +; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.557 ; +; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.557 ; +; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.557 ; +; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.557 ; +; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.557 ; +; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.557 ; +; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.557 ; +; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.557 ; +; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.557 ; +; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.557 ; +; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.557 ; +; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.557 ; +; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.512 ; +; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.512 ; +; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.512 ; +; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.512 ; +; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.512 ; +; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.512 ; +; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.512 ; +; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.512 ; +; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.512 ; +; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.512 ; +; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.512 ; +; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.512 ; +; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.512 ; +; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.484 ; +; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.484 ; +; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.484 ; +; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.484 ; +; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.484 ; +; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.484 ; +; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.484 ; +; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.484 ; +; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.484 ; +; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.484 ; +; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.484 ; +; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.484 ; +; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 2.484 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; +; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.033 ; 2.430 ; ++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; 0.169 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.215 ; 0.468 ; +; 0.172 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.218 ; 0.494 ; +; 0.174 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.497 ; +; 0.174 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.218 ; 0.496 ; +; 0.176 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.499 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.186 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.509 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.314 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.315 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.314 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.315 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.193 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.313 ; +; 0.193 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.313 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[16] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[14] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_done ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.315 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.315 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CAS_N ; DE0_D5M:inst|Sdram_Control_4Port:u7|CAS_N ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|RAS_N ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.315 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.315 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.315 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.196 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[12] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.316 ; +; 0.196 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.316 ; +; 0.197 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.316 ; +; 0.197 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.316 ; +; 0.197 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.316 ; +; 0.198 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.317 ; +; 0.202 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.321 ; +; 0.202 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.329 ; +; 0.203 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_initial ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CS_N[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.322 ; +; 0.204 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.324 ; +; 0.205 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_done ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.325 ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'CLOCK_50' ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.187 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.307 ; +; 0.194 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; ps2:inst6|clk_div[0] ; ps2:inst6|clk_div[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.314 ; +; 0.197 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.316 ; +; 0.199 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.318 ; +; 0.206 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.325 ; +; 0.208 ; DE0_D5M:inst|rClk[0] ; DE0_D5M:inst|rClk[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.022 ; 0.314 ; +; 0.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.336 ; +; 0.272 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.391 ; +; 0.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.413 ; +; 0.294 ; ps2:inst6|clk_div[6] ; ps2:inst6|clk_div[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.414 ; +; 0.295 ; ps2:inst6|clk_div[2] ; ps2:inst6|clk_div[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.415 ; +; 0.295 ; ps2:inst6|clk_div[4] ; ps2:inst6|clk_div[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.415 ; +; 0.296 ; ps2:inst6|clk_div[3] ; ps2:inst6|clk_div[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.416 ; +; 0.296 ; ps2:inst6|clk_div[5] ; ps2:inst6|clk_div[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.416 ; +; 0.296 ; ps2:inst6|clk_div[7] ; ps2:inst6|clk_div[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.416 ; +; 0.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.416 ; +; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.417 ; +; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.417 ; +; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.418 ; +; 0.299 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.418 ; +; 0.299 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.418 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.418 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.418 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.418 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.418 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.418 ; +; 0.300 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.419 ; +; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.419 ; +; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.419 ; +; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.419 ; +; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.419 ; +; 0.301 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.420 ; +; 0.301 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.420 ; +; 0.301 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.420 ; +; 0.302 ; ps2:inst6|clk_div[0] ; ps2:inst6|clk_div[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.422 ; +; 0.304 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.424 ; +; 0.304 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.424 ; +; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.308 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.427 ; +; 0.308 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.427 ; +; 0.308 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.427 ; +; 0.308 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.427 ; +; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.428 ; +; 0.309 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.428 ; +; 0.311 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.430 ; +; 0.311 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.431 ; +; 0.315 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.435 ; +; 0.315 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.435 ; +; 0.318 ; ps2:inst6|clk_div[8] ; ps2:inst6|clk_div[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.022 ; 0.424 ; +; 0.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.438 ; +; 0.327 ; ps2:inst6|clk_div[7] ; ps2:inst6|clk_div[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.163 ; 0.574 ; +; 0.329 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.449 ; +; 0.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.487 ; +; 0.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.488 ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.353 ; 1.842 ; +; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.353 ; 1.842 ; +; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.353 ; 1.842 ; +; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.353 ; 1.842 ; +; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.353 ; 1.842 ; +; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.353 ; 1.842 ; +; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.353 ; 1.842 ; +; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.353 ; 1.842 ; +; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.353 ; 1.842 ; +; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.353 ; 1.842 ; +; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.353 ; 1.842 ; +; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.353 ; 1.842 ; +; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.353 ; 1.842 ; +; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.353 ; 1.842 ; +; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.353 ; 1.842 ; +; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.353 ; 1.842 ; +; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.840 ; +; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.840 ; +; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.840 ; +; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.840 ; +; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.840 ; +; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.840 ; +; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.840 ; +; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.840 ; +; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.840 ; +; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.840 ; +; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.840 ; +; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.840 ; +; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.840 ; +; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.840 ; +; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.840 ; +; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.840 ; +; 0.816 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.353 ; 1.860 ; +; 0.817 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.354 ; 1.858 ; +; 0.852 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.504 ; 1.651 ; +; 0.852 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.504 ; 1.651 ; +; 0.852 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.504 ; 1.651 ; +; 0.852 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.504 ; 1.651 ; +; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.649 ; +; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.649 ; +; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.649 ; +; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.649 ; +; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.649 ; +; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.649 ; +; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.648 ; +; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.649 ; +; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.648 ; +; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.502 ; 1.648 ; +; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.649 ; +; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.649 ; +; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.648 ; +; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.648 ; +; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.648 ; +; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.648 ; +; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.648 ; +; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.506 ; 1.643 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.654 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.654 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.654 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.654 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.654 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.654 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.654 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.654 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.654 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.654 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.654 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.654 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.654 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.493 ; 1.654 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; +; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.494 ; 1.653 ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Recovery: 'CLOCK_50' ; ++--------+-------------------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.491 ; 3.867 ; +; 15.652 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.491 ; 3.864 ; +; 15.714 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.491 ; 3.802 ; +; 15.758 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 3.757 ; +; 15.787 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.491 ; 3.729 ; +; 15.840 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 3.675 ; +; 15.840 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 3.675 ; +; 15.843 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 3.672 ; +; 15.900 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 3.615 ; +; 15.905 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 3.610 ; +; 15.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 3.545 ; +; 15.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 3.542 ; +; 15.975 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 3.540 ; +; 15.978 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 3.537 ; +; 16.034 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 3.481 ; +; 16.109 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.492 ; 3.406 ; +; 16.404 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.491 ; 3.112 ; +; 16.447 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.491 ; 3.069 ; +; 16.450 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.496 ; 3.061 ; +; 16.538 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.491 ; 2.978 ; +; 16.541 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.491 ; 2.975 ; +; 16.578 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.491 ; 2.938 ; +; 16.604 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.491 ; 2.912 ; +; 16.635 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.491 ; 2.881 ; +; 16.676 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.491 ; 2.840 ; +; 16.757 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.491 ; 2.759 ; +; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.719 ; +; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.719 ; +; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.719 ; +; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.719 ; +; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.719 ; +; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.719 ; +; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.719 ; +; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.719 ; +; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.719 ; +; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.719 ; +; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.719 ; +; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.719 ; +; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.719 ; +; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.719 ; +; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.719 ; +; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.719 ; +; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.716 ; +; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.716 ; +; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.716 ; +; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.716 ; +; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.716 ; +; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.716 ; +; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.716 ; +; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.716 ; +; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.716 ; +; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.716 ; +; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.716 ; +; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.716 ; +; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.716 ; +; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.716 ; +; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.716 ; +; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.716 ; +; 17.258 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.490 ; 2.259 ; +; 17.275 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.490 ; 2.242 ; +; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.654 ; +; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.654 ; +; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.654 ; +; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.654 ; +; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.654 ; +; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.654 ; +; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.654 ; +; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.654 ; +; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.654 ; +; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.654 ; +; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.654 ; +; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.654 ; +; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.654 ; +; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.654 ; +; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.654 ; +; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.654 ; +; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.609 ; +; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.609 ; +; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.609 ; +; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.609 ; +; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.609 ; +; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.609 ; +; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.609 ; +; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.609 ; +; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.609 ; +; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.609 ; +; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.609 ; +; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.609 ; +; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.609 ; +; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.609 ; +; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.609 ; +; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.609 ; +; 17.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.581 ; +; 17.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.581 ; +; 17.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.581 ; +; 17.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.581 ; +; 17.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.581 ; +; 17.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.581 ; +; 17.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.581 ; +; 17.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.035 ; 2.581 ; ++--------+-------------------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Removal: 'CLOCK_50' ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 0.970 ; +; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 0.970 ; +; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 0.970 ; +; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 0.970 ; +; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 0.970 ; +; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 0.970 ; +; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 0.970 ; +; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 0.970 ; +; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 0.970 ; +; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 0.970 ; +; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 0.970 ; +; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 0.970 ; +; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 0.970 ; +; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 0.970 ; +; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 0.970 ; +; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 0.970 ; +; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 1.053 ; +; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 1.053 ; +; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 1.053 ; +; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 1.053 ; +; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 1.053 ; +; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 1.053 ; +; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 1.053 ; +; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 1.053 ; +; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 1.053 ; +; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 1.053 ; +; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 1.053 ; +; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 1.053 ; +; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 1.053 ; +; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 1.053 ; +; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 1.053 ; +; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.037 ; 1.053 ; +; 1.182 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.040 ; 1.306 ; +; 1.182 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.040 ; 1.306 ; +; 1.182 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.040 ; 1.306 ; +; 1.182 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.040 ; 1.306 ; +; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 1.311 ; +; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 1.311 ; +; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 1.311 ; +; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 1.311 ; +; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 1.311 ; +; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 1.311 ; +; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 1.311 ; +; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 1.311 ; +; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 1.311 ; +; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 1.311 ; +; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 1.311 ; +; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 1.311 ; +; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 1.311 ; +; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.444 ; +; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.444 ; +; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.444 ; +; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.444 ; +; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.444 ; +; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.444 ; +; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.444 ; +; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.444 ; +; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.444 ; +; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.444 ; +; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.444 ; +; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.444 ; +; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.444 ; +; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.444 ; +; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.444 ; +; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.444 ; +; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.473 ; +; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.473 ; +; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.473 ; +; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.473 ; +; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.473 ; +; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.473 ; +; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.473 ; +; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.473 ; +; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.473 ; +; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.473 ; +; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.473 ; +; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.473 ; +; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.487 ; +; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.487 ; +; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.487 ; +; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.487 ; +; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.487 ; +; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.487 ; +; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.487 ; +; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.487 ; +; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.487 ; +; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.487 ; +; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.487 ; +; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.487 ; +; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.487 ; +; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.487 ; +; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.487 ; +; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.487 ; +; 1.383 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.503 ; +; 1.383 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.503 ; +; 1.383 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.503 ; +; 1.383 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.503 ; +; 1.383 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.503 ; +; 1.383 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.503 ; +; 1.383 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 1.503 ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.007 ; 1.486 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.008 ; 1.491 ; +; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.020 ; 1.483 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.018 ; 1.486 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.018 ; 1.486 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.010 ; 1.494 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.010 ; 1.494 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.010 ; 1.494 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.010 ; 1.494 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.010 ; 1.494 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.010 ; 1.494 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.010 ; 1.494 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.488 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.488 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.488 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.488 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.015 ; 1.489 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.492 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.492 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.018 ; 1.486 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.018 ; 1.486 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.018 ; 1.486 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.018 ; 1.486 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.018 ; 1.486 ; +; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.018 ; 1.486 ; +; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.493 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.022 ; 1.486 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.022 ; 1.486 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.021 ; 1.487 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.022 ; 1.486 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.022 ; 1.486 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.022 ; 1.486 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.021 ; 1.487 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.022 ; 1.486 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.022 ; 1.486 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.021 ; 1.487 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.022 ; 1.486 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.022 ; 1.486 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.022 ; 1.486 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.021 ; 1.487 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.021 ; 1.487 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.022 ; 1.486 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.022 ; 1.486 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.021 ; 1.487 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.021 ; 1.487 ; +; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.022 ; 1.486 ; +; 2.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.019 ; 1.493 ; +; 2.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.019 ; 1.493 ; +; 2.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.019 ; 1.493 ; +; 2.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.019 ; 1.493 ; +; 2.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.019 ; 1.493 ; +; 2.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.019 ; 1.493 ; +; 2.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.019 ; 1.493 ; +; 2.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.035 ; 1.482 ; +; 2.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.035 ; 1.482 ; +; 2.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.035 ; 1.482 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.030 ; 1.491 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.030 ; 1.491 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.030 ; 1.491 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.030 ; 1.491 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.030 ; 1.491 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.030 ; 1.491 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.030 ; 1.491 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.030 ; 1.491 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.027 ; 1.494 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.027 ; 1.494 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.027 ; 1.494 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.027 ; 1.494 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.033 ; 1.488 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.033 ; 1.488 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.034 ; 1.487 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.034 ; 1.487 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.034 ; 1.487 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.034 ; 1.487 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.033 ; 1.488 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.034 ; 1.487 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.034 ; 1.487 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.034 ; 1.487 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.033 ; 1.488 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.033 ; 1.488 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.027 ; 1.494 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.027 ; 1.494 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.030 ; 1.491 ; +; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.030 ; 1.491 ; +; 2.438 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.037 ; 1.485 ; +; 2.438 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.037 ; 1.485 ; +; 2.438 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.037 ; 1.485 ; +; 2.440 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.033 ; 1.491 ; +; 2.440 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.033 ; 1.491 ; +; 2.440 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.033 ; 1.491 ; +; 2.440 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.033 ; 1.491 ; +; 2.440 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.033 ; 1.491 ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0 ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0 ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[11] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[4] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR ; +; 3.782 ; 3.966 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; +; 3.782 ; 3.966 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; +; 3.782 ; 3.966 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4] ; +; 3.782 ; 3.966 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5] ; +; 3.782 ; 3.966 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; +; 3.782 ; 3.966 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2] ; +; 3.782 ; 3.966 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3] ; +; 3.782 ; 3.966 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5] ; +; 3.782 ; 3.966 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6] ; +; 3.782 ; 3.966 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; +; 3.782 ; 3.966 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[8] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5] ; +; 3.783 ; 3.967 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6] ; ++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ; ++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+ +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; +; 9.266 ; 9.450 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_1 ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[0] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[1] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[2] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[3] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[4] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[5] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[6] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[7] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; ++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; 2.313 ; 3.173 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; 2.313 ; 3.173 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; 2.020 ; 2.772 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; 2.477 ; 3.286 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.145 ; 2.958 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.219 ; 2.968 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.199 ; 2.936 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.339 ; 3.104 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.171 ; 2.964 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.125 ; 2.875 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.319 ; 3.084 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.044 ; 2.800 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.117 ; 2.876 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.154 ; 2.906 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.149 ; 2.902 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 1.979 ; 2.735 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.143 ; 2.894 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.095 ; 2.869 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.477 ; 3.286 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; -0.978 ; -1.819 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; -0.978 ; -1.823 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; -1.027 ; -1.819 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; -1.578 ; -2.319 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; -1.739 ; -2.535 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; -1.827 ; -2.568 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; -1.810 ; -2.539 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; -1.943 ; -2.700 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; -1.762 ; -2.539 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; -1.733 ; -2.468 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; -1.925 ; -2.682 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; -1.640 ; -2.381 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; -1.716 ; -2.467 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; -1.761 ; -2.499 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; -1.756 ; -2.494 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; -1.578 ; -2.319 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; -1.751 ; -2.487 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; -1.692 ; -2.450 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; -2.076 ; -2.875 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 4.730 ; 4.624 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 3.684 ; 3.742 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 4.730 ; 4.624 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 3.815 ; 3.840 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 3.815 ; 3.840 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 3.242 ; 3.262 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 2.078 ; 2.058 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 1.952 ; 1.919 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 2.052 ; 2.029 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 2.057 ; 2.028 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 1.941 ; 1.906 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 1.978 ; 1.945 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 1.808 ; 1.766 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 1.853 ; 1.814 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 2.078 ; 2.058 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 1.927 ; 1.900 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 2.054 ; 2.025 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 1.844 ; 1.803 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 1.826 ; 1.785 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 1.834 ; 1.793 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 1.837 ; 1.796 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 1.803 ; 1.760 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 1.988 ; 1.956 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 4.395 ; 4.265 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.002 ; 2.927 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.121 ; 3.023 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.160 ; 3.078 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 4.395 ; 4.265 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.241 ; 3.219 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.153 ; 3.073 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.198 ; 3.158 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.262 ; 3.392 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.060 ; 3.149 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.863 ; 2.956 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.033 ; 3.014 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.869 ; 2.835 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.897 ; 2.958 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.024 ; 2.995 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.902 ; 2.958 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.130 ; 3.250 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 1.953 ; 1.920 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 1.907 ; 1.872 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 2.149 ; 2.152 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 3.454 ; 3.223 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -1.313 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -1.366 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 3.600 ; 3.651 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 3.600 ; 3.651 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 4.603 ; 4.499 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 3.725 ; 3.745 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 3.725 ; 3.745 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 3.171 ; 3.194 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 1.559 ; 1.515 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 1.698 ; 1.662 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 1.793 ; 1.768 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 1.798 ; 1.767 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 1.687 ; 1.650 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 1.722 ; 1.687 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 1.559 ; 1.515 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 1.602 ; 1.561 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 1.819 ; 1.797 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 1.672 ; 1.642 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 1.796 ; 1.765 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 1.595 ; 1.552 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 1.575 ; 1.533 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 1.583 ; 1.541 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 1.587 ; 1.545 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 1.553 ; 1.509 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 1.731 ; 1.697 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 2.168 ; 2.112 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.168 ; 2.154 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.351 ; 2.369 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.399 ; 2.438 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.763 ; 3.577 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.470 ; 2.514 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.385 ; 2.426 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.364 ; 2.385 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.482 ; 2.527 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.327 ; 2.344 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.176 ; 2.112 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.375 ; 2.389 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.296 ; 2.310 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.239 ; 2.200 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.483 ; 2.518 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.211 ; 2.169 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.435 ; 2.401 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 1.697 ; 1.662 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 1.654 ; 1.616 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 1.886 ; 1.885 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 3.200 ; 2.967 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -1.537 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -1.591 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; SW[4] ; VGA_B[0] ; 5.176 ; 5.154 ; 6.021 ; 5.999 ; +; SW[4] ; VGA_B[1] ; 5.325 ; 5.357 ; 6.143 ; 6.155 ; +; SW[4] ; VGA_B[2] ; 4.830 ; 4.862 ; 5.653 ; 5.685 ; +; SW[4] ; VGA_B[3] ; 4.907 ; 4.908 ; 5.750 ; 5.751 ; +; SW[4] ; VGA_G[0] ; 5.589 ; 5.608 ; 6.383 ; 6.402 ; +; SW[4] ; VGA_G[1] ; 4.995 ; 5.039 ; 5.858 ; 5.902 ; +; SW[4] ; VGA_G[2] ; 5.187 ; 5.230 ; 6.012 ; 6.021 ; +; SW[4] ; VGA_G[3] ; 5.213 ; 5.235 ; 6.059 ; 6.081 ; +; SW[4] ; VGA_R[0] ; 5.709 ; 5.731 ; 6.569 ; 6.591 ; +; SW[4] ; VGA_R[1] ; 5.293 ; 5.337 ; 6.128 ; 6.153 ; +; SW[4] ; VGA_R[2] ; 5.073 ; 5.075 ; 5.885 ; 5.894 ; +; SW[4] ; VGA_R[3] ; 5.035 ; 5.052 ; 5.862 ; 5.879 ; +; SW[5] ; VGA_B[0] ; 4.971 ; 4.949 ; 5.788 ; 5.766 ; +; SW[5] ; VGA_B[1] ; 4.983 ; 5.015 ; 5.757 ; 5.789 ; +; SW[5] ; VGA_B[2] ; 4.771 ; 4.803 ; 5.560 ; 5.578 ; +; SW[5] ; VGA_B[3] ; 4.704 ; 4.705 ; 5.518 ; 5.519 ; +; SW[5] ; VGA_G[0] ; 5.231 ; 5.250 ; 6.012 ; 6.031 ; +; SW[5] ; VGA_G[1] ; 4.807 ; 4.851 ; 5.613 ; 5.657 ; +; SW[5] ; VGA_G[2] ; 4.873 ; 4.916 ; 5.653 ; 5.695 ; +; SW[5] ; VGA_G[3] ; 5.009 ; 5.031 ; 5.823 ; 5.845 ; +; SW[5] ; VGA_R[0] ; 5.524 ; 5.546 ; 6.330 ; 6.352 ; +; SW[5] ; VGA_R[1] ; 4.954 ; 4.998 ; 5.728 ; 5.772 ; +; SW[5] ; VGA_R[2] ; 4.752 ; 4.754 ; 5.531 ; 5.533 ; +; SW[5] ; VGA_R[3] ; 4.891 ; 4.910 ; 5.724 ; 5.741 ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; SW[4] ; VGA_B[0] ; 4.956 ; 4.939 ; 5.803 ; 5.786 ; +; SW[4] ; VGA_B[1] ; 4.832 ; 4.867 ; 5.683 ; 5.681 ; +; SW[4] ; VGA_B[2] ; 4.699 ; 4.708 ; 5.495 ; 5.504 ; +; SW[4] ; VGA_B[3] ; 4.600 ; 4.593 ; 5.402 ; 5.418 ; +; SW[4] ; VGA_G[0] ; 5.265 ; 5.255 ; 6.138 ; 6.128 ; +; SW[4] ; VGA_G[1] ; 4.426 ; 4.447 ; 5.249 ; 5.263 ; +; SW[4] ; VGA_G[2] ; 4.957 ; 4.970 ; 5.808 ; 5.817 ; +; SW[4] ; VGA_G[3] ; 4.574 ; 4.595 ; 5.413 ; 5.389 ; +; SW[4] ; VGA_R[0] ; 5.413 ; 5.406 ; 6.276 ; 6.269 ; +; SW[4] ; VGA_R[1] ; 4.784 ; 4.809 ; 5.609 ; 5.627 ; +; SW[4] ; VGA_R[2] ; 4.871 ; 4.878 ; 5.700 ; 5.700 ; +; SW[4] ; VGA_R[3] ; 4.632 ; 4.692 ; 5.488 ; 5.461 ; +; SW[5] ; VGA_B[0] ; 4.392 ; 4.371 ; 5.181 ; 5.179 ; +; SW[5] ; VGA_B[1] ; 4.801 ; 4.837 ; 5.574 ; 5.610 ; +; SW[5] ; VGA_B[2] ; 4.374 ; 4.416 ; 5.188 ; 5.188 ; +; SW[5] ; VGA_B[3] ; 4.537 ; 4.543 ; 5.345 ; 5.344 ; +; SW[5] ; VGA_G[0] ; 4.426 ; 4.405 ; 5.215 ; 5.214 ; +; SW[5] ; VGA_G[1] ; 4.607 ; 4.637 ; 5.416 ; 5.428 ; +; SW[5] ; VGA_G[2] ; 4.453 ; 4.460 ; 5.231 ; 5.231 ; +; SW[5] ; VGA_G[3] ; 4.791 ; 4.811 ; 5.610 ; 5.622 ; +; SW[5] ; VGA_R[0] ; 4.516 ; 4.498 ; 5.305 ; 5.307 ; +; SW[5] ; VGA_R[1] ; 4.815 ; 4.836 ; 5.588 ; 5.609 ; +; SW[5] ; VGA_R[2] ; 4.584 ; 4.578 ; 5.354 ; 5.387 ; +; SW[5] ; VGA_R[3] ; 4.683 ; 4.742 ; 5.479 ; 5.520 ; ++------------+-------------+-------+-------+-------+-------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Output Enable Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.568 ; 2.549 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.911 ; 2.892 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.700 ; 2.681 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.710 ; 2.691 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.850 ; 2.831 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.568 ; 2.549 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.700 ; 2.681 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.588 ; 2.569 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.668 ; 2.649 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.926 ; 2.907 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.926 ; 2.907 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.931 ; 2.912 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.916 ; 2.897 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.921 ; 2.902 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.931 ; 2.912 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.911 ; 2.892 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.568 ; 2.549 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 1.449 ; 1.449 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 1.779 ; 1.779 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 1.576 ; 1.576 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 1.586 ; 1.586 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 1.720 ; 1.720 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 1.449 ; 1.449 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 1.576 ; 1.576 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 1.469 ; 1.469 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 1.545 ; 1.545 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 1.793 ; 1.793 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 1.793 ; 1.793 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 1.799 ; 1.799 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 1.783 ; 1.783 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 1.789 ; 1.789 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 1.799 ; 1.799 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 1.779 ; 1.779 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 1.449 ; 1.449 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Output Disable Times ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.613 ; 2.613 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.015 ; 3.015 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.753 ; 2.753 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.763 ; 2.763 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.916 ; 2.916 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.613 ; 2.613 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.753 ; 2.753 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.633 ; 2.633 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.726 ; 2.726 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.027 ; 3.027 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.027 ; 3.027 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.035 ; 3.035 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.017 ; 3.017 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.025 ; 3.025 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.035 ; 3.035 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.015 ; 3.015 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.613 ; 2.613 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 1.492 ; 1.624 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 1.878 ; 2.010 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 1.627 ; 1.759 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 1.637 ; 1.769 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 1.784 ; 1.916 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 1.492 ; 1.624 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 1.627 ; 1.759 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 1.512 ; 1.644 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 1.601 ; 1.733 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 1.891 ; 2.023 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 1.891 ; 2.023 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 1.898 ; 2.030 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 1.881 ; 2.013 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 1.888 ; 2.020 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 1.898 ; 2.030 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 1.878 ; 2.010 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 1.492 ; 1.624 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ + + +---------------- +; MTBF Summary ; +---------------- +Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 40 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 13.328 ns + +Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 + + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Worst-Case MTBF (Years) ; Typical MTBF (Years) ; Included in Design MTBF ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.328 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; ; ; ; 7.214 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; ; ; ; 6.114 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.361 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; ; ; ; 7.524 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; ; ; ; 5.837 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.363 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; ; ; ; 7.592 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; ; ; ; 5.771 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.483 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; ; ; ; 7.068 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; ; ; ; 6.415 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.491 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; ; ; ; 7.107 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; ; ; ; 6.384 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.495 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; ; ; ; 7.162 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; ; ; ; 6.333 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.506 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; ; ; ; 7.085 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; ; ; ; 6.421 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.510 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; ; ; ; 7.590 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; ; ; ; 5.920 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.544 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; ; ; ; 7.257 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; ; ; ; 6.287 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.572 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; ; ; ; 7.047 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; ; ; ; 6.525 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.587 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; ; ; ; 7.326 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; ; ; ; 6.261 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.597 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; ; ; ; 7.145 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; ; ; ; 6.452 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.633 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; ; ; ; 7.273 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; ; ; ; 6.360 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.641 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; ; ; ; 7.431 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; ; ; ; 6.210 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.664 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; ; ; ; 7.325 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; ; ; ; 6.339 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.669 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; ; ; ; 7.590 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; ; ; ; 6.079 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.681 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; ; ; ; 7.500 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; ; ; ; 6.181 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.763 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; ; ; ; 7.382 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; ; ; ; 6.381 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.765 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; ; ; ; 7.130 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; ; ; ; 6.635 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.779 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; ; ; ; 7.593 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; ; ; ; 6.186 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.789 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; ; ; ; 7.431 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; ; ; ; 6.358 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.818 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; ; ; ; 7.054 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; ; ; ; 6.764 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.827 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; ; ; ; 7.519 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; ; ; ; 6.308 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.858 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ; ; ; 7.442 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; ; ; ; 6.416 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.860 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; ; ; ; 7.534 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; ; ; ; 6.326 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.872 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; ; ; ; 7.263 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; ; ; ; 6.609 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.884 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; ; ; ; 7.442 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; ; ; ; 6.442 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.932 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; ; ; ; 7.596 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; ; ; ; 6.336 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.941 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; ; ; ; 7.530 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; ; ; ; 6.411 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.942 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; ; ; ; 7.526 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; ; ; ; 6.416 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.950 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; ; ; ; 7.532 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; ; ; ; 6.418 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.979 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; ; ; ; 7.597 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; ; ; ; 6.382 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.987 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; ; ; ; 7.599 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; ; ; ; 6.388 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.021 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; ; ; ; 7.440 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; ; ; ; 6.581 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.025 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; ; ; ; 7.531 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; ; ; ; 6.494 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.049 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ; ; ; 7.533 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; ; ; ; 6.516 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.064 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; ; ; ; 7.507 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; ; ; ; 6.557 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.078 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; ; ; ; 7.341 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; ; ; ; 6.737 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.099 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; ; ; ; 7.515 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; ; ; ; 6.584 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.388 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; ; ; ; 7.599 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; ; ; ; 6.789 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + ++-------------------------------------------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------------------------------------------+---------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------------------------------------------+---------+-------+----------+---------+---------------------+ +; Worst-case Slack ; -0.837 ; 0.169 ; -1.488 ; 0.849 ; 3.734 ; +; CLOCK_50 ; 14.268 ; 0.187 ; 12.673 ; 0.849 ; 9.266 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.837 ; 0.169 ; -1.488 ; 2.409 ; 3.734 ; +; Design-wide TNS ; -39.407 ; 0.0 ; -368.986 ; 0.0 ; 0.0 ; +; CLOCK_50 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -39.407 ; 0.000 ; -368.986 ; 0.000 ; 0.000 ; ++------------------------------------------------------+---------+-------+----------+---------+---------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; 4.175 ; 4.835 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; 4.175 ; 4.835 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; 3.570 ; 4.128 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; 4.346 ; 4.882 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.719 ; 4.304 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.888 ; 4.403 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.837 ; 4.347 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 4.081 ; 4.605 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.797 ; 4.328 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.695 ; 4.207 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 4.048 ; 4.575 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.537 ; 4.045 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.682 ; 4.211 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.737 ; 4.250 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.742 ; 4.251 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.421 ; 3.933 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.713 ; 4.225 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.625 ; 4.168 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 4.346 ; 4.882 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; -0.978 ; -1.819 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; -0.978 ; -1.823 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; -1.027 ; -1.819 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; -1.578 ; -2.319 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; -1.739 ; -2.535 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; -1.827 ; -2.568 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; -1.810 ; -2.539 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; -1.943 ; -2.700 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; -1.762 ; -2.539 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; -1.733 ; -2.468 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; -1.925 ; -2.682 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; -1.640 ; -2.381 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; -1.716 ; -2.467 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; -1.761 ; -2.499 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; -1.756 ; -2.494 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; -1.578 ; -2.319 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; -1.751 ; -2.487 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; -1.692 ; -2.450 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; -2.076 ; -2.875 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 7.926 ; 7.746 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 6.149 ; 6.132 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 7.926 ; 7.746 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 6.407 ; 6.287 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 6.407 ; 6.287 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 5.330 ; 5.394 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 3.447 ; 3.336 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 3.257 ; 3.115 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 3.414 ; 3.270 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 3.413 ; 3.273 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 3.225 ; 3.093 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 3.268 ; 3.141 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 3.008 ; 2.891 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 3.073 ; 2.949 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 3.447 ; 3.336 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 3.235 ; 3.095 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 3.429 ; 3.303 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 3.048 ; 2.930 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 3.030 ; 2.910 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 3.035 ; 2.917 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 3.038 ; 2.923 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 3.004 ; 2.884 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 3.343 ; 3.195 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 6.815 ; 6.557 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 5.037 ; 4.853 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 5.167 ; 4.959 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 5.229 ; 5.016 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 6.815 ; 6.557 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 5.405 ; 5.227 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 5.223 ; 5.014 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 5.360 ; 5.203 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 5.549 ; 5.513 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 5.131 ; 5.050 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 4.801 ; 4.763 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 5.067 ; 4.895 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 4.775 ; 4.677 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 4.893 ; 4.820 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 5.056 ; 4.954 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 4.932 ; 4.824 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 5.289 ; 5.224 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 3.240 ; 3.114 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 3.182 ; 3.050 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 3.560 ; 3.464 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 5.236 ; 4.875 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -0.448 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -0.595 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 3.600 ; 3.651 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 3.600 ; 3.651 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 4.603 ; 4.499 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 3.725 ; 3.745 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 3.725 ; 3.745 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 3.171 ; 3.194 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 1.559 ; 1.515 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 1.698 ; 1.662 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 1.793 ; 1.768 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 1.798 ; 1.767 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 1.687 ; 1.650 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 1.722 ; 1.687 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 1.559 ; 1.515 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 1.602 ; 1.561 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 1.819 ; 1.797 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 1.672 ; 1.642 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 1.796 ; 1.765 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 1.595 ; 1.552 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 1.575 ; 1.533 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 1.583 ; 1.541 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 1.587 ; 1.545 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 1.553 ; 1.509 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 1.731 ; 1.697 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 2.168 ; 2.112 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.168 ; 2.154 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.351 ; 2.369 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.399 ; 2.438 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.763 ; 3.577 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.470 ; 2.514 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.385 ; 2.426 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.364 ; 2.385 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.482 ; 2.527 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.327 ; 2.344 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.176 ; 2.112 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.375 ; 2.389 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.296 ; 2.310 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.239 ; 2.200 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.483 ; 2.518 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.211 ; 2.169 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.435 ; 2.401 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 1.697 ; 1.662 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 1.654 ; 1.616 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 1.886 ; 1.885 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 3.200 ; 2.967 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -1.537 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -1.591 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++------------------------------------------------------------+ +; Progagation Delay ; ++------------+-------------+-------+-------+--------+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+--------+--------+ +; SW[4] ; VGA_B[0] ; 8.826 ; 8.684 ; 9.435 ; 9.293 ; +; SW[4] ; VGA_B[1] ; 9.179 ; 9.016 ; 9.739 ; 9.533 ; +; SW[4] ; VGA_B[2] ; 8.250 ; 8.155 ; 8.832 ; 8.739 ; +; SW[4] ; VGA_B[3] ; 8.364 ; 8.243 ; 8.973 ; 8.852 ; +; SW[4] ; VGA_G[0] ; 9.485 ; 9.420 ; 10.061 ; 9.947 ; +; SW[4] ; VGA_G[1] ; 8.548 ; 8.524 ; 9.170 ; 9.146 ; +; SW[4] ; VGA_G[2] ; 8.898 ; 8.839 ; 9.483 ; 9.352 ; +; SW[4] ; VGA_G[3] ; 8.888 ; 8.793 ; 9.498 ; 9.407 ; +; SW[4] ; VGA_R[0] ; 9.747 ; 9.647 ; 10.341 ; 10.272 ; +; SW[4] ; VGA_R[1] ; 9.114 ; 8.972 ; 9.685 ; 9.510 ; +; SW[4] ; VGA_R[2] ; 8.692 ; 8.534 ; 9.241 ; 9.092 ; +; SW[4] ; VGA_R[3] ; 8.517 ; 8.427 ; 9.113 ; 9.023 ; +; SW[5] ; VGA_B[0] ; 8.458 ; 8.316 ; 9.069 ; 8.927 ; +; SW[5] ; VGA_B[1] ; 8.540 ; 8.377 ; 9.057 ; 8.894 ; +; SW[5] ; VGA_B[2] ; 8.138 ; 8.045 ; 8.672 ; 8.553 ; +; SW[5] ; VGA_B[3] ; 7.996 ; 7.875 ; 8.606 ; 8.485 ; +; SW[5] ; VGA_G[0] ; 8.837 ; 8.772 ; 9.396 ; 9.326 ; +; SW[5] ; VGA_G[1] ; 8.195 ; 8.171 ; 8.754 ; 8.730 ; +; SW[5] ; VGA_G[2] ; 8.330 ; 8.252 ; 8.870 ; 8.783 ; +; SW[5] ; VGA_G[3] ; 8.527 ; 8.427 ; 9.130 ; 9.039 ; +; SW[5] ; VGA_R[0] ; 9.391 ; 9.296 ; 9.924 ; 9.857 ; +; SW[5] ; VGA_R[1] ; 8.481 ; 8.339 ; 9.004 ; 8.854 ; +; SW[5] ; VGA_R[2] ; 8.101 ; 7.943 ; 8.629 ; 8.475 ; +; SW[5] ; VGA_R[3] ; 8.269 ; 8.189 ; 8.912 ; 8.822 ; ++------------+-------------+-------+-------+--------+--------+ + + ++----------------------------------------------------------+ +; Minimum Progagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; SW[4] ; VGA_B[0] ; 4.956 ; 4.939 ; 5.803 ; 5.786 ; +; SW[4] ; VGA_B[1] ; 4.832 ; 4.867 ; 5.683 ; 5.681 ; +; SW[4] ; VGA_B[2] ; 4.699 ; 4.708 ; 5.495 ; 5.504 ; +; SW[4] ; VGA_B[3] ; 4.600 ; 4.593 ; 5.402 ; 5.418 ; +; SW[4] ; VGA_G[0] ; 5.265 ; 5.255 ; 6.138 ; 6.128 ; +; SW[4] ; VGA_G[1] ; 4.426 ; 4.447 ; 5.249 ; 5.263 ; +; SW[4] ; VGA_G[2] ; 4.957 ; 4.970 ; 5.808 ; 5.817 ; +; SW[4] ; VGA_G[3] ; 4.574 ; 4.595 ; 5.413 ; 5.389 ; +; SW[4] ; VGA_R[0] ; 5.413 ; 5.406 ; 6.276 ; 6.269 ; +; SW[4] ; VGA_R[1] ; 4.784 ; 4.809 ; 5.609 ; 5.627 ; +; SW[4] ; VGA_R[2] ; 4.871 ; 4.878 ; 5.700 ; 5.700 ; +; SW[4] ; VGA_R[3] ; 4.632 ; 4.692 ; 5.488 ; 5.461 ; +; SW[5] ; VGA_B[0] ; 4.392 ; 4.371 ; 5.181 ; 5.179 ; +; SW[5] ; VGA_B[1] ; 4.801 ; 4.837 ; 5.574 ; 5.610 ; +; SW[5] ; VGA_B[2] ; 4.374 ; 4.416 ; 5.188 ; 5.188 ; +; SW[5] ; VGA_B[3] ; 4.537 ; 4.543 ; 5.345 ; 5.344 ; +; SW[5] ; VGA_G[0] ; 4.426 ; 4.405 ; 5.215 ; 5.214 ; +; SW[5] ; VGA_G[1] ; 4.607 ; 4.637 ; 5.416 ; 5.428 ; +; SW[5] ; VGA_G[2] ; 4.453 ; 4.460 ; 5.231 ; 5.231 ; +; SW[5] ; VGA_G[3] ; 4.791 ; 4.811 ; 5.610 ; 5.622 ; +; SW[5] ; VGA_R[0] ; 4.516 ; 4.498 ; 5.305 ; 5.307 ; +; SW[5] ; VGA_R[1] ; 4.815 ; 4.836 ; 5.588 ; 5.609 ; +; SW[5] ; VGA_R[2] ; 4.584 ; 4.578 ; 5.354 ; 5.387 ; +; SW[5] ; VGA_R[3] ; 4.683 ; 4.742 ; 5.479 ; 5.520 ; ++------------+-------------+-------+-------+-------+-------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; DRAM_LDQM ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_UDQM ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_BA_1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_BA_0 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_CAS_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_CKE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_CS_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_RAS_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_WE_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_CLK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_CLK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_HS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_VS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_B[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_B[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_B[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_B[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_G[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_G[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_G[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_G[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_R[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_R[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_R[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_R[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[31] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[30] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[29] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[28] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[27] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[26] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[25] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[24] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[23] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[22] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[21] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[20] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[19] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[18] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[17] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[16] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; PS2_DAT ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; PS2_CLK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; GPIO_1_CLKIN[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[15] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[14] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[13] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[12] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[11] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[31] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[30] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[29] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[28] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[27] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[26] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[25] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[24] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[23] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[22] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[21] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[20] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[19] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[18] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[17] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[16] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[15] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[14] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[13] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[12] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[11] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; PS2_DAT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; PS2_CLK ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; KEY[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; KEY[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1_CLKIN[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; KEY[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow Corner Signal Integrity Metrics ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; DRAM_LDQM ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_UDQM ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_BA_1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_BA_0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_CAS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_CKE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_CS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_RAS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_WE_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.08 V ; -0.00596 V ; 0.305 V ; 0.266 V ; 5.3e-09 s ; 4.39e-09 s ; Yes ; Yes ; 3.08 V ; 3.08e-06 V ; 3.08 V ; -0.00596 V ; 0.305 V ; 0.266 V ; 5.3e-09 s ; 4.39e-09 s ; Yes ; Yes ; +; DRAM_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; VGA_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; VGA_HS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_VS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; DRAM_ADDR[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; LEDG[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.08 V ; -0.00513 V ; 0.274 V ; 0.267 V ; 5.67e-09 s ; 4.62e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.08 V ; -0.00513 V ; 0.274 V ; 0.267 V ; 5.67e-09 s ; 4.62e-09 s ; No ; Yes ; +; LEDG[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_B[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_B[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_B[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_B[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_G[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_G[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_G[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_G[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_R[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_R[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_R[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_R[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; DRAM_DQ[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.08 V ; -0.00596 V ; 0.305 V ; 0.266 V ; 5.3e-09 s ; 4.39e-09 s ; Yes ; Yes ; 3.08 V ; 3.08e-06 V ; 3.08 V ; -0.00596 V ; 0.305 V ; 0.266 V ; 5.3e-09 s ; 4.39e-09 s ; Yes ; Yes ; +; DRAM_DQ[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[31] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[30] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[29] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[28] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[27] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[26] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[25] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[24] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[23] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[22] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[21] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[20] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[19] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[18] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; PS2_DAT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; PS2_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.02e-06 V ; 3.14 V ; -0.0402 V ; 0.146 V ; 0.156 V ; 4.62e-10 s ; 4.36e-10 s ; Yes ; Yes ; 3.08 V ; 1.02e-06 V ; 3.14 V ; -0.0402 V ; 0.146 V ; 0.156 V ; 4.62e-10 s ; 4.36e-10 s ; Yes ; Yes ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast Corner Signal Integrity Metrics ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; DRAM_LDQM ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_UDQM ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_BA_1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_BA_0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_CAS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_CKE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_CS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_RAS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_WE_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.48 V ; -0.0142 V ; 0.362 V ; 0.291 V ; 3.89e-09 s ; 3.25e-09 s ; No ; No ; 3.46 V ; 1.9e-07 V ; 3.48 V ; -0.0142 V ; 0.362 V ; 0.291 V ; 3.89e-09 s ; 3.25e-09 s ; No ; No ; +; DRAM_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; VGA_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; VGA_HS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_VS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; DRAM_ADDR[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; LEDG[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.346 V ; 4.12e-09 s ; 3.34e-09 s ; No ; Yes ; 3.46 V ; 1.29e-07 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.346 V ; 4.12e-09 s ; 3.34e-09 s ; No ; Yes ; +; LEDG[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_B[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_B[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_B[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_B[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_G[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_G[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_G[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_G[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_R[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_R[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_R[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_R[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; DRAM_DQ[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.48 V ; -0.0142 V ; 0.362 V ; 0.291 V ; 3.89e-09 s ; 3.25e-09 s ; No ; No ; 3.46 V ; 1.9e-07 V ; 3.48 V ; -0.0142 V ; 0.362 V ; 0.291 V ; 3.89e-09 s ; 3.25e-09 s ; No ; No ; +; DRAM_DQ[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[31] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[30] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[29] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[28] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[27] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[26] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[25] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[24] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[23] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[22] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[21] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[20] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[19] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[18] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; PS2_DAT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; PS2_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.52e-08 V ; 3.58 V ; -0.064 V ; 0.234 V ; 0.085 V ; 2.93e-10 s ; 3.07e-10 s ; Yes ; Yes ; 3.46 V ; 6.52e-08 V ; 3.58 V ; -0.064 V ; 0.234 V ; 0.085 V ; 2.93e-10 s ; 3.07e-10 s ; Yes ; Yes ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup Transfers ; ++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 3231 ; 0 ; 0 ; 0 ; +; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 141 ; 0 ; 0 ; 0 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 11685 ; 0 ; 0 ; 0 ; ++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold Transfers ; ++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 3231 ; 0 ; 0 ; 0 ; +; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 141 ; 0 ; 0 ; 0 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 11685 ; 0 ; 0 ; 0 ; ++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++--------------------------------------------------------------------------------------------------------------+ +; Recovery Transfers ; ++------------+-----------------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+-----------------------------------------------------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 519 ; 0 ; 0 ; 0 ; +; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 302 ; 0 ; 0 ; 0 ; ++------------+-----------------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++--------------------------------------------------------------------------------------------------------------+ +; Removal Transfers ; ++------------+-----------------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+-----------------------------------------------------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 519 ; 0 ; 0 ; 0 ; +; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 302 ; 0 ; 0 ; 0 ; ++------------+-----------------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 5 ; 5 ; +; Unconstrained Input Ports ; 43 ; 43 ; +; Unconstrained Input Port Paths ; 491 ; 491 ; +; Unconstrained Output Ports ; 89 ; 89 ; +; Unconstrained Output Port Paths ; 530 ; 530 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version + Info: Processing started: Tue Mar 08 16:24:47 2016 +Info: Command: quartus_sta DE0_D5M -c DE0_D5M +Info: qsta_default_script.tcl version: #1 +Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (332164): Evaluating HDL-embedded SDC commands + Info (332165): Entity dcfifo_v5o1 + Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* + Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* +Info (332104): Reading SDC File: 'DE0_D5M.sdc' +Info (332110): Deriving PLL clocks + Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[0]} {inst|u6|altpll_component|auto_generated|pll1|clk[0]} + Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[1]} {inst|u6|altpll_component|auto_generated|pll1|clk[1]} +Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment. +Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. + Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold) + Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) + Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1200mV 85C Model +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. +Info (332146): Worst-case setup slack is -0.837 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -0.837 -39.407 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 14.268 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.331 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 0.331 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.358 0.000 CLOCK_50 +Info (332146): Worst-case recovery slack is -1.488 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -1.488 -368.986 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 12.673 0.000 CLOCK_50 +Info (332146): Worst-case removal slack is 1.559 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 1.559 0.000 CLOCK_50 + Info (332119): 4.115 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case minimum pulse width slack is 3.734 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 3.734 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.580 0.000 CLOCK_50 +Info (332114): Report Metastability: Found 40 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 40 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 11.193 ns + Info (332114): + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment. +Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. + Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold) + Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) + Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. +Info (332146): Worst-case setup slack is -0.283 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -0.283 -5.821 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 14.832 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.298 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 0.298 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.312 0.000 CLOCK_50 +Info (332146): Worst-case recovery slack is -0.835 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -0.835 -178.452 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 13.489 0.000 CLOCK_50 +Info (332146): Worst-case removal slack is 1.418 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 1.418 0.000 CLOCK_50 + Info (332119): 3.617 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case minimum pulse width slack is 3.739 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 3.739 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.561 0.000 CLOCK_50 +Info (332114): Report Metastability: Found 40 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 40 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 11.719 ns + Info (332114): + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 +Info: Analyzing Fast 1200mV 0C Model +Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment. +Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. + Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold) + Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) + Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) +Info (332146): Worst-case setup slack is 1.209 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 1.209 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 16.656 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.169 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 0.169 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.187 0.000 CLOCK_50 +Info (332146): Worst-case recovery slack is 0.780 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 0.780 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 15.649 0.000 CLOCK_50 +Info (332146): Worst-case removal slack is 0.849 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 0.849 0.000 CLOCK_50 + Info (332119): 2.409 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case minimum pulse width slack is 3.746 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 3.746 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.266 0.000 CLOCK_50 +Info (332114): Report Metastability: Found 40 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 40 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 13.328 ns + Info (332114): + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 29 warnings + Info: Peak virtual memory: 549 megabytes + Info: Processing ended: Tue Mar 08 16:24:59 2016 + Info: Elapsed time: 00:00:12 + Info: Total CPU time (on all processors): 00:00:06 + + |