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diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v
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index 0000000..dda909a
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v
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+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   rad09@EE-RAD09-02
+//  Generated date: Wed Mar 06 11:57:58 2013
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    vga_mouse_square_core
+// ------------------------------------------------------------------
+
+
+module vga_mouse_square_core (
+  clk, en, arst_n, vga_xy_rsc_mgc_in_wire_d, mouse_xy_rsc_mgc_in_wire_d, cursor_size_rsc_mgc_in_wire_d,
+      video_in_rsc_mgc_in_wire_d, video_out_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [19:0] vga_xy_rsc_mgc_in_wire_d;
+  input [19:0] mouse_xy_rsc_mgc_in_wire_d;
+  input [7:0] cursor_size_rsc_mgc_in_wire_d;
+  input [29:0] video_in_rsc_mgc_in_wire_d;
+  output [29:0] video_out_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [9:0] reg_video_out_rsc_mgc_out_stdreg_d_tmp;
+  reg [9:0] reg_video_out_rsc_mgc_out_stdreg_d_tmp_1;
+  reg [9:0] reg_video_out_rsc_mgc_out_stdreg_d_tmp_2;
+  wire or_itm;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign video_out_rsc_mgc_out_stdreg_d = {reg_video_out_rsc_mgc_out_stdreg_d_tmp
+      , reg_video_out_rsc_mgc_out_stdreg_d_tmp_1 , reg_video_out_rsc_mgc_out_stdreg_d_tmp_2};
+  assign or_itm = (readslicef_12_1_11((conv_u2u_11_12(readslicef_12_11_1((conv_u2u_11_12({(mouse_xy_rsc_mgc_in_wire_d[19:10])
+      , 1'b1}) + conv_u2u_11_12({(~ (vga_xy_rsc_mgc_in_wire_d[19:10])) , 1'b1}))))
+      + conv_s2u_11_12({3'b100 , cursor_size_rsc_mgc_in_wire_d})))) | (readslicef_12_1_11((conv_u2u_11_12(readslicef_12_11_1((conv_u2u_11_12({(vga_xy_rsc_mgc_in_wire_d[19:10])
+      , 1'b1}) + conv_u2u_11_12({(~ (mouse_xy_rsc_mgc_in_wire_d[19:10])) , 1'b1}))))
+      + conv_s2u_11_12({3'b100 , cursor_size_rsc_mgc_in_wire_d})))) | (readslicef_12_1_11((conv_u2u_11_12(readslicef_12_11_1((conv_u2u_11_12({(mouse_xy_rsc_mgc_in_wire_d[9:0])
+      , 1'b1}) + conv_u2u_11_12({(~ (vga_xy_rsc_mgc_in_wire_d[9:0])) , 1'b1}))))
+      + conv_s2u_11_12({3'b100 , cursor_size_rsc_mgc_in_wire_d})))) | (readslicef_12_1_11((conv_u2u_11_12(readslicef_12_11_1((conv_u2u_11_12({(vga_xy_rsc_mgc_in_wire_d[9:0])
+      , 1'b1}) + conv_u2u_11_12({(~ (mouse_xy_rsc_mgc_in_wire_d[9:0])) , 1'b1}))))
+      + conv_s2u_11_12({3'b100 , cursor_size_rsc_mgc_in_wire_d}))));
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      reg_video_out_rsc_mgc_out_stdreg_d_tmp <= 10'b0;
+      reg_video_out_rsc_mgc_out_stdreg_d_tmp_1 <= 10'b0;
+      reg_video_out_rsc_mgc_out_stdreg_d_tmp_2 <= 10'b0;
+    end
+    else begin
+      if ( en ) begin
+        reg_video_out_rsc_mgc_out_stdreg_d_tmp <= (video_in_rsc_mgc_in_wire_d[29:20])
+            & ({{9{or_itm}}, or_itm});
+        reg_video_out_rsc_mgc_out_stdreg_d_tmp_1 <= video_in_rsc_mgc_in_wire_d[19:10];
+        reg_video_out_rsc_mgc_out_stdreg_d_tmp_2 <= (video_in_rsc_mgc_in_wire_d[9:0])
+            & ({{9{or_itm}}, or_itm});
+      end
+    end
+  end
+
+  function [0:0] readslicef_12_1_11;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 11;
+    readslicef_12_1_11 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    vga_mouse_square
+//  Generated from file(s):
+//   12) $PROJECT_HOME/vga_mouse_square__old/vga_mouse_square_working_demo_sw.c
+// ------------------------------------------------------------------
+
+
+module vga_mouse_square (
+  vga_xy_rsc_z, mouse_xy_rsc_z, cursor_size_rsc_z, video_in_rsc_z, video_out_rsc_z,
+      clk, en, arst_n
+);
+  input [19:0] vga_xy_rsc_z;
+  input [19:0] mouse_xy_rsc_z;
+  input [7:0] cursor_size_rsc_z;
+  input [29:0] video_in_rsc_z;
+  output [29:0] video_out_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [19:0] vga_xy_rsc_mgc_in_wire_d;
+  wire [19:0] mouse_xy_rsc_mgc_in_wire_d;
+  wire [7:0] cursor_size_rsc_mgc_in_wire_d;
+  wire [29:0] video_in_rsc_mgc_in_wire_d;
+  wire [29:0] video_out_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(20)) vga_xy_rsc_mgc_in_wire (
+      .d(vga_xy_rsc_mgc_in_wire_d),
+      .z(vga_xy_rsc_z)
+    );
+  mgc_in_wire #(.rscid(2),
+  .width(20)) mouse_xy_rsc_mgc_in_wire (
+      .d(mouse_xy_rsc_mgc_in_wire_d),
+      .z(mouse_xy_rsc_z)
+    );
+  mgc_in_wire #(.rscid(3),
+  .width(8)) cursor_size_rsc_mgc_in_wire (
+      .d(cursor_size_rsc_mgc_in_wire_d),
+      .z(cursor_size_rsc_z)
+    );
+  mgc_in_wire #(.rscid(4),
+  .width(30)) video_in_rsc_mgc_in_wire (
+      .d(video_in_rsc_mgc_in_wire_d),
+      .z(video_in_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(5),
+  .width(30)) video_out_rsc_mgc_out_stdreg (
+      .d(video_out_rsc_mgc_out_stdreg_d),
+      .z(video_out_rsc_z)
+    );
+  vga_mouse_square_core vga_mouse_square_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vga_xy_rsc_mgc_in_wire_d(vga_xy_rsc_mgc_in_wire_d),
+      .mouse_xy_rsc_mgc_in_wire_d(mouse_xy_rsc_mgc_in_wire_d),
+      .cursor_size_rsc_mgc_in_wire_d(cursor_size_rsc_mgc_in_wire_d),
+      .video_in_rsc_mgc_in_wire_d(video_in_rsc_mgc_in_wire_d),
+      .video_out_rsc_mgc_out_stdreg_d(video_out_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+