diff options
Diffstat (limited to 'student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.hier_info')
| -rw-r--r-- | student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.hier_info | 13948 |
1 files changed, 13948 insertions, 0 deletions
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.hier_info b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.hier_info new file mode 100644 index 0000000..72a4e8f --- /dev/null +++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.hier_info @@ -0,0 +1,13948 @@ +|TOP_DE0_CAMERA_MOUSE +DRAM_LDQM <= DE0_D5M:inst.DRAM_LDQM +CLOCK_50 => DE0_D5M:inst.CLOCK_50 +CLOCK_50 => ps2:inst6.iCLK_50 +DRAM_DQ[0] <> DE0_D5M:inst.DRAM_DQ[0] +DRAM_DQ[1] <> DE0_D5M:inst.DRAM_DQ[1] +DRAM_DQ[2] <> DE0_D5M:inst.DRAM_DQ[2] +DRAM_DQ[3] <> DE0_D5M:inst.DRAM_DQ[3] +DRAM_DQ[4] <> DE0_D5M:inst.DRAM_DQ[4] +DRAM_DQ[5] <> DE0_D5M:inst.DRAM_DQ[5] +DRAM_DQ[6] <> DE0_D5M:inst.DRAM_DQ[6] +DRAM_DQ[7] <> DE0_D5M:inst.DRAM_DQ[7] +DRAM_DQ[8] <> DE0_D5M:inst.DRAM_DQ[8] +DRAM_DQ[9] <> DE0_D5M:inst.DRAM_DQ[9] +DRAM_DQ[10] <> DE0_D5M:inst.DRAM_DQ[10] +DRAM_DQ[11] <> DE0_D5M:inst.DRAM_DQ[11] +DRAM_DQ[12] <> DE0_D5M:inst.DRAM_DQ[12] +DRAM_DQ[13] <> DE0_D5M:inst.DRAM_DQ[13] +DRAM_DQ[14] <> DE0_D5M:inst.DRAM_DQ[14] +DRAM_DQ[15] <> DE0_D5M:inst.DRAM_DQ[15] +GPIO_1[0] <> DE0_D5M:inst.GPIO_1[0] +GPIO_1[1] <> DE0_D5M:inst.GPIO_1[1] +GPIO_1[2] <> DE0_D5M:inst.GPIO_1[2] +GPIO_1[3] <> DE0_D5M:inst.GPIO_1[3] +GPIO_1[4] <> DE0_D5M:inst.GPIO_1[4] +GPIO_1[5] <> DE0_D5M:inst.GPIO_1[5] +GPIO_1[6] <> DE0_D5M:inst.GPIO_1[6] +GPIO_1[7] <> DE0_D5M:inst.GPIO_1[7] +GPIO_1[8] <> DE0_D5M:inst.GPIO_1[8] +GPIO_1[9] <> DE0_D5M:inst.GPIO_1[9] +GPIO_1[10] <> DE0_D5M:inst.GPIO_1[10] +GPIO_1[11] <> DE0_D5M:inst.GPIO_1[11] +GPIO_1[12] <> DE0_D5M:inst.GPIO_1[12] +GPIO_1[13] <> DE0_D5M:inst.GPIO_1[13] +GPIO_1[14] <> DE0_D5M:inst.GPIO_1[14] +GPIO_1[15] <> DE0_D5M:inst.GPIO_1[15] +GPIO_1[16] <> DE0_D5M:inst.GPIO_1[16] +GPIO_1[17] <> DE0_D5M:inst.GPIO_1[17] +GPIO_1[18] <> DE0_D5M:inst.GPIO_1[18] +GPIO_1[19] <> DE0_D5M:inst.GPIO_1[19] +GPIO_1[20] <> DE0_D5M:inst.GPIO_1[20] +GPIO_1[21] <> DE0_D5M:inst.GPIO_1[21] +GPIO_1[22] <> DE0_D5M:inst.GPIO_1[22] +GPIO_1[23] <> DE0_D5M:inst.GPIO_1[23] +GPIO_1[24] <> DE0_D5M:inst.GPIO_1[24] +GPIO_1[25] <> DE0_D5M:inst.GPIO_1[25] +GPIO_1[26] <> DE0_D5M:inst.GPIO_1[26] +GPIO_1[27] <> DE0_D5M:inst.GPIO_1[27] +GPIO_1[28] <> DE0_D5M:inst.GPIO_1[28] +GPIO_1[29] <> DE0_D5M:inst.GPIO_1[29] +GPIO_1[30] <> DE0_D5M:inst.GPIO_1[30] +GPIO_1[31] <> DE0_D5M:inst.GPIO_1[31] +GPIO_1_CLKIN[0] => DE0_D5M:inst.GPIO_1_CLKIN[0] +GPIO_1_CLKIN[1] => DE0_D5M:inst.GPIO_1_CLKIN[1] +KEY[0] => DE0_D5M:inst.KEY[0] +KEY[0] => ps2:inst6.iRST_n +KEY[0] => vga_mouse_square:vga_mouse_catapult_inst.arst_n +KEY[0] => sobel:inst1.arst_n +KEY[1] => DE0_D5M:inst.KEY[1] +KEY[1] => ps2:inst6.iSTART +KEY[2] => DE0_D5M:inst.KEY[2] +SW[0] => DE0_D5M:inst.SW[0] +SW[0] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[0] +SW[1] => DE0_D5M:inst.SW[1] +SW[1] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[1] +SW[2] => DE0_D5M:inst.SW[2] +SW[2] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[2] +SW[3] => DE0_D5M:inst.SW[3] +SW[3] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[3] +SW[4] => DE0_D5M:inst.SW[4] +SW[4] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[4] +SW[4] => vga_mux:inst10.sel[0] +SW[5] => DE0_D5M:inst.SW[5] +SW[5] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[5] +SW[5] => vga_mux:inst10.sel[1] +SW[6] => DE0_D5M:inst.SW[6] +SW[6] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[6] +SW[7] => DE0_D5M:inst.SW[7] +SW[7] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[7] +SW[8] => DE0_D5M:inst.SW[8] +SW[9] => DE0_D5M:inst.SW[9] +DRAM_UDQM <= DE0_D5M:inst.DRAM_UDQM +DRAM_BA_1 <= DE0_D5M:inst.DRAM_BA_1 +DRAM_BA_0 <= DE0_D5M:inst.DRAM_BA_0 +DRAM_CAS_N <= DE0_D5M:inst.DRAM_CAS_N +DRAM_CKE <= DE0_D5M:inst.DRAM_CKE +DRAM_CS_N <= DE0_D5M:inst.DRAM_CS_N +DRAM_RAS_N <= DE0_D5M:inst.DRAM_RAS_N +DRAM_WE_N <= DE0_D5M:inst.DRAM_WE_N +DRAM_CLK <= DE0_D5M:inst.DRAM_CLK +VGA_CLK <= DE0_D5M:inst.VGA_CLK +VGA_HS <= DE0_D5M:inst.VGA_HS +VGA_VS <= DE0_D5M:inst.VGA_VS +PS2_DAT <> ps2:inst6.PS2_DAT +PS2_CLK <> ps2:inst6.PS2_CLK +DRAM_ADDR[0] <= DE0_D5M:inst.DRAM_ADDR[0] +DRAM_ADDR[1] <= DE0_D5M:inst.DRAM_ADDR[1] +DRAM_ADDR[2] <= DE0_D5M:inst.DRAM_ADDR[2] +DRAM_ADDR[3] <= DE0_D5M:inst.DRAM_ADDR[3] +DRAM_ADDR[4] <= DE0_D5M:inst.DRAM_ADDR[4] +DRAM_ADDR[5] <= DE0_D5M:inst.DRAM_ADDR[5] +DRAM_ADDR[6] <= DE0_D5M:inst.DRAM_ADDR[6] +DRAM_ADDR[7] <= DE0_D5M:inst.DRAM_ADDR[7] +DRAM_ADDR[8] <= DE0_D5M:inst.DRAM_ADDR[8] +DRAM_ADDR[9] <= DE0_D5M:inst.DRAM_ADDR[9] +DRAM_ADDR[10] <= DE0_D5M:inst.DRAM_ADDR[10] +DRAM_ADDR[11] <= DE0_D5M:inst.DRAM_ADDR[11] +GPIO_1_CLKOUT[0] <= DE0_D5M:inst.GPIO_1_CLKOUT[0] +GPIO_1_CLKOUT[1] <= DE0_D5M:inst.GPIO_1_CLKOUT[1] +HEX0[0] <= ps2:inst6.oX_MOV1[0] +HEX0[1] <= ps2:inst6.oX_MOV1[1] +HEX0[2] <= ps2:inst6.oX_MOV1[2] +HEX0[3] <= ps2:inst6.oX_MOV1[3] +HEX0[4] <= ps2:inst6.oX_MOV1[4] +HEX0[5] <= ps2:inst6.oX_MOV1[5] +HEX0[6] <= ps2:inst6.oX_MOV1[6] +HEX1[0] <= ps2:inst6.oX_MOV2[0] +HEX1[1] <= ps2:inst6.oX_MOV2[1] +HEX1[2] <= ps2:inst6.oX_MOV2[2] +HEX1[3] <= ps2:inst6.oX_MOV2[3] +HEX1[4] <= ps2:inst6.oX_MOV2[4] +HEX1[5] <= ps2:inst6.oX_MOV2[5] +HEX1[6] <= ps2:inst6.oX_MOV2[6] +HEX2[0] <= ps2:inst6.oY_MOV1[0] +HEX2[1] <= ps2:inst6.oY_MOV1[1] +HEX2[2] <= ps2:inst6.oY_MOV1[2] +HEX2[3] <= ps2:inst6.oY_MOV1[3] +HEX2[4] <= ps2:inst6.oY_MOV1[4] +HEX2[5] <= ps2:inst6.oY_MOV1[5] +HEX2[6] <= ps2:inst6.oY_MOV1[6] +HEX3[0] <= ps2:inst6.oY_MOV2[0] +HEX3[1] <= ps2:inst6.oY_MOV2[1] +HEX3[2] <= ps2:inst6.oY_MOV2[2] +HEX3[3] <= ps2:inst6.oY_MOV2[3] +HEX3[4] <= ps2:inst6.oY_MOV2[4] +HEX3[5] <= ps2:inst6.oY_MOV2[5] +HEX3[6] <= ps2:inst6.oY_MOV2[6] +LEDG[0] <= ps2:inst6.oRIGBUT +LEDG[1] <= ps2:inst6.oMIDBUT +LEDG[2] <= ps2:inst6.oLEFBUT +LEDG[3] <= <GND> +LEDG[4] <= <GND> +LEDG[5] <= <GND> +LEDG[6] <= <GND> +LEDG[7] <= <GND> +LEDG[8] <= <GND> +LEDG[9] <= <GND> +VGA_B[0] <= VGA_MUX_OUT[6].DB_MAX_OUTPUT_PORT_TYPE +VGA_B[1] <= VGA_MUX_OUT[7].DB_MAX_OUTPUT_PORT_TYPE +VGA_B[2] <= VGA_MUX_OUT[8].DB_MAX_OUTPUT_PORT_TYPE +VGA_B[3] <= VGA_MUX_OUT[9].DB_MAX_OUTPUT_PORT_TYPE +VGA_G[0] <= VGA_MUX_OUT[16].DB_MAX_OUTPUT_PORT_TYPE +VGA_G[1] <= VGA_MUX_OUT[17].DB_MAX_OUTPUT_PORT_TYPE +VGA_G[2] <= VGA_MUX_OUT[18].DB_MAX_OUTPUT_PORT_TYPE +VGA_G[3] <= VGA_MUX_OUT[19].DB_MAX_OUTPUT_PORT_TYPE +VGA_R[0] <= VGA_MUX_OUT[26].DB_MAX_OUTPUT_PORT_TYPE +VGA_R[1] <= VGA_MUX_OUT[27].DB_MAX_OUTPUT_PORT_TYPE +VGA_R[2] <= VGA_MUX_OUT[28].DB_MAX_OUTPUT_PORT_TYPE +VGA_R[3] <= VGA_MUX_OUT[29].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst +CLOCK_50 => CLOCK_50.IN4 +KEY[0] => KEY[0].IN1 +KEY[1] => _.IN1 +KEY[2] => _.IN1 +SW[0] => SW[0].IN1 +SW[1] => SW[1].IN1 +SW[2] => SW[2].IN1 +SW[3] => ~NO_FANOUT~ +SW[4] => ~NO_FANOUT~ +SW[5] => ~NO_FANOUT~ +SW[6] => ~NO_FANOUT~ +SW[7] => ~NO_FANOUT~ +SW[8] => ~NO_FANOUT~ +SW[9] => ~NO_FANOUT~ +LEDG[0] <= Y_Cont[0].DB_MAX_OUTPUT_PORT_TYPE +LEDG[1] <= Y_Cont[1].DB_MAX_OUTPUT_PORT_TYPE +LEDG[2] <= Y_Cont[2].DB_MAX_OUTPUT_PORT_TYPE +LEDG[3] <= Y_Cont[3].DB_MAX_OUTPUT_PORT_TYPE +LEDG[4] <= Y_Cont[4].DB_MAX_OUTPUT_PORT_TYPE +LEDG[5] <= Y_Cont[5].DB_MAX_OUTPUT_PORT_TYPE +LEDG[6] <= Y_Cont[6].DB_MAX_OUTPUT_PORT_TYPE +LEDG[7] <= Y_Cont[7].DB_MAX_OUTPUT_PORT_TYPE +LEDG[8] <= Y_Cont[8].DB_MAX_OUTPUT_PORT_TYPE +LEDG[9] <= Y_Cont[9].DB_MAX_OUTPUT_PORT_TYPE +HEX0[0] <= SEG7_LUT_8:u5.oSEG0 +HEX0[1] <= SEG7_LUT_8:u5.oSEG0 +HEX0[2] <= SEG7_LUT_8:u5.oSEG0 +HEX0[3] <= SEG7_LUT_8:u5.oSEG0 +HEX0[4] <= SEG7_LUT_8:u5.oSEG0 +HEX0[5] <= SEG7_LUT_8:u5.oSEG0 +HEX0[6] <= SEG7_LUT_8:u5.oSEG0 +HEX1[0] <= SEG7_LUT_8:u5.oSEG1 +HEX1[1] <= SEG7_LUT_8:u5.oSEG1 +HEX1[2] <= SEG7_LUT_8:u5.oSEG1 +HEX1[3] <= SEG7_LUT_8:u5.oSEG1 +HEX1[4] <= SEG7_LUT_8:u5.oSEG1 +HEX1[5] <= SEG7_LUT_8:u5.oSEG1 +HEX1[6] <= SEG7_LUT_8:u5.oSEG1 +HEX2[0] <= SEG7_LUT_8:u5.oSEG2 +HEX2[1] <= SEG7_LUT_8:u5.oSEG2 +HEX2[2] <= SEG7_LUT_8:u5.oSEG2 +HEX2[3] <= SEG7_LUT_8:u5.oSEG2 +HEX2[4] <= SEG7_LUT_8:u5.oSEG2 +HEX2[5] <= SEG7_LUT_8:u5.oSEG2 +HEX2[6] <= SEG7_LUT_8:u5.oSEG2 +HEX3[0] <= SEG7_LUT_8:u5.oSEG3 +HEX3[1] <= SEG7_LUT_8:u5.oSEG3 +HEX3[2] <= SEG7_LUT_8:u5.oSEG3 +HEX3[3] <= SEG7_LUT_8:u5.oSEG3 +HEX3[4] <= SEG7_LUT_8:u5.oSEG3 +HEX3[5] <= SEG7_LUT_8:u5.oSEG3 +HEX3[6] <= SEG7_LUT_8:u5.oSEG3 +DRAM_DQ[0] <> Sdram_Control_4Port:u7.DQ +DRAM_DQ[1] <> Sdram_Control_4Port:u7.DQ +DRAM_DQ[2] <> Sdram_Control_4Port:u7.DQ +DRAM_DQ[3] <> Sdram_Control_4Port:u7.DQ +DRAM_DQ[4] <> Sdram_Control_4Port:u7.DQ +DRAM_DQ[5] <> Sdram_Control_4Port:u7.DQ +DRAM_DQ[6] <> Sdram_Control_4Port:u7.DQ +DRAM_DQ[7] <> Sdram_Control_4Port:u7.DQ +DRAM_DQ[8] <> Sdram_Control_4Port:u7.DQ +DRAM_DQ[9] <> Sdram_Control_4Port:u7.DQ +DRAM_DQ[10] <> Sdram_Control_4Port:u7.DQ +DRAM_DQ[11] <> Sdram_Control_4Port:u7.DQ +DRAM_DQ[12] <> Sdram_Control_4Port:u7.DQ +DRAM_DQ[13] <> Sdram_Control_4Port:u7.DQ +DRAM_DQ[14] <> Sdram_Control_4Port:u7.DQ +DRAM_DQ[15] <> Sdram_Control_4Port:u7.DQ +DRAM_ADDR[0] <= Sdram_Control_4Port:u7.SA +DRAM_ADDR[1] <= Sdram_Control_4Port:u7.SA +DRAM_ADDR[2] <= Sdram_Control_4Port:u7.SA +DRAM_ADDR[3] <= Sdram_Control_4Port:u7.SA +DRAM_ADDR[4] <= Sdram_Control_4Port:u7.SA +DRAM_ADDR[5] <= Sdram_Control_4Port:u7.SA +DRAM_ADDR[6] <= Sdram_Control_4Port:u7.SA +DRAM_ADDR[7] <= Sdram_Control_4Port:u7.SA +DRAM_ADDR[8] <= Sdram_Control_4Port:u7.SA +DRAM_ADDR[9] <= Sdram_Control_4Port:u7.SA +DRAM_ADDR[10] <= Sdram_Control_4Port:u7.SA +DRAM_ADDR[11] <= Sdram_Control_4Port:u7.SA +DRAM_LDQM <= Sdram_Control_4Port:u7.DQM +DRAM_UDQM <= Sdram_Control_4Port:u7.DQM +DRAM_WE_N <= Sdram_Control_4Port:u7.WE_N +DRAM_CAS_N <= Sdram_Control_4Port:u7.CAS_N +DRAM_RAS_N <= Sdram_Control_4Port:u7.RAS_N +DRAM_CS_N <= Sdram_Control_4Port:u7.CS_N +DRAM_BA_0 <= Sdram_Control_4Port:u7.BA +DRAM_BA_1 <= Sdram_Control_4Port:u7.BA +DRAM_CLK <= sdram_pll:u6.c1 +DRAM_CKE <= Sdram_Control_4Port:u7.CKE +VGA_HS <= VGA_Controller:u1.oVGA_H_SYNC +VGA_VS <= VGA_Controller:u1.oVGA_V_SYNC +VGA_R[0] <= VGA_Controller:u1.oVGA_R +VGA_R[1] <= VGA_Controller:u1.oVGA_R +VGA_R[2] <= VGA_Controller:u1.oVGA_R +VGA_R[3] <= VGA_Controller:u1.oVGA_R +VGA_R[4] <= VGA_Controller:u1.oVGA_R +VGA_R[5] <= VGA_Controller:u1.oVGA_R +VGA_R[6] <= VGA_Controller:u1.oVGA_R +VGA_R[7] <= VGA_Controller:u1.oVGA_R +VGA_R[8] <= VGA_Controller:u1.oVGA_R +VGA_R[9] <= VGA_Controller:u1.oVGA_R +VGA_G[0] <= VGA_Controller:u1.oVGA_G +VGA_G[1] <= VGA_Controller:u1.oVGA_G +VGA_G[2] <= VGA_Controller:u1.oVGA_G +VGA_G[3] <= VGA_Controller:u1.oVGA_G +VGA_G[4] <= VGA_Controller:u1.oVGA_G +VGA_G[5] <= VGA_Controller:u1.oVGA_G +VGA_G[6] <= VGA_Controller:u1.oVGA_G +VGA_G[7] <= VGA_Controller:u1.oVGA_G +VGA_G[8] <= VGA_Controller:u1.oVGA_G +VGA_G[9] <= VGA_Controller:u1.oVGA_G +VGA_B[0] <= VGA_Controller:u1.oVGA_B +VGA_B[1] <= VGA_Controller:u1.oVGA_B +VGA_B[2] <= VGA_Controller:u1.oVGA_B +VGA_B[3] <= VGA_Controller:u1.oVGA_B +VGA_B[4] <= VGA_Controller:u1.oVGA_B +VGA_B[5] <= VGA_Controller:u1.oVGA_B +VGA_B[6] <= VGA_Controller:u1.oVGA_B +VGA_B[7] <= VGA_Controller:u1.oVGA_B +VGA_B[8] <= VGA_Controller:u1.oVGA_B +VGA_B[9] <= VGA_Controller:u1.oVGA_B +VGA_CLK <= GPIO_1_CLKOUT[0].DB_MAX_OUTPUT_PORT_TYPE +VGA_X[0] <= VGA_Controller:u1.oVGA_Y +VGA_X[1] <= VGA_Controller:u1.oVGA_Y +VGA_X[2] <= VGA_Controller:u1.oVGA_Y +VGA_X[3] <= VGA_Controller:u1.oVGA_Y +VGA_X[4] <= VGA_Controller:u1.oVGA_Y +VGA_X[5] <= VGA_Controller:u1.oVGA_Y +VGA_X[6] <= VGA_Controller:u1.oVGA_Y +VGA_X[7] <= VGA_Controller:u1.oVGA_Y +VGA_X[8] <= VGA_Controller:u1.oVGA_Y +VGA_X[9] <= VGA_Controller:u1.oVGA_Y +VGA_X[10] <= VGA_Controller:u1.oVGA_Y +VGA_X[11] <= VGA_Controller:u1.oVGA_Y +VGA_Y[0] <= VGA_Controller:u1.oVGA_X +VGA_Y[1] <= VGA_Controller:u1.oVGA_X +VGA_Y[2] <= VGA_Controller:u1.oVGA_X +VGA_Y[3] <= VGA_Controller:u1.oVGA_X +VGA_Y[4] <= VGA_Controller:u1.oVGA_X +VGA_Y[5] <= VGA_Controller:u1.oVGA_X +VGA_Y[6] <= VGA_Controller:u1.oVGA_X +VGA_Y[7] <= VGA_Controller:u1.oVGA_X +VGA_Y[8] <= VGA_Controller:u1.oVGA_X +VGA_Y[9] <= VGA_Controller:u1.oVGA_X +VGA_Y[10] <= VGA_Controller:u1.oVGA_X +VGA_Y[11] <= VGA_Controller:u1.oVGA_X +VGA_ACTIVE <= VGA_Controller:u1.oVGA_ACTIVE +GPIO_1_CLKIN[0] => CCD_PIXCLK.IN2 +GPIO_1_CLKIN[1] => ~NO_FANOUT~ +GPIO_1_CLKOUT[0] <= GPIO_1_CLKOUT[0].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1_CLKOUT[1] <= <GND> +GPIO_1[12] <> <UNC> +GPIO_1[13] <> <UNC> +GPIO_1[14] <> GPIO_1[14] +GPIO_1[15] <> <VCC> +GPIO_1[16] <> <UNC> +GPIO_1[19] <> I2C_CCD_Config:u8.I2C_SDAT +GPIO_1[20] <> I2C_CCD_Config:u8.I2C_SCLK +GPIO_1[21] <> <UNC> +GPIO_1[22] <> <UNC> +GPIO_1[23] <> <UNC> +GPIO_1[24] <> <UNC> +GPIO_1[25] <> <UNC> +GPIO_1[26] <> <UNC> +GPIO_1[27] <> <UNC> +GPIO_1[28] <> <UNC> +GPIO_1[29] <> <UNC> +GPIO_1[30] <> <UNC> +GPIO_1[31] <> <UNC> + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1 +iRed[0] => oVGA_R.DATAB +iRed[1] => oVGA_R.DATAB +iRed[2] => oVGA_R.DATAB +iRed[3] => oVGA_R.DATAB +iRed[4] => oVGA_R.DATAB +iRed[5] => oVGA_R.DATAB +iRed[6] => oVGA_R.DATAB +iRed[7] => oVGA_R.DATAB +iRed[8] => oVGA_R.DATAB +iRed[9] => oVGA_R.DATAB +iGreen[0] => oVGA_G.DATAB +iGreen[1] => oVGA_G.DATAB +iGreen[2] => oVGA_G.DATAB +iGreen[3] => oVGA_G.DATAB +iGreen[4] => oVGA_G.DATAB +iGreen[5] => oVGA_G.DATAB +iGreen[6] => oVGA_G.DATAB +iGreen[7] => oVGA_G.DATAB +iGreen[8] => oVGA_G.DATAB +iGreen[9] => oVGA_G.DATAB +iBlue[0] => oVGA_B.DATAB +iBlue[1] => oVGA_B.DATAB +iBlue[2] => oVGA_B.DATAB +iBlue[3] => oVGA_B.DATAB +iBlue[4] => oVGA_B.DATAB +iBlue[5] => oVGA_B.DATAB +iBlue[6] => oVGA_B.DATAB +iBlue[7] => oVGA_B.DATAB +iBlue[8] => oVGA_B.DATAB +iBlue[9] => oVGA_B.DATAB +oRequest <= oRequest~reg0.DB_MAX_OUTPUT_PORT_TYPE +oVGA_R[0] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE +oVGA_R[1] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE +oVGA_R[2] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE +oVGA_R[3] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE +oVGA_R[4] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE +oVGA_R[5] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE +oVGA_R[6] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE +oVGA_R[7] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE +oVGA_R[8] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE +oVGA_R[9] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE +oVGA_G[0] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE +oVGA_G[1] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE +oVGA_G[2] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE +oVGA_G[3] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE +oVGA_G[4] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE +oVGA_G[5] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE +oVGA_G[6] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE +oVGA_G[7] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE +oVGA_G[8] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE +oVGA_G[9] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE +oVGA_B[0] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE +oVGA_B[1] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE +oVGA_B[2] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE +oVGA_B[3] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE +oVGA_B[4] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE +oVGA_B[5] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE +oVGA_B[6] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE +oVGA_B[7] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE +oVGA_B[8] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE +oVGA_B[9] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE +oVGA_H_SYNC <= oVGA_H_SYNC~reg0.DB_MAX_OUTPUT_PORT_TYPE +oVGA_V_SYNC <= oVGA_V_SYNC~reg0.DB_MAX_OUTPUT_PORT_TYPE +oVGA_SYNC <= <GND> +oVGA_BLANK <= oVGA_BLANK.DB_MAX_OUTPUT_PORT_TYPE +oVGA_CLOCK <= iCLK.DB_MAX_OUTPUT_PORT_TYPE +oVGA_X[0] <= H_Cont[0].DB_MAX_OUTPUT_PORT_TYPE +oVGA_X[1] <= H_Cont[1].DB_MAX_OUTPUT_PORT_TYPE +oVGA_X[2] <= H_Cont[2].DB_MAX_OUTPUT_PORT_TYPE +oVGA_X[3] <= H_Cont[3].DB_MAX_OUTPUT_PORT_TYPE +oVGA_X[4] <= H_Cont[4].DB_MAX_OUTPUT_PORT_TYPE +oVGA_X[5] <= H_Cont[5].DB_MAX_OUTPUT_PORT_TYPE +oVGA_X[6] <= H_Cont[6].DB_MAX_OUTPUT_PORT_TYPE +oVGA_X[7] <= H_Cont[7].DB_MAX_OUTPUT_PORT_TYPE +oVGA_X[8] <= H_Cont[8].DB_MAX_OUTPUT_PORT_TYPE +oVGA_X[9] <= H_Cont[9].DB_MAX_OUTPUT_PORT_TYPE +oVGA_X[10] <= H_Cont[10].DB_MAX_OUTPUT_PORT_TYPE +oVGA_X[11] <= H_Cont[11].DB_MAX_OUTPUT_PORT_TYPE +oVGA_Y[0] <= V_Cont[0].DB_MAX_OUTPUT_PORT_TYPE +oVGA_Y[1] <= V_Cont[1].DB_MAX_OUTPUT_PORT_TYPE +oVGA_Y[2] <= V_Cont[2].DB_MAX_OUTPUT_PORT_TYPE +oVGA_Y[3] <= V_Cont[3].DB_MAX_OUTPUT_PORT_TYPE +oVGA_Y[4] <= V_Cont[4].DB_MAX_OUTPUT_PORT_TYPE +oVGA_Y[5] <= V_Cont[5].DB_MAX_OUTPUT_PORT_TYPE +oVGA_Y[6] <= V_Cont[6].DB_MAX_OUTPUT_PORT_TYPE +oVGA_Y[7] <= V_Cont[7].DB_MAX_OUTPUT_PORT_TYPE +oVGA_Y[8] <= V_Cont[8].DB_MAX_OUTPUT_PORT_TYPE +oVGA_Y[9] <= V_Cont[9].DB_MAX_OUTPUT_PORT_TYPE +oVGA_Y[10] <= V_Cont[10].DB_MAX_OUTPUT_PORT_TYPE +oVGA_Y[11] <= V_Cont[11].DB_MAX_OUTPUT_PORT_TYPE +oVGA_ACTIVE <= active.DB_MAX_OUTPUT_PORT_TYPE +iCLK => oVGA_V_SYNC~reg0.CLK +iCLK => V_Cont[0].CLK +iCLK => V_Cont[1].CLK +iCLK => V_Cont[2].CLK +iCLK => V_Cont[3].CLK +iCLK => V_Cont[4].CLK +iCLK => V_Cont[5].CLK +iCLK => V_Cont[6].CLK +iCLK => V_Cont[7].CLK +iCLK => V_Cont[8].CLK +iCLK => V_Cont[9].CLK +iCLK => V_Cont[10].CLK +iCLK => V_Cont[11].CLK +iCLK => active.CLK +iCLK => oVGA_H_SYNC~reg0.CLK +iCLK => H_Cont[0].CLK +iCLK => H_Cont[1].CLK +iCLK => H_Cont[2].CLK +iCLK => H_Cont[3].CLK +iCLK => H_Cont[4].CLK +iCLK => H_Cont[5].CLK +iCLK => H_Cont[6].CLK +iCLK => H_Cont[7].CLK +iCLK => H_Cont[8].CLK +iCLK => H_Cont[9].CLK +iCLK => H_Cont[10].CLK +iCLK => H_Cont[11].CLK +iCLK => oRequest~reg0.CLK +iCLK => oVGA_CLOCK.DATAIN +iRST_N => active.ACLR +iRST_N => oVGA_H_SYNC~reg0.ACLR +iRST_N => H_Cont[0].ACLR +iRST_N => H_Cont[1].ACLR +iRST_N => H_Cont[2].ACLR +iRST_N => H_Cont[3].ACLR +iRST_N => H_Cont[4].ACLR +iRST_N => H_Cont[5].ACLR +iRST_N => H_Cont[6].ACLR +iRST_N => H_Cont[7].ACLR +iRST_N => H_Cont[8].ACLR +iRST_N => H_Cont[9].ACLR +iRST_N => H_Cont[10].ACLR +iRST_N => H_Cont[11].ACLR +iRST_N => oRequest~reg0.ACLR +iRST_N => oVGA_V_SYNC~reg0.ACLR +iRST_N => V_Cont[0].ACLR +iRST_N => V_Cont[1].ACLR +iRST_N => V_Cont[2].ACLR +iRST_N => V_Cont[3].ACLR +iRST_N => V_Cont[4].ACLR +iRST_N => V_Cont[5].ACLR +iRST_N => V_Cont[6].ACLR +iRST_N => V_Cont[7].ACLR +iRST_N => V_Cont[8].ACLR +iRST_N => V_Cont[9].ACLR +iRST_N => V_Cont[10].ACLR +iRST_N => V_Cont[11].ACLR + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Reset_Delay:u2 +iCLK => oRST_2~reg0.CLK +iCLK => oRST_1~reg0.CLK +iCLK => oRST_0~reg0.CLK +iCLK => Cont[0].CLK +iCLK => Cont[1].CLK +iCLK => Cont[2].CLK +iCLK => Cont[3].CLK +iCLK => Cont[4].CLK +iCLK => Cont[5].CLK +iCLK => Cont[6].CLK +iCLK => Cont[7].CLK +iCLK => Cont[8].CLK +iCLK => Cont[9].CLK +iCLK => Cont[10].CLK +iCLK => Cont[11].CLK +iCLK => Cont[12].CLK +iCLK => Cont[13].CLK +iCLK => Cont[14].CLK +iCLK => Cont[15].CLK +iCLK => Cont[16].CLK +iCLK => Cont[17].CLK +iCLK => Cont[18].CLK +iCLK => Cont[19].CLK +iCLK => Cont[20].CLK +iCLK => Cont[21].CLK +iCLK => Cont[22].CLK +iCLK => Cont[23].CLK +iCLK => Cont[24].CLK +iCLK => Cont[25].CLK +iCLK => Cont[26].CLK +iCLK => Cont[27].CLK +iCLK => Cont[28].CLK +iCLK => Cont[29].CLK +iCLK => Cont[30].CLK +iCLK => Cont[31].CLK +iRST => oRST_2~reg0.ACLR +iRST => oRST_1~reg0.ACLR +iRST => oRST_0~reg0.ACLR +iRST => Cont[0].ACLR +iRST => Cont[1].ACLR +iRST => Cont[2].ACLR +iRST => Cont[3].ACLR +iRST => Cont[4].ACLR +iRST => Cont[5].ACLR +iRST => Cont[6].ACLR +iRST => Cont[7].ACLR +iRST => Cont[8].ACLR +iRST => Cont[9].ACLR +iRST => Cont[10].ACLR +iRST => Cont[11].ACLR +iRST => Cont[12].ACLR +iRST => Cont[13].ACLR +iRST => Cont[14].ACLR +iRST => Cont[15].ACLR +iRST => Cont[16].ACLR +iRST => Cont[17].ACLR +iRST => Cont[18].ACLR +iRST => Cont[19].ACLR +iRST => Cont[20].ACLR +iRST => Cont[21].ACLR +iRST => Cont[22].ACLR +iRST => Cont[23].ACLR +iRST => Cont[24].ACLR +iRST => Cont[25].ACLR +iRST => Cont[26].ACLR +iRST => Cont[27].ACLR +iRST => Cont[28].ACLR +iRST => Cont[29].ACLR +iRST => Cont[30].ACLR +iRST => Cont[31].ACLR +oRST_0 <= oRST_0~reg0.DB_MAX_OUTPUT_PORT_TYPE +oRST_1 <= oRST_1~reg0.DB_MAX_OUTPUT_PORT_TYPE +oRST_2 <= oRST_2~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3 +oDATA[0] <= mCCD_DATA[0].DB_MAX_OUTPUT_PORT_TYPE +oDATA[1] <= mCCD_DATA[1].DB_MAX_OUTPUT_PORT_TYPE +oDATA[2] <= mCCD_DATA[2].DB_MAX_OUTPUT_PORT_TYPE +oDATA[3] <= mCCD_DATA[3].DB_MAX_OUTPUT_PORT_TYPE +oDATA[4] <= mCCD_DATA[4].DB_MAX_OUTPUT_PORT_TYPE +oDATA[5] <= mCCD_DATA[5].DB_MAX_OUTPUT_PORT_TYPE +oDATA[6] <= mCCD_DATA[6].DB_MAX_OUTPUT_PORT_TYPE +oDATA[7] <= mCCD_DATA[7].DB_MAX_OUTPUT_PORT_TYPE +oDATA[8] <= mCCD_DATA[8].DB_MAX_OUTPUT_PORT_TYPE +oDATA[9] <= mCCD_DATA[9].DB_MAX_OUTPUT_PORT_TYPE +oDATA[10] <= mCCD_DATA[10].DB_MAX_OUTPUT_PORT_TYPE +oDATA[11] <= mCCD_DATA[11].DB_MAX_OUTPUT_PORT_TYPE +oDVAL <= oDVAL.DB_MAX_OUTPUT_PORT_TYPE +oX_Cont[0] <= X_Cont[0].DB_MAX_OUTPUT_PORT_TYPE +oX_Cont[1] <= X_Cont[1].DB_MAX_OUTPUT_PORT_TYPE +oX_Cont[2] <= X_Cont[2].DB_MAX_OUTPUT_PORT_TYPE +oX_Cont[3] <= X_Cont[3].DB_MAX_OUTPUT_PORT_TYPE +oX_Cont[4] <= X_Cont[4].DB_MAX_OUTPUT_PORT_TYPE +oX_Cont[5] <= X_Cont[5].DB_MAX_OUTPUT_PORT_TYPE +oX_Cont[6] <= X_Cont[6].DB_MAX_OUTPUT_PORT_TYPE +oX_Cont[7] <= X_Cont[7].DB_MAX_OUTPUT_PORT_TYPE +oX_Cont[8] <= X_Cont[8].DB_MAX_OUTPUT_PORT_TYPE +oX_Cont[9] <= X_Cont[9].DB_MAX_OUTPUT_PORT_TYPE +oX_Cont[10] <= X_Cont[10].DB_MAX_OUTPUT_PORT_TYPE +oX_Cont[11] <= X_Cont[11].DB_MAX_OUTPUT_PORT_TYPE +oX_Cont[12] <= X_Cont[12].DB_MAX_OUTPUT_PORT_TYPE +oX_Cont[13] <= X_Cont[13].DB_MAX_OUTPUT_PORT_TYPE +oX_Cont[14] <= X_Cont[14].DB_MAX_OUTPUT_PORT_TYPE +oX_Cont[15] <= X_Cont[15].DB_MAX_OUTPUT_PORT_TYPE +oY_Cont[0] <= Y_Cont[0].DB_MAX_OUTPUT_PORT_TYPE +oY_Cont[1] <= Y_Cont[1].DB_MAX_OUTPUT_PORT_TYPE +oY_Cont[2] <= Y_Cont[2].DB_MAX_OUTPUT_PORT_TYPE +oY_Cont[3] <= Y_Cont[3].DB_MAX_OUTPUT_PORT_TYPE +oY_Cont[4] <= Y_Cont[4].DB_MAX_OUTPUT_PORT_TYPE +oY_Cont[5] <= Y_Cont[5].DB_MAX_OUTPUT_PORT_TYPE +oY_Cont[6] <= Y_Cont[6].DB_MAX_OUTPUT_PORT_TYPE +oY_Cont[7] <= Y_Cont[7].DB_MAX_OUTPUT_PORT_TYPE +oY_Cont[8] <= Y_Cont[8].DB_MAX_OUTPUT_PORT_TYPE +oY_Cont[9] <= Y_Cont[9].DB_MAX_OUTPUT_PORT_TYPE +oY_Cont[10] <= Y_Cont[10].DB_MAX_OUTPUT_PORT_TYPE +oY_Cont[11] <= Y_Cont[11].DB_MAX_OUTPUT_PORT_TYPE +oY_Cont[12] <= Y_Cont[12].DB_MAX_OUTPUT_PORT_TYPE +oY_Cont[13] <= Y_Cont[13].DB_MAX_OUTPUT_PORT_TYPE +oY_Cont[14] <= Y_Cont[14].DB_MAX_OUTPUT_PORT_TYPE +oY_Cont[15] <= Y_Cont[15].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[0] <= Frame_Cont[0].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[1] <= Frame_Cont[1].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[2] <= Frame_Cont[2].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[3] <= Frame_Cont[3].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[4] <= Frame_Cont[4].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[5] <= Frame_Cont[5].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[6] <= Frame_Cont[6].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[7] <= Frame_Cont[7].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[8] <= Frame_Cont[8].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[9] <= Frame_Cont[9].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[10] <= Frame_Cont[10].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[11] <= Frame_Cont[11].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[12] <= Frame_Cont[12].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[13] <= Frame_Cont[13].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[14] <= Frame_Cont[14].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[15] <= Frame_Cont[15].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[16] <= Frame_Cont[16].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[17] <= Frame_Cont[17].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[18] <= Frame_Cont[18].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[19] <= Frame_Cont[19].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[20] <= Frame_Cont[20].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[21] <= Frame_Cont[21].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[22] <= Frame_Cont[22].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[23] <= Frame_Cont[23].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[24] <= Frame_Cont[24].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[25] <= Frame_Cont[25].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[26] <= Frame_Cont[26].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[27] <= Frame_Cont[27].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[28] <= Frame_Cont[28].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[29] <= Frame_Cont[29].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[30] <= Frame_Cont[30].DB_MAX_OUTPUT_PORT_TYPE +oFrame_Cont[31] <= Frame_Cont[31].DB_MAX_OUTPUT_PORT_TYPE +iDATA[0] => mCCD_DATA.DATAB +iDATA[1] => mCCD_DATA.DATAB +iDATA[2] => mCCD_DATA.DATAB +iDATA[3] => mCCD_DATA.DATAB +iDATA[4] => mCCD_DATA.DATAB +iDATA[5] => mCCD_DATA.DATAB +iDATA[6] => mCCD_DATA.DATAB +iDATA[7] => mCCD_DATA.DATAB +iDATA[8] => mCCD_DATA.DATAB +iDATA[9] => mCCD_DATA.DATAB +iDATA[10] => mCCD_DATA.DATAB +iDATA[11] => mCCD_DATA.DATAB +iFVAL => Pre_FVAL.DATAIN +iFVAL => Equal0.IN1 +iFVAL => Equal1.IN0 +iLVAL => mCCD_DATA.OUTPUTSELECT +iLVAL => mCCD_DATA.OUTPUTSELECT +iLVAL => mCCD_DATA.OUTPUTSELECT +iLVAL => mCCD_DATA.OUTPUTSELECT +iLVAL => mCCD_DATA.OUTPUTSELECT +iLVAL => mCCD_DATA.OUTPUTSELECT +iLVAL => mCCD_DATA.OUTPUTSELECT +iLVAL => mCCD_DATA.OUTPUTSELECT +iLVAL => mCCD_DATA.OUTPUTSELECT +iLVAL => mCCD_DATA.OUTPUTSELECT +iLVAL => mCCD_DATA.OUTPUTSELECT +iLVAL => mCCD_DATA.OUTPUTSELECT +iLVAL => mCCD_LVAL.DATAIN +iSTART => mSTART.OUTPUTSELECT +iEND => mSTART.OUTPUTSELECT +iCLK => mCCD_DATA[0].CLK +iCLK => mCCD_DATA[1].CLK +iCLK => mCCD_DATA[2].CLK +iCLK => mCCD_DATA[3].CLK +iCLK => mCCD_DATA[4].CLK +iCLK => mCCD_DATA[5].CLK +iCLK => mCCD_DATA[6].CLK +iCLK => mCCD_DATA[7].CLK +iCLK => mCCD_DATA[8].CLK +iCLK => mCCD_DATA[9].CLK +iCLK => mCCD_DATA[10].CLK +iCLK => mCCD_DATA[11].CLK +iCLK => Frame_Cont[0].CLK +iCLK => Frame_Cont[1].CLK +iCLK => Frame_Cont[2].CLK +iCLK => Frame_Cont[3].CLK +iCLK => Frame_Cont[4].CLK +iCLK => Frame_Cont[5].CLK +iCLK => Frame_Cont[6].CLK +iCLK => Frame_Cont[7].CLK +iCLK => Frame_Cont[8].CLK +iCLK => Frame_Cont[9].CLK +iCLK => Frame_Cont[10].CLK +iCLK => Frame_Cont[11].CLK +iCLK => Frame_Cont[12].CLK +iCLK => Frame_Cont[13].CLK +iCLK => Frame_Cont[14].CLK +iCLK => Frame_Cont[15].CLK +iCLK => Frame_Cont[16].CLK +iCLK => Frame_Cont[17].CLK +iCLK => Frame_Cont[18].CLK +iCLK => Frame_Cont[19].CLK +iCLK => Frame_Cont[20].CLK +iCLK => Frame_Cont[21].CLK +iCLK => Frame_Cont[22].CLK +iCLK => Frame_Cont[23].CLK +iCLK => Frame_Cont[24].CLK +iCLK => Frame_Cont[25].CLK +iCLK => Frame_Cont[26].CLK +iCLK => Frame_Cont[27].CLK +iCLK => Frame_Cont[28].CLK +iCLK => Frame_Cont[29].CLK +iCLK => Frame_Cont[30].CLK +iCLK => Frame_Cont[31].CLK +iCLK => Y_Cont[0].CLK +iCLK => Y_Cont[1].CLK +iCLK => Y_Cont[2].CLK +iCLK => Y_Cont[3].CLK +iCLK => Y_Cont[4].CLK +iCLK => Y_Cont[5].CLK +iCLK => Y_Cont[6].CLK +iCLK => Y_Cont[7].CLK +iCLK => Y_Cont[8].CLK +iCLK => Y_Cont[9].CLK +iCLK => Y_Cont[10].CLK +iCLK => Y_Cont[11].CLK +iCLK => Y_Cont[12].CLK +iCLK => Y_Cont[13].CLK +iCLK => Y_Cont[14].CLK +iCLK => Y_Cont[15].CLK +iCLK => X_Cont[0].CLK +iCLK => X_Cont[1].CLK +iCLK => X_Cont[2].CLK +iCLK => X_Cont[3].CLK +iCLK => X_Cont[4].CLK +iCLK => X_Cont[5].CLK +iCLK => X_Cont[6].CLK +iCLK => X_Cont[7].CLK +iCLK => X_Cont[8].CLK +iCLK => X_Cont[9].CLK +iCLK => X_Cont[10].CLK +iCLK => X_Cont[11].CLK +iCLK => X_Cont[12].CLK +iCLK => X_Cont[13].CLK +iCLK => X_Cont[14].CLK +iCLK => X_Cont[15].CLK +iCLK => mCCD_LVAL.CLK +iCLK => mCCD_FVAL.CLK +iCLK => Pre_FVAL.CLK +iCLK => mSTART.CLK +iRST => Y_Cont[0].ACLR +iRST => Y_Cont[1].ACLR +iRST => Y_Cont[2].ACLR +iRST => Y_Cont[3].ACLR +iRST => Y_Cont[4].ACLR +iRST => Y_Cont[5].ACLR +iRST => Y_Cont[6].ACLR +iRST => Y_Cont[7].ACLR +iRST => Y_Cont[8].ACLR +iRST => Y_Cont[9].ACLR +iRST => Y_Cont[10].ACLR +iRST => Y_Cont[11].ACLR +iRST => Y_Cont[12].ACLR +iRST => Y_Cont[13].ACLR +iRST => Y_Cont[14].ACLR +iRST => Y_Cont[15].ACLR +iRST => X_Cont[0].ACLR +iRST => X_Cont[1].ACLR +iRST => X_Cont[2].ACLR +iRST => X_Cont[3].ACLR +iRST => X_Cont[4].ACLR +iRST => X_Cont[5].ACLR +iRST => X_Cont[6].ACLR +iRST => X_Cont[7].ACLR +iRST => X_Cont[8].ACLR +iRST => X_Cont[9].ACLR +iRST => X_Cont[10].ACLR +iRST => X_Cont[11].ACLR +iRST => X_Cont[12].ACLR +iRST => X_Cont[13].ACLR +iRST => X_Cont[14].ACLR +iRST => X_Cont[15].ACLR +iRST => mCCD_LVAL.ACLR +iRST => mCCD_FVAL.ACLR +iRST => Pre_FVAL.ACLR +iRST => mCCD_DATA[0].ACLR +iRST => mCCD_DATA[1].ACLR +iRST => mCCD_DATA[2].ACLR +iRST => mCCD_DATA[3].ACLR +iRST => mCCD_DATA[4].ACLR +iRST => mCCD_DATA[5].ACLR +iRST => mCCD_DATA[6].ACLR +iRST => mCCD_DATA[7].ACLR +iRST => mCCD_DATA[8].ACLR +iRST => mCCD_DATA[9].ACLR +iRST => mCCD_DATA[10].ACLR +iRST => mCCD_DATA[11].ACLR +iRST => Frame_Cont[0].ACLR +iRST => Frame_Cont[1].ACLR +iRST => Frame_Cont[2].ACLR +iRST => Frame_Cont[3].ACLR +iRST => Frame_Cont[4].ACLR +iRST => Frame_Cont[5].ACLR +iRST => Frame_Cont[6].ACLR +iRST => Frame_Cont[7].ACLR +iRST => Frame_Cont[8].ACLR +iRST => Frame_Cont[9].ACLR +iRST => Frame_Cont[10].ACLR +iRST => Frame_Cont[11].ACLR +iRST => Frame_Cont[12].ACLR +iRST => Frame_Cont[13].ACLR +iRST => Frame_Cont[14].ACLR +iRST => Frame_Cont[15].ACLR +iRST => Frame_Cont[16].ACLR +iRST => Frame_Cont[17].ACLR +iRST => Frame_Cont[18].ACLR +iRST => Frame_Cont[19].ACLR +iRST => Frame_Cont[20].ACLR +iRST => Frame_Cont[21].ACLR +iRST => Frame_Cont[22].ACLR +iRST => Frame_Cont[23].ACLR +iRST => Frame_Cont[24].ACLR +iRST => Frame_Cont[25].ACLR +iRST => Frame_Cont[26].ACLR +iRST => Frame_Cont[27].ACLR +iRST => Frame_Cont[28].ACLR +iRST => Frame_Cont[29].ACLR +iRST => Frame_Cont[30].ACLR +iRST => Frame_Cont[31].ACLR +iRST => mSTART.ACLR + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4 +oRed[0] <= mCCD_R[0].DB_MAX_OUTPUT_PORT_TYPE +oRed[1] <= mCCD_R[1].DB_MAX_OUTPUT_PORT_TYPE +oRed[2] <= mCCD_R[2].DB_MAX_OUTPUT_PORT_TYPE +oRed[3] <= mCCD_R[3].DB_MAX_OUTPUT_PORT_TYPE +oRed[4] <= mCCD_R[4].DB_MAX_OUTPUT_PORT_TYPE +oRed[5] <= mCCD_R[5].DB_MAX_OUTPUT_PORT_TYPE +oRed[6] <= mCCD_R[6].DB_MAX_OUTPUT_PORT_TYPE +oRed[7] <= mCCD_R[7].DB_MAX_OUTPUT_PORT_TYPE +oRed[8] <= mCCD_R[8].DB_MAX_OUTPUT_PORT_TYPE +oRed[9] <= mCCD_R[9].DB_MAX_OUTPUT_PORT_TYPE +oRed[10] <= mCCD_R[10].DB_MAX_OUTPUT_PORT_TYPE +oRed[11] <= mCCD_R[11].DB_MAX_OUTPUT_PORT_TYPE +oGreen[0] <= mCCD_G[1].DB_MAX_OUTPUT_PORT_TYPE +oGreen[1] <= mCCD_G[2].DB_MAX_OUTPUT_PORT_TYPE +oGreen[2] <= mCCD_G[3].DB_MAX_OUTPUT_PORT_TYPE +oGreen[3] <= mCCD_G[4].DB_MAX_OUTPUT_PORT_TYPE +oGreen[4] <= mCCD_G[5].DB_MAX_OUTPUT_PORT_TYPE +oGreen[5] <= mCCD_G[6].DB_MAX_OUTPUT_PORT_TYPE +oGreen[6] <= mCCD_G[7].DB_MAX_OUTPUT_PORT_TYPE +oGreen[7] <= mCCD_G[8].DB_MAX_OUTPUT_PORT_TYPE +oGreen[8] <= mCCD_G[9].DB_MAX_OUTPUT_PORT_TYPE +oGreen[9] <= mCCD_G[10].DB_MAX_OUTPUT_PORT_TYPE +oGreen[10] <= mCCD_G[11].DB_MAX_OUTPUT_PORT_TYPE +oGreen[11] <= mCCD_G[12].DB_MAX_OUTPUT_PORT_TYPE +oBlue[0] <= mCCD_B[0].DB_MAX_OUTPUT_PORT_TYPE +oBlue[1] <= mCCD_B[1].DB_MAX_OUTPUT_PORT_TYPE +oBlue[2] <= mCCD_B[2].DB_MAX_OUTPUT_PORT_TYPE +oBlue[3] <= mCCD_B[3].DB_MAX_OUTPUT_PORT_TYPE +oBlue[4] <= mCCD_B[4].DB_MAX_OUTPUT_PORT_TYPE +oBlue[5] <= mCCD_B[5].DB_MAX_OUTPUT_PORT_TYPE +oBlue[6] <= mCCD_B[6].DB_MAX_OUTPUT_PORT_TYPE +oBlue[7] <= mCCD_B[7].DB_MAX_OUTPUT_PORT_TYPE +oBlue[8] <= mCCD_B[8].DB_MAX_OUTPUT_PORT_TYPE +oBlue[9] <= mCCD_B[9].DB_MAX_OUTPUT_PORT_TYPE +oBlue[10] <= mCCD_B[10].DB_MAX_OUTPUT_PORT_TYPE +oBlue[11] <= mCCD_B[11].DB_MAX_OUTPUT_PORT_TYPE +oDVAL <= mDVAL.DB_MAX_OUTPUT_PORT_TYPE +iX_Cont[0] => mDVAL.IN0 +iX_Cont[0] => Equal0.IN1 +iX_Cont[0] => Equal1.IN1 +iX_Cont[0] => Equal2.IN1 +iX_Cont[0] => Equal3.IN0 +iX_Cont[1] => ~NO_FANOUT~ +iX_Cont[2] => ~NO_FANOUT~ +iX_Cont[3] => ~NO_FANOUT~ +iX_Cont[4] => ~NO_FANOUT~ +iX_Cont[5] => ~NO_FANOUT~ +iX_Cont[6] => ~NO_FANOUT~ +iX_Cont[7] => ~NO_FANOUT~ +iX_Cont[8] => ~NO_FANOUT~ +iX_Cont[9] => ~NO_FANOUT~ +iX_Cont[10] => ~NO_FANOUT~ +iY_Cont[0] => mDVAL.IN1 +iY_Cont[0] => Equal0.IN0 +iY_Cont[0] => Equal1.IN0 +iY_Cont[0] => Equal2.IN0 +iY_Cont[0] => Equal3.IN1 +iY_Cont[1] => ~NO_FANOUT~ +iY_Cont[2] => ~NO_FANOUT~ +iY_Cont[3] => ~NO_FANOUT~ +iY_Cont[4] => ~NO_FANOUT~ +iY_Cont[5] => ~NO_FANOUT~ +iY_Cont[6] => ~NO_FANOUT~ +iY_Cont[7] => ~NO_FANOUT~ +iY_Cont[8] => ~NO_FANOUT~ +iY_Cont[9] => ~NO_FANOUT~ +iY_Cont[10] => ~NO_FANOUT~ +iDATA[0] => iDATA[0].IN1 +iDATA[1] => iDATA[1].IN1 +iDATA[2] => iDATA[2].IN1 +iDATA[3] => iDATA[3].IN1 +iDATA[4] => iDATA[4].IN1 +iDATA[5] => iDATA[5].IN1 +iDATA[6] => iDATA[6].IN1 +iDATA[7] => iDATA[7].IN1 +iDATA[8] => iDATA[8].IN1 +iDATA[9] => iDATA[9].IN1 +iDATA[10] => iDATA[10].IN1 +iDATA[11] => iDATA[11].IN1 +iDVAL => iDVAL.IN1 +iCLK => iCLK.IN1 +iRST => mDVAL.ACLR +iRST => mDATAd_1[0].ACLR +iRST => mDATAd_1[1].ACLR +iRST => mDATAd_1[2].ACLR +iRST => mDATAd_1[3].ACLR +iRST => mDATAd_1[4].ACLR +iRST => mDATAd_1[5].ACLR +iRST => mDATAd_1[6].ACLR +iRST => mDATAd_1[7].ACLR +iRST => mDATAd_1[8].ACLR +iRST => mDATAd_1[9].ACLR +iRST => mDATAd_1[10].ACLR +iRST => mDATAd_1[11].ACLR +iRST => mDATAd_0[0].ACLR +iRST => mDATAd_0[1].ACLR +iRST => mDATAd_0[2].ACLR +iRST => mDATAd_0[3].ACLR +iRST => mDATAd_0[4].ACLR +iRST => mDATAd_0[5].ACLR +iRST => mDATAd_0[6].ACLR +iRST => mDATAd_0[7].ACLR +iRST => mDATAd_0[8].ACLR +iRST => mDATAd_0[9].ACLR +iRST => mDATAd_0[10].ACLR +iRST => mDATAd_0[11].ACLR +iRST => mCCD_B[0].ACLR +iRST => mCCD_B[1].ACLR +iRST => mCCD_B[2].ACLR +iRST => mCCD_B[3].ACLR +iRST => mCCD_B[4].ACLR +iRST => mCCD_B[5].ACLR +iRST => mCCD_B[6].ACLR +iRST => mCCD_B[7].ACLR +iRST => mCCD_B[8].ACLR +iRST => mCCD_B[9].ACLR +iRST => mCCD_B[10].ACLR +iRST => mCCD_B[11].ACLR +iRST => mCCD_G[1].ACLR +iRST => mCCD_G[2].ACLR +iRST => mCCD_G[3].ACLR +iRST => mCCD_G[4].ACLR +iRST => mCCD_G[5].ACLR +iRST => mCCD_G[6].ACLR +iRST => mCCD_G[7].ACLR +iRST => mCCD_G[8].ACLR +iRST => mCCD_G[9].ACLR +iRST => mCCD_G[10].ACLR +iRST => mCCD_G[11].ACLR +iRST => mCCD_G[12].ACLR +iRST => mCCD_R[0].ACLR +iRST => mCCD_R[1].ACLR +iRST => mCCD_R[2].ACLR +iRST => mCCD_R[3].ACLR +iRST => mCCD_R[4].ACLR +iRST => mCCD_R[5].ACLR +iRST => mCCD_R[6].ACLR +iRST => mCCD_R[7].ACLR +iRST => mCCD_R[8].ACLR +iRST => mCCD_R[9].ACLR +iRST => mCCD_R[10].ACLR +iRST => mCCD_R[11].ACLR + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0 +clken => clken.IN1 +clock => clock.IN1 +shiftin[0] => shiftin[0].IN1 +shiftin[1] => shiftin[1].IN1 +shiftin[2] => shiftin[2].IN1 +shiftin[3] => shiftin[3].IN1 +shiftin[4] => shiftin[4].IN1 +shiftin[5] => shiftin[5].IN1 +shiftin[6] => shiftin[6].IN1 +shiftin[7] => shiftin[7].IN1 +shiftin[8] => shiftin[8].IN1 +shiftin[9] => shiftin[9].IN1 +shiftin[10] => shiftin[10].IN1 +shiftin[11] => shiftin[11].IN1 +shiftout[0] <= altshift_taps:altshift_taps_component.shiftout +shiftout[1] <= altshift_taps:altshift_taps_component.shiftout +shiftout[2] <= altshift_taps:altshift_taps_component.shiftout +shiftout[3] <= altshift_taps:altshift_taps_component.shiftout +shiftout[4] <= altshift_taps:altshift_taps_component.shiftout +shiftout[5] <= altshift_taps:altshift_taps_component.shiftout +shiftout[6] <= altshift_taps:altshift_taps_component.shiftout +shiftout[7] <= altshift_taps:altshift_taps_component.shiftout +shiftout[8] <= altshift_taps:altshift_taps_component.shiftout +shiftout[9] <= altshift_taps:altshift_taps_component.shiftout +shiftout[10] <= altshift_taps:altshift_taps_component.shiftout +shiftout[11] <= altshift_taps:altshift_taps_component.shiftout +taps0x[0] <= altshift_taps:altshift_taps_component.taps +taps0x[1] <= altshift_taps:altshift_taps_component.taps +taps0x[2] <= altshift_taps:altshift_taps_component.taps +taps0x[3] <= altshift_taps:altshift_taps_component.taps +taps0x[4] <= altshift_taps:altshift_taps_component.taps +taps0x[5] <= altshift_taps:altshift_taps_component.taps +taps0x[6] <= altshift_taps:altshift_taps_component.taps +taps0x[7] <= altshift_taps:altshift_taps_component.taps +taps0x[8] <= altshift_taps:altshift_taps_component.taps +taps0x[9] <= altshift_taps:altshift_taps_component.taps +taps0x[10] <= altshift_taps:altshift_taps_component.taps +taps0x[11] <= altshift_taps:altshift_taps_component.taps +taps1x[0] <= altshift_taps:altshift_taps_component.taps +taps1x[1] <= altshift_taps:altshift_taps_component.taps +taps1x[2] <= altshift_taps:altshift_taps_component.taps +taps1x[3] <= altshift_taps:altshift_taps_component.taps +taps1x[4] <= altshift_taps:altshift_taps_component.taps +taps1x[5] <= altshift_taps:altshift_taps_component.taps +taps1x[6] <= altshift_taps:altshift_taps_component.taps +taps1x[7] <= altshift_taps:altshift_taps_component.taps +taps1x[8] <= altshift_taps:altshift_taps_component.taps +taps1x[9] <= altshift_taps:altshift_taps_component.taps +taps1x[10] <= altshift_taps:altshift_taps_component.taps +taps1x[11] <= altshift_taps:altshift_taps_component.taps + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component +shiftin[0] => shift_taps_rnn:auto_generated.shiftin[0] +shiftin[1] => shift_taps_rnn:auto_generated.shiftin[1] +shiftin[2] => shift_taps_rnn:auto_generated.shiftin[2] +shiftin[3] => shift_taps_rnn:auto_generated.shiftin[3] +shiftin[4] => shift_taps_rnn:auto_generated.shiftin[4] +shiftin[5] => shift_taps_rnn:auto_generated.shiftin[5] +shiftin[6] => shift_taps_rnn:auto_generated.shiftin[6] +shiftin[7] => shift_taps_rnn:auto_generated.shiftin[7] +shiftin[8] => shift_taps_rnn:auto_generated.shiftin[8] +shiftin[9] => shift_taps_rnn:auto_generated.shiftin[9] +shiftin[10] => shift_taps_rnn:auto_generated.shiftin[10] +shiftin[11] => shift_taps_rnn:auto_generated.shiftin[11] +clock => shift_taps_rnn:auto_generated.clock +clken => shift_taps_rnn:auto_generated.clken +shiftout[0] <= shift_taps_rnn:auto_generated.shiftout[0] +shiftout[1] <= shift_taps_rnn:auto_generated.shiftout[1] +shiftout[2] <= shift_taps_rnn:auto_generated.shiftout[2] +shiftout[3] <= shift_taps_rnn:auto_generated.shiftout[3] +shiftout[4] <= shift_taps_rnn:auto_generated.shiftout[4] +shiftout[5] <= shift_taps_rnn:auto_generated.shiftout[5] +shiftout[6] <= shift_taps_rnn:auto_generated.shiftout[6] +shiftout[7] <= shift_taps_rnn:auto_generated.shiftout[7] +shiftout[8] <= shift_taps_rnn:auto_generated.shiftout[8] +shiftout[9] <= shift_taps_rnn:auto_generated.shiftout[9] +shiftout[10] <= shift_taps_rnn:auto_generated.shiftout[10] +shiftout[11] <= shift_taps_rnn:auto_generated.shiftout[11] +taps[0] <= shift_taps_rnn:auto_generated.taps[0] +taps[1] <= shift_taps_rnn:auto_generated.taps[1] +taps[2] <= shift_taps_rnn:auto_generated.taps[2] +taps[3] <= shift_taps_rnn:auto_generated.taps[3] +taps[4] <= shift_taps_rnn:auto_generated.taps[4] +taps[5] <= shift_taps_rnn:auto_generated.taps[5] +taps[6] <= shift_taps_rnn:auto_generated.taps[6] +taps[7] <= shift_taps_rnn:auto_generated.taps[7] +taps[8] <= shift_taps_rnn:auto_generated.taps[8] +taps[9] <= shift_taps_rnn:auto_generated.taps[9] +taps[10] <= shift_taps_rnn:auto_generated.taps[10] +taps[11] <= shift_taps_rnn:auto_generated.taps[11] +taps[12] <= shift_taps_rnn:auto_generated.taps[12] +taps[13] <= shift_taps_rnn:auto_generated.taps[13] +taps[14] <= shift_taps_rnn:auto_generated.taps[14] +taps[15] <= shift_taps_rnn:auto_generated.taps[15] +taps[16] <= shift_taps_rnn:auto_generated.taps[16] +taps[17] <= shift_taps_rnn:auto_generated.taps[17] +taps[18] <= shift_taps_rnn:auto_generated.taps[18] +taps[19] <= shift_taps_rnn:auto_generated.taps[19] +taps[20] <= shift_taps_rnn:auto_generated.taps[20] +taps[21] <= shift_taps_rnn:auto_generated.taps[21] +taps[22] <= shift_taps_rnn:auto_generated.taps[22] +taps[23] <= shift_taps_rnn:auto_generated.taps[23] +aclr => ~NO_FANOUT~ + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated +clken => altsyncram_lp81:altsyncram2.clocken0 +clken => cntr_cuf:cntr1.clk_en +clock => altsyncram_lp81:altsyncram2.clock0 +clock => cntr_cuf:cntr1.clock +shiftin[0] => altsyncram_lp81:altsyncram2.data_a[0] +shiftin[1] => altsyncram_lp81:altsyncram2.data_a[1] +shiftin[2] => altsyncram_lp81:altsyncram2.data_a[2] +shiftin[3] => altsyncram_lp81:altsyncram2.data_a[3] +shiftin[4] => altsyncram_lp81:altsyncram2.data_a[4] +shiftin[5] => altsyncram_lp81:altsyncram2.data_a[5] +shiftin[6] => altsyncram_lp81:altsyncram2.data_a[6] +shiftin[7] => altsyncram_lp81:altsyncram2.data_a[7] +shiftin[8] => altsyncram_lp81:altsyncram2.data_a[8] +shiftin[9] => altsyncram_lp81:altsyncram2.data_a[9] +shiftin[10] => altsyncram_lp81:altsyncram2.data_a[10] +shiftin[11] => altsyncram_lp81:altsyncram2.data_a[11] +shiftout[0] <= altsyncram_lp81:altsyncram2.q_b[12] +shiftout[1] <= altsyncram_lp81:altsyncram2.q_b[13] +shiftout[2] <= altsyncram_lp81:altsyncram2.q_b[14] +shiftout[3] <= altsyncram_lp81:altsyncram2.q_b[15] +shiftout[4] <= altsyncram_lp81:altsyncram2.q_b[16] +shiftout[5] <= altsyncram_lp81:altsyncram2.q_b[17] +shiftout[6] <= altsyncram_lp81:altsyncram2.q_b[18] +shiftout[7] <= altsyncram_lp81:altsyncram2.q_b[19] +shiftout[8] <= altsyncram_lp81:altsyncram2.q_b[20] +shiftout[9] <= altsyncram_lp81:altsyncram2.q_b[21] +shiftout[10] <= altsyncram_lp81:altsyncram2.q_b[22] +shiftout[11] <= altsyncram_lp81:altsyncram2.q_b[23] +taps[0] <= altsyncram_lp81:altsyncram2.q_b[0] +taps[1] <= altsyncram_lp81:altsyncram2.q_b[1] +taps[2] <= altsyncram_lp81:altsyncram2.q_b[2] +taps[3] <= altsyncram_lp81:altsyncram2.q_b[3] +taps[4] <= altsyncram_lp81:altsyncram2.q_b[4] +taps[5] <= altsyncram_lp81:altsyncram2.q_b[5] +taps[6] <= altsyncram_lp81:altsyncram2.q_b[6] +taps[7] <= altsyncram_lp81:altsyncram2.q_b[7] +taps[8] <= altsyncram_lp81:altsyncram2.q_b[8] +taps[9] <= altsyncram_lp81:altsyncram2.q_b[9] +taps[10] <= altsyncram_lp81:altsyncram2.q_b[10] +taps[11] <= altsyncram_lp81:altsyncram2.q_b[11] +taps[12] <= altsyncram_lp81:altsyncram2.q_b[12] +taps[13] <= altsyncram_lp81:altsyncram2.q_b[13] +taps[14] <= altsyncram_lp81:altsyncram2.q_b[14] +taps[15] <= altsyncram_lp81:altsyncram2.q_b[15] +taps[16] <= altsyncram_lp81:altsyncram2.q_b[16] +taps[17] <= altsyncram_lp81:altsyncram2.q_b[17] +taps[18] <= altsyncram_lp81:altsyncram2.q_b[18] +taps[19] <= altsyncram_lp81:altsyncram2.q_b[19] +taps[20] <= altsyncram_lp81:altsyncram2.q_b[20] +taps[21] <= altsyncram_lp81:altsyncram2.q_b[21] +taps[22] <= altsyncram_lp81:altsyncram2.q_b[22] +taps[23] <= altsyncram_lp81:altsyncram2.q_b[23] + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2 +address_a[0] => ram_block3a0.PORTAADDR +address_a[0] => ram_block3a1.PORTAADDR +address_a[0] => ram_block3a2.PORTAADDR +address_a[0] => ram_block3a3.PORTAADDR +address_a[0] => ram_block3a4.PORTAADDR +address_a[0] => ram_block3a5.PORTAADDR +address_a[0] => ram_block3a6.PORTAADDR +address_a[0] => ram_block3a7.PORTAADDR +address_a[0] => ram_block3a8.PORTAADDR +address_a[0] => ram_block3a9.PORTAADDR +address_a[0] => ram_block3a10.PORTAADDR +address_a[0] => ram_block3a11.PORTAADDR +address_a[0] => ram_block3a12.PORTAADDR +address_a[0] => ram_block3a13.PORTAADDR +address_a[0] => ram_block3a14.PORTAADDR +address_a[0] => ram_block3a15.PORTAADDR +address_a[0] => ram_block3a16.PORTAADDR +address_a[0] => ram_block3a17.PORTAADDR +address_a[0] => ram_block3a18.PORTAADDR +address_a[0] => ram_block3a19.PORTAADDR +address_a[0] => ram_block3a20.PORTAADDR +address_a[0] => ram_block3a21.PORTAADDR +address_a[0] => ram_block3a22.PORTAADDR +address_a[0] => ram_block3a23.PORTAADDR +address_a[1] => ram_block3a0.PORTAADDR1 +address_a[1] => ram_block3a1.PORTAADDR1 +address_a[1] => ram_block3a2.PORTAADDR1 +address_a[1] => ram_block3a3.PORTAADDR1 +address_a[1] => ram_block3a4.PORTAADDR1 +address_a[1] => ram_block3a5.PORTAADDR1 +address_a[1] => ram_block3a6.PORTAADDR1 +address_a[1] => ram_block3a7.PORTAADDR1 +address_a[1] => ram_block3a8.PORTAADDR1 +address_a[1] => ram_block3a9.PORTAADDR1 +address_a[1] => ram_block3a10.PORTAADDR1 +address_a[1] => ram_block3a11.PORTAADDR1 +address_a[1] => ram_block3a12.PORTAADDR1 +address_a[1] => ram_block3a13.PORTAADDR1 +address_a[1] => ram_block3a14.PORTAADDR1 +address_a[1] => ram_block3a15.PORTAADDR1 +address_a[1] => ram_block3a16.PORTAADDR1 +address_a[1] => ram_block3a17.PORTAADDR1 +address_a[1] => ram_block3a18.PORTAADDR1 +address_a[1] => ram_block3a19.PORTAADDR1 +address_a[1] => ram_block3a20.PORTAADDR1 +address_a[1] => ram_block3a21.PORTAADDR1 +address_a[1] => ram_block3a22.PORTAADDR1 +address_a[1] => ram_block3a23.PORTAADDR1 +address_a[2] => ram_block3a0.PORTAADDR2 +address_a[2] => ram_block3a1.PORTAADDR2 +address_a[2] => ram_block3a2.PORTAADDR2 +address_a[2] => ram_block3a3.PORTAADDR2 +address_a[2] => ram_block3a4.PORTAADDR2 +address_a[2] => ram_block3a5.PORTAADDR2 +address_a[2] => ram_block3a6.PORTAADDR2 +address_a[2] => ram_block3a7.PORTAADDR2 +address_a[2] => ram_block3a8.PORTAADDR2 +address_a[2] => ram_block3a9.PORTAADDR2 +address_a[2] => ram_block3a10.PORTAADDR2 +address_a[2] => ram_block3a11.PORTAADDR2 +address_a[2] => ram_block3a12.PORTAADDR2 +address_a[2] => ram_block3a13.PORTAADDR2 +address_a[2] => ram_block3a14.PORTAADDR2 +address_a[2] => ram_block3a15.PORTAADDR2 +address_a[2] => ram_block3a16.PORTAADDR2 +address_a[2] => ram_block3a17.PORTAADDR2 +address_a[2] => ram_block3a18.PORTAADDR2 +address_a[2] => ram_block3a19.PORTAADDR2 +address_a[2] => ram_block3a20.PORTAADDR2 +address_a[2] => ram_block3a21.PORTAADDR2 +address_a[2] => ram_block3a22.PORTAADDR2 +address_a[2] => ram_block3a23.PORTAADDR2 +address_a[3] => ram_block3a0.PORTAADDR3 +address_a[3] => ram_block3a1.PORTAADDR3 +address_a[3] => ram_block3a2.PORTAADDR3 +address_a[3] => ram_block3a3.PORTAADDR3 +address_a[3] => ram_block3a4.PORTAADDR3 +address_a[3] => ram_block3a5.PORTAADDR3 +address_a[3] => ram_block3a6.PORTAADDR3 +address_a[3] => ram_block3a7.PORTAADDR3 +address_a[3] => ram_block3a8.PORTAADDR3 +address_a[3] => ram_block3a9.PORTAADDR3 +address_a[3] => ram_block3a10.PORTAADDR3 +address_a[3] => ram_block3a11.PORTAADDR3 +address_a[3] => ram_block3a12.PORTAADDR3 +address_a[3] => ram_block3a13.PORTAADDR3 +address_a[3] => ram_block3a14.PORTAADDR3 +address_a[3] => ram_block3a15.PORTAADDR3 +address_a[3] => ram_block3a16.PORTAADDR3 +address_a[3] => ram_block3a17.PORTAADDR3 +address_a[3] => ram_block3a18.PORTAADDR3 +address_a[3] => ram_block3a19.PORTAADDR3 +address_a[3] => ram_block3a20.PORTAADDR3 +address_a[3] => ram_block3a21.PORTAADDR3 +address_a[3] => ram_block3a22.PORTAADDR3 +address_a[3] => ram_block3a23.PORTAADDR3 +address_a[4] => ram_block3a0.PORTAADDR4 +address_a[4] => ram_block3a1.PORTAADDR4 +address_a[4] => ram_block3a2.PORTAADDR4 +address_a[4] => ram_block3a3.PORTAADDR4 +address_a[4] => ram_block3a4.PORTAADDR4 +address_a[4] => ram_block3a5.PORTAADDR4 +address_a[4] => ram_block3a6.PORTAADDR4 +address_a[4] => ram_block3a7.PORTAADDR4 +address_a[4] => ram_block3a8.PORTAADDR4 +address_a[4] => ram_block3a9.PORTAADDR4 +address_a[4] => ram_block3a10.PORTAADDR4 +address_a[4] => ram_block3a11.PORTAADDR4 +address_a[4] => ram_block3a12.PORTAADDR4 +address_a[4] => ram_block3a13.PORTAADDR4 +address_a[4] => ram_block3a14.PORTAADDR4 +address_a[4] => ram_block3a15.PORTAADDR4 +address_a[4] => ram_block3a16.PORTAADDR4 +address_a[4] => ram_block3a17.PORTAADDR4 +address_a[4] => ram_block3a18.PORTAADDR4 +address_a[4] => ram_block3a19.PORTAADDR4 +address_a[4] => ram_block3a20.PORTAADDR4 +address_a[4] => ram_block3a21.PORTAADDR4 +address_a[4] => ram_block3a22.PORTAADDR4 +address_a[4] => ram_block3a23.PORTAADDR4 +address_a[5] => ram_block3a0.PORTAADDR5 +address_a[5] => ram_block3a1.PORTAADDR5 +address_a[5] => ram_block3a2.PORTAADDR5 +address_a[5] => ram_block3a3.PORTAADDR5 +address_a[5] => ram_block3a4.PORTAADDR5 +address_a[5] => ram_block3a5.PORTAADDR5 +address_a[5] => ram_block3a6.PORTAADDR5 +address_a[5] => ram_block3a7.PORTAADDR5 +address_a[5] => ram_block3a8.PORTAADDR5 +address_a[5] => ram_block3a9.PORTAADDR5 +address_a[5] => ram_block3a10.PORTAADDR5 +address_a[5] => ram_block3a11.PORTAADDR5 +address_a[5] => ram_block3a12.PORTAADDR5 +address_a[5] => ram_block3a13.PORTAADDR5 +address_a[5] => ram_block3a14.PORTAADDR5 +address_a[5] => ram_block3a15.PORTAADDR5 +address_a[5] => ram_block3a16.PORTAADDR5 +address_a[5] => ram_block3a17.PORTAADDR5 +address_a[5] => ram_block3a18.PORTAADDR5 +address_a[5] => ram_block3a19.PORTAADDR5 +address_a[5] => ram_block3a20.PORTAADDR5 +address_a[5] => ram_block3a21.PORTAADDR5 +address_a[5] => ram_block3a22.PORTAADDR5 +address_a[5] => ram_block3a23.PORTAADDR5 +address_a[6] => ram_block3a0.PORTAADDR6 +address_a[6] => ram_block3a1.PORTAADDR6 +address_a[6] => ram_block3a2.PORTAADDR6 +address_a[6] => ram_block3a3.PORTAADDR6 +address_a[6] => ram_block3a4.PORTAADDR6 +address_a[6] => ram_block3a5.PORTAADDR6 +address_a[6] => ram_block3a6.PORTAADDR6 +address_a[6] => ram_block3a7.PORTAADDR6 +address_a[6] => ram_block3a8.PORTAADDR6 +address_a[6] => ram_block3a9.PORTAADDR6 +address_a[6] => ram_block3a10.PORTAADDR6 +address_a[6] => ram_block3a11.PORTAADDR6 +address_a[6] => ram_block3a12.PORTAADDR6 +address_a[6] => ram_block3a13.PORTAADDR6 +address_a[6] => ram_block3a14.PORTAADDR6 +address_a[6] => ram_block3a15.PORTAADDR6 +address_a[6] => ram_block3a16.PORTAADDR6 +address_a[6] => ram_block3a17.PORTAADDR6 +address_a[6] => ram_block3a18.PORTAADDR6 +address_a[6] => ram_block3a19.PORTAADDR6 +address_a[6] => ram_block3a20.PORTAADDR6 +address_a[6] => ram_block3a21.PORTAADDR6 +address_a[6] => ram_block3a22.PORTAADDR6 +address_a[6] => ram_block3a23.PORTAADDR6 +address_a[7] => ram_block3a0.PORTAADDR7 +address_a[7] => ram_block3a1.PORTAADDR7 +address_a[7] => ram_block3a2.PORTAADDR7 +address_a[7] => ram_block3a3.PORTAADDR7 +address_a[7] => ram_block3a4.PORTAADDR7 +address_a[7] => ram_block3a5.PORTAADDR7 +address_a[7] => ram_block3a6.PORTAADDR7 +address_a[7] => ram_block3a7.PORTAADDR7 +address_a[7] => ram_block3a8.PORTAADDR7 +address_a[7] => ram_block3a9.PORTAADDR7 +address_a[7] => ram_block3a10.PORTAADDR7 +address_a[7] => ram_block3a11.PORTAADDR7 +address_a[7] => ram_block3a12.PORTAADDR7 +address_a[7] => ram_block3a13.PORTAADDR7 +address_a[7] => ram_block3a14.PORTAADDR7 +address_a[7] => ram_block3a15.PORTAADDR7 +address_a[7] => ram_block3a16.PORTAADDR7 +address_a[7] => ram_block3a17.PORTAADDR7 +address_a[7] => ram_block3a18.PORTAADDR7 +address_a[7] => ram_block3a19.PORTAADDR7 +address_a[7] => ram_block3a20.PORTAADDR7 +address_a[7] => ram_block3a21.PORTAADDR7 +address_a[7] => ram_block3a22.PORTAADDR7 +address_a[7] => ram_block3a23.PORTAADDR7 +address_a[8] => ram_block3a0.PORTAADDR8 +address_a[8] => ram_block3a1.PORTAADDR8 +address_a[8] => ram_block3a2.PORTAADDR8 +address_a[8] => ram_block3a3.PORTAADDR8 +address_a[8] => ram_block3a4.PORTAADDR8 +address_a[8] => ram_block3a5.PORTAADDR8 +address_a[8] => ram_block3a6.PORTAADDR8 +address_a[8] => ram_block3a7.PORTAADDR8 +address_a[8] => ram_block3a8.PORTAADDR8 +address_a[8] => ram_block3a9.PORTAADDR8 +address_a[8] => ram_block3a10.PORTAADDR8 +address_a[8] => ram_block3a11.PORTAADDR8 +address_a[8] => ram_block3a12.PORTAADDR8 +address_a[8] => ram_block3a13.PORTAADDR8 +address_a[8] => ram_block3a14.PORTAADDR8 +address_a[8] => ram_block3a15.PORTAADDR8 +address_a[8] => ram_block3a16.PORTAADDR8 +address_a[8] => ram_block3a17.PORTAADDR8 +address_a[8] => ram_block3a18.PORTAADDR8 +address_a[8] => ram_block3a19.PORTAADDR8 +address_a[8] => ram_block3a20.PORTAADDR8 +address_a[8] => ram_block3a21.PORTAADDR8 +address_a[8] => ram_block3a22.PORTAADDR8 +address_a[8] => ram_block3a23.PORTAADDR8 +address_a[9] => ram_block3a0.PORTAADDR9 +address_a[9] => ram_block3a1.PORTAADDR9 +address_a[9] => ram_block3a2.PORTAADDR9 +address_a[9] => ram_block3a3.PORTAADDR9 +address_a[9] => ram_block3a4.PORTAADDR9 +address_a[9] => ram_block3a5.PORTAADDR9 +address_a[9] => ram_block3a6.PORTAADDR9 +address_a[9] => ram_block3a7.PORTAADDR9 +address_a[9] => ram_block3a8.PORTAADDR9 +address_a[9] => ram_block3a9.PORTAADDR9 +address_a[9] => ram_block3a10.PORTAADDR9 +address_a[9] => ram_block3a11.PORTAADDR9 +address_a[9] => ram_block3a12.PORTAADDR9 +address_a[9] => ram_block3a13.PORTAADDR9 +address_a[9] => ram_block3a14.PORTAADDR9 +address_a[9] => ram_block3a15.PORTAADDR9 +address_a[9] => ram_block3a16.PORTAADDR9 +address_a[9] => ram_block3a17.PORTAADDR9 +address_a[9] => ram_block3a18.PORTAADDR9 +address_a[9] => ram_block3a19.PORTAADDR9 +address_a[9] => ram_block3a20.PORTAADDR9 +address_a[9] => ram_block3a21.PORTAADDR9 +address_a[9] => ram_block3a22.PORTAADDR9 +address_a[9] => ram_block3a23.PORTAADDR9 +address_a[10] => ram_block3a0.PORTAADDR10 +address_a[10] => ram_block3a1.PORTAADDR10 +address_a[10] => ram_block3a2.PORTAADDR10 +address_a[10] => ram_block3a3.PORTAADDR10 +address_a[10] => ram_block3a4.PORTAADDR10 +address_a[10] => ram_block3a5.PORTAADDR10 +address_a[10] => ram_block3a6.PORTAADDR10 +address_a[10] => ram_block3a7.PORTAADDR10 +address_a[10] => ram_block3a8.PORTAADDR10 +address_a[10] => ram_block3a9.PORTAADDR10 +address_a[10] => ram_block3a10.PORTAADDR10 +address_a[10] => ram_block3a11.PORTAADDR10 +address_a[10] => ram_block3a12.PORTAADDR10 +address_a[10] => ram_block3a13.PORTAADDR10 +address_a[10] => ram_block3a14.PORTAADDR10 +address_a[10] => ram_block3a15.PORTAADDR10 +address_a[10] => ram_block3a16.PORTAADDR10 +address_a[10] => ram_block3a17.PORTAADDR10 +address_a[10] => ram_block3a18.PORTAADDR10 +address_a[10] => ram_block3a19.PORTAADDR10 +address_a[10] => ram_block3a20.PORTAADDR10 +address_a[10] => ram_block3a21.PORTAADDR10 +address_a[10] => ram_block3a22.PORTAADDR10 +address_a[10] => ram_block3a23.PORTAADDR10 +address_b[0] => ram_block3a0.PORTBADDR +address_b[0] => ram_block3a1.PORTBADDR +address_b[0] => ram_block3a2.PORTBADDR +address_b[0] => ram_block3a3.PORTBADDR +address_b[0] => ram_block3a4.PORTBADDR +address_b[0] => ram_block3a5.PORTBADDR +address_b[0] => ram_block3a6.PORTBADDR +address_b[0] => ram_block3a7.PORTBADDR +address_b[0] => ram_block3a8.PORTBADDR +address_b[0] => ram_block3a9.PORTBADDR +address_b[0] => ram_block3a10.PORTBADDR +address_b[0] => ram_block3a11.PORTBADDR +address_b[0] => ram_block3a12.PORTBADDR +address_b[0] => ram_block3a13.PORTBADDR +address_b[0] => ram_block3a14.PORTBADDR +address_b[0] => ram_block3a15.PORTBADDR +address_b[0] => ram_block3a16.PORTBADDR +address_b[0] => ram_block3a17.PORTBADDR +address_b[0] => ram_block3a18.PORTBADDR +address_b[0] => ram_block3a19.PORTBADDR +address_b[0] => ram_block3a20.PORTBADDR +address_b[0] => ram_block3a21.PORTBADDR +address_b[0] => ram_block3a22.PORTBADDR +address_b[0] => ram_block3a23.PORTBADDR +address_b[1] => ram_block3a0.PORTBADDR1 +address_b[1] => ram_block3a1.PORTBADDR1 +address_b[1] => ram_block3a2.PORTBADDR1 +address_b[1] => ram_block3a3.PORTBADDR1 +address_b[1] => ram_block3a4.PORTBADDR1 +address_b[1] => ram_block3a5.PORTBADDR1 +address_b[1] => ram_block3a6.PORTBADDR1 +address_b[1] => ram_block3a7.PORTBADDR1 +address_b[1] => ram_block3a8.PORTBADDR1 +address_b[1] => ram_block3a9.PORTBADDR1 +address_b[1] => ram_block3a10.PORTBADDR1 +address_b[1] => ram_block3a11.PORTBADDR1 +address_b[1] => ram_block3a12.PORTBADDR1 +address_b[1] => ram_block3a13.PORTBADDR1 +address_b[1] => ram_block3a14.PORTBADDR1 +address_b[1] => ram_block3a15.PORTBADDR1 +address_b[1] => ram_block3a16.PORTBADDR1 +address_b[1] => ram_block3a17.PORTBADDR1 +address_b[1] => ram_block3a18.PORTBADDR1 +address_b[1] => ram_block3a19.PORTBADDR1 +address_b[1] => ram_block3a20.PORTBADDR1 +address_b[1] => ram_block3a21.PORTBADDR1 +address_b[1] => ram_block3a22.PORTBADDR1 +address_b[1] => ram_block3a23.PORTBADDR1 +address_b[2] => ram_block3a0.PORTBADDR2 +address_b[2] => ram_block3a1.PORTBADDR2 +address_b[2] => ram_block3a2.PORTBADDR2 +address_b[2] => ram_block3a3.PORTBADDR2 +address_b[2] => ram_block3a4.PORTBADDR2 +address_b[2] => ram_block3a5.PORTBADDR2 +address_b[2] => ram_block3a6.PORTBADDR2 +address_b[2] => ram_block3a7.PORTBADDR2 +address_b[2] => ram_block3a8.PORTBADDR2 +address_b[2] => ram_block3a9.PORTBADDR2 +address_b[2] => ram_block3a10.PORTBADDR2 +address_b[2] => ram_block3a11.PORTBADDR2 +address_b[2] => ram_block3a12.PORTBADDR2 +address_b[2] => ram_block3a13.PORTBADDR2 +address_b[2] => ram_block3a14.PORTBADDR2 +address_b[2] => ram_block3a15.PORTBADDR2 +address_b[2] => ram_block3a16.PORTBADDR2 +address_b[2] => ram_block3a17.PORTBADDR2 +address_b[2] => ram_block3a18.PORTBADDR2 +address_b[2] => ram_block3a19.PORTBADDR2 +address_b[2] => ram_block3a20.PORTBADDR2 +address_b[2] => ram_block3a21.PORTBADDR2 +address_b[2] => ram_block3a22.PORTBADDR2 +address_b[2] => ram_block3a23.PORTBADDR2 +address_b[3] => ram_block3a0.PORTBADDR3 +address_b[3] => ram_block3a1.PORTBADDR3 +address_b[3] => ram_block3a2.PORTBADDR3 +address_b[3] => ram_block3a3.PORTBADDR3 +address_b[3] => ram_block3a4.PORTBADDR3 +address_b[3] => ram_block3a5.PORTBADDR3 +address_b[3] => ram_block3a6.PORTBADDR3 +address_b[3] => ram_block3a7.PORTBADDR3 +address_b[3] => ram_block3a8.PORTBADDR3 +address_b[3] => ram_block3a9.PORTBADDR3 +address_b[3] => ram_block3a10.PORTBADDR3 +address_b[3] => ram_block3a11.PORTBADDR3 +address_b[3] => ram_block3a12.PORTBADDR3 +address_b[3] => ram_block3a13.PORTBADDR3 +address_b[3] => ram_block3a14.PORTBADDR3 +address_b[3] => ram_block3a15.PORTBADDR3 +address_b[3] => ram_block3a16.PORTBADDR3 +address_b[3] => ram_block3a17.PORTBADDR3 +address_b[3] => ram_block3a18.PORTBADDR3 +address_b[3] => ram_block3a19.PORTBADDR3 +address_b[3] => ram_block3a20.PORTBADDR3 +address_b[3] => ram_block3a21.PORTBADDR3 +address_b[3] => ram_block3a22.PORTBADDR3 +address_b[3] => ram_block3a23.PORTBADDR3 +address_b[4] => ram_block3a0.PORTBADDR4 +address_b[4] => ram_block3a1.PORTBADDR4 +address_b[4] => ram_block3a2.PORTBADDR4 +address_b[4] => ram_block3a3.PORTBADDR4 +address_b[4] => ram_block3a4.PORTBADDR4 +address_b[4] => ram_block3a5.PORTBADDR4 +address_b[4] => ram_block3a6.PORTBADDR4 +address_b[4] => ram_block3a7.PORTBADDR4 +address_b[4] => ram_block3a8.PORTBADDR4 +address_b[4] => ram_block3a9.PORTBADDR4 +address_b[4] => ram_block3a10.PORTBADDR4 +address_b[4] => ram_block3a11.PORTBADDR4 +address_b[4] => ram_block3a12.PORTBADDR4 +address_b[4] => ram_block3a13.PORTBADDR4 +address_b[4] => ram_block3a14.PORTBADDR4 +address_b[4] => ram_block3a15.PORTBADDR4 +address_b[4] => ram_block3a16.PORTBADDR4 +address_b[4] => ram_block3a17.PORTBADDR4 +address_b[4] => ram_block3a18.PORTBADDR4 +address_b[4] => ram_block3a19.PORTBADDR4 +address_b[4] => ram_block3a20.PORTBADDR4 +address_b[4] => ram_block3a21.PORTBADDR4 +address_b[4] => ram_block3a22.PORTBADDR4 +address_b[4] => ram_block3a23.PORTBADDR4 +address_b[5] => ram_block3a0.PORTBADDR5 +address_b[5] => ram_block3a1.PORTBADDR5 +address_b[5] => ram_block3a2.PORTBADDR5 +address_b[5] => ram_block3a3.PORTBADDR5 +address_b[5] => ram_block3a4.PORTBADDR5 +address_b[5] => ram_block3a5.PORTBADDR5 +address_b[5] => ram_block3a6.PORTBADDR5 +address_b[5] => ram_block3a7.PORTBADDR5 +address_b[5] => ram_block3a8.PORTBADDR5 +address_b[5] => ram_block3a9.PORTBADDR5 +address_b[5] => ram_block3a10.PORTBADDR5 +address_b[5] => ram_block3a11.PORTBADDR5 +address_b[5] => ram_block3a12.PORTBADDR5 +address_b[5] => ram_block3a13.PORTBADDR5 +address_b[5] => ram_block3a14.PORTBADDR5 +address_b[5] => ram_block3a15.PORTBADDR5 +address_b[5] => ram_block3a16.PORTBADDR5 +address_b[5] => ram_block3a17.PORTBADDR5 +address_b[5] => ram_block3a18.PORTBADDR5 +address_b[5] => ram_block3a19.PORTBADDR5 +address_b[5] => ram_block3a20.PORTBADDR5 +address_b[5] => ram_block3a21.PORTBADDR5 +address_b[5] => ram_block3a22.PORTBADDR5 +address_b[5] => ram_block3a23.PORTBADDR5 +address_b[6] => ram_block3a0.PORTBADDR6 +address_b[6] => ram_block3a1.PORTBADDR6 +address_b[6] => ram_block3a2.PORTBADDR6 +address_b[6] => ram_block3a3.PORTBADDR6 +address_b[6] => ram_block3a4.PORTBADDR6 +address_b[6] => ram_block3a5.PORTBADDR6 +address_b[6] => ram_block3a6.PORTBADDR6 +address_b[6] => ram_block3a7.PORTBADDR6 +address_b[6] => ram_block3a8.PORTBADDR6 +address_b[6] => ram_block3a9.PORTBADDR6 +address_b[6] => ram_block3a10.PORTBADDR6 +address_b[6] => ram_block3a11.PORTBADDR6 +address_b[6] => ram_block3a12.PORTBADDR6 +address_b[6] => ram_block3a13.PORTBADDR6 +address_b[6] => ram_block3a14.PORTBADDR6 +address_b[6] => ram_block3a15.PORTBADDR6 +address_b[6] => ram_block3a16.PORTBADDR6 +address_b[6] => ram_block3a17.PORTBADDR6 +address_b[6] => ram_block3a18.PORTBADDR6 +address_b[6] => ram_block3a19.PORTBADDR6 +address_b[6] => ram_block3a20.PORTBADDR6 +address_b[6] => ram_block3a21.PORTBADDR6 +address_b[6] => ram_block3a22.PORTBADDR6 +address_b[6] => ram_block3a23.PORTBADDR6 +address_b[7] => ram_block3a0.PORTBADDR7 +address_b[7] => ram_block3a1.PORTBADDR7 +address_b[7] => ram_block3a2.PORTBADDR7 +address_b[7] => ram_block3a3.PORTBADDR7 +address_b[7] => ram_block3a4.PORTBADDR7 +address_b[7] => ram_block3a5.PORTBADDR7 +address_b[7] => ram_block3a6.PORTBADDR7 +address_b[7] => ram_block3a7.PORTBADDR7 +address_b[7] => ram_block3a8.PORTBADDR7 +address_b[7] => ram_block3a9.PORTBADDR7 +address_b[7] => ram_block3a10.PORTBADDR7 +address_b[7] => ram_block3a11.PORTBADDR7 +address_b[7] => ram_block3a12.PORTBADDR7 +address_b[7] => ram_block3a13.PORTBADDR7 +address_b[7] => ram_block3a14.PORTBADDR7 +address_b[7] => ram_block3a15.PORTBADDR7 +address_b[7] => ram_block3a16.PORTBADDR7 +address_b[7] => ram_block3a17.PORTBADDR7 +address_b[7] => ram_block3a18.PORTBADDR7 +address_b[7] => ram_block3a19.PORTBADDR7 +address_b[7] => ram_block3a20.PORTBADDR7 +address_b[7] => ram_block3a21.PORTBADDR7 +address_b[7] => ram_block3a22.PORTBADDR7 +address_b[7] => ram_block3a23.PORTBADDR7 +address_b[8] => ram_block3a0.PORTBADDR8 +address_b[8] => ram_block3a1.PORTBADDR8 +address_b[8] => ram_block3a2.PORTBADDR8 +address_b[8] => ram_block3a3.PORTBADDR8 +address_b[8] => ram_block3a4.PORTBADDR8 +address_b[8] => ram_block3a5.PORTBADDR8 +address_b[8] => ram_block3a6.PORTBADDR8 +address_b[8] => ram_block3a7.PORTBADDR8 +address_b[8] => ram_block3a8.PORTBADDR8 +address_b[8] => ram_block3a9.PORTBADDR8 +address_b[8] => ram_block3a10.PORTBADDR8 +address_b[8] => ram_block3a11.PORTBADDR8 +address_b[8] => ram_block3a12.PORTBADDR8 +address_b[8] => ram_block3a13.PORTBADDR8 +address_b[8] => ram_block3a14.PORTBADDR8 +address_b[8] => ram_block3a15.PORTBADDR8 +address_b[8] => ram_block3a16.PORTBADDR8 +address_b[8] => ram_block3a17.PORTBADDR8 +address_b[8] => ram_block3a18.PORTBADDR8 +address_b[8] => ram_block3a19.PORTBADDR8 +address_b[8] => ram_block3a20.PORTBADDR8 +address_b[8] => ram_block3a21.PORTBADDR8 +address_b[8] => ram_block3a22.PORTBADDR8 +address_b[8] => ram_block3a23.PORTBADDR8 +address_b[9] => ram_block3a0.PORTBADDR9 +address_b[9] => ram_block3a1.PORTBADDR9 +address_b[9] => ram_block3a2.PORTBADDR9 +address_b[9] => ram_block3a3.PORTBADDR9 +address_b[9] => ram_block3a4.PORTBADDR9 +address_b[9] => ram_block3a5.PORTBADDR9 +address_b[9] => ram_block3a6.PORTBADDR9 +address_b[9] => ram_block3a7.PORTBADDR9 +address_b[9] => ram_block3a8.PORTBADDR9 +address_b[9] => ram_block3a9.PORTBADDR9 +address_b[9] => ram_block3a10.PORTBADDR9 +address_b[9] => ram_block3a11.PORTBADDR9 +address_b[9] => ram_block3a12.PORTBADDR9 +address_b[9] => ram_block3a13.PORTBADDR9 +address_b[9] => ram_block3a14.PORTBADDR9 +address_b[9] => ram_block3a15.PORTBADDR9 +address_b[9] => ram_block3a16.PORTBADDR9 +address_b[9] => ram_block3a17.PORTBADDR9 +address_b[9] => ram_block3a18.PORTBADDR9 +address_b[9] => ram_block3a19.PORTBADDR9 +address_b[9] => ram_block3a20.PORTBADDR9 +address_b[9] => ram_block3a21.PORTBADDR9 +address_b[9] => ram_block3a22.PORTBADDR9 +address_b[9] => ram_block3a23.PORTBADDR9 +address_b[10] => ram_block3a0.PORTBADDR10 +address_b[10] => ram_block3a1.PORTBADDR10 +address_b[10] => ram_block3a2.PORTBADDR10 +address_b[10] => ram_block3a3.PORTBADDR10 +address_b[10] => ram_block3a4.PORTBADDR10 +address_b[10] => ram_block3a5.PORTBADDR10 +address_b[10] => ram_block3a6.PORTBADDR10 +address_b[10] => ram_block3a7.PORTBADDR10 +address_b[10] => ram_block3a8.PORTBADDR10 +address_b[10] => ram_block3a9.PORTBADDR10 +address_b[10] => ram_block3a10.PORTBADDR10 +address_b[10] => ram_block3a11.PORTBADDR10 +address_b[10] => ram_block3a12.PORTBADDR10 +address_b[10] => ram_block3a13.PORTBADDR10 +address_b[10] => ram_block3a14.PORTBADDR10 +address_b[10] => ram_block3a15.PORTBADDR10 +address_b[10] => ram_block3a16.PORTBADDR10 +address_b[10] => ram_block3a17.PORTBADDR10 +address_b[10] => ram_block3a18.PORTBADDR10 +address_b[10] => ram_block3a19.PORTBADDR10 +address_b[10] => ram_block3a20.PORTBADDR10 +address_b[10] => ram_block3a21.PORTBADDR10 +address_b[10] => ram_block3a22.PORTBADDR10 +address_b[10] => ram_block3a23.PORTBADDR10 +clock0 => ram_block3a0.CLK0 +clock0 => ram_block3a1.CLK0 +clock0 => ram_block3a2.CLK0 +clock0 => ram_block3a3.CLK0 +clock0 => ram_block3a4.CLK0 +clock0 => ram_block3a5.CLK0 +clock0 => ram_block3a6.CLK0 +clock0 => ram_block3a7.CLK0 +clock0 => ram_block3a8.CLK0 +clock0 => ram_block3a9.CLK0 +clock0 => ram_block3a10.CLK0 +clock0 => ram_block3a11.CLK0 +clock0 => ram_block3a12.CLK0 +clock0 => ram_block3a13.CLK0 +clock0 => ram_block3a14.CLK0 +clock0 => ram_block3a15.CLK0 +clock0 => ram_block3a16.CLK0 +clock0 => ram_block3a17.CLK0 +clock0 => ram_block3a18.CLK0 +clock0 => ram_block3a19.CLK0 +clock0 => ram_block3a20.CLK0 +clock0 => ram_block3a21.CLK0 +clock0 => ram_block3a22.CLK0 +clock0 => ram_block3a23.CLK0 +clocken0 => ram_block3a0.ENA0 +clocken0 => ram_block3a1.ENA0 +clocken0 => ram_block3a2.ENA0 +clocken0 => ram_block3a3.ENA0 +clocken0 => ram_block3a4.ENA0 +clocken0 => ram_block3a5.ENA0 +clocken0 => ram_block3a6.ENA0 +clocken0 => ram_block3a7.ENA0 +clocken0 => ram_block3a8.ENA0 +clocken0 => ram_block3a9.ENA0 +clocken0 => ram_block3a10.ENA0 +clocken0 => ram_block3a11.ENA0 +clocken0 => ram_block3a12.ENA0 +clocken0 => ram_block3a13.ENA0 +clocken0 => ram_block3a14.ENA0 +clocken0 => ram_block3a15.ENA0 +clocken0 => ram_block3a16.ENA0 +clocken0 => ram_block3a17.ENA0 +clocken0 => ram_block3a18.ENA0 +clocken0 => ram_block3a19.ENA0 +clocken0 => ram_block3a20.ENA0 +clocken0 => ram_block3a21.ENA0 +clocken0 => ram_block3a22.ENA0 +clocken0 => ram_block3a23.ENA0 +data_a[0] => ram_block3a0.PORTADATAIN +data_a[1] => ram_block3a1.PORTADATAIN +data_a[2] => ram_block3a2.PORTADATAIN +data_a[3] => ram_block3a3.PORTADATAIN +data_a[4] => ram_block3a4.PORTADATAIN +data_a[5] => ram_block3a5.PORTADATAIN +data_a[6] => ram_block3a6.PORTADATAIN +data_a[7] => ram_block3a7.PORTADATAIN +data_a[8] => ram_block3a8.PORTADATAIN +data_a[9] => ram_block3a9.PORTADATAIN +data_a[10] => ram_block3a10.PORTADATAIN +data_a[11] => ram_block3a11.PORTADATAIN +data_a[12] => ram_block3a12.PORTADATAIN +data_a[13] => ram_block3a13.PORTADATAIN +data_a[14] => ram_block3a14.PORTADATAIN +data_a[15] => ram_block3a15.PORTADATAIN +data_a[16] => ram_block3a16.PORTADATAIN +data_a[17] => ram_block3a17.PORTADATAIN +data_a[18] => ram_block3a18.PORTADATAIN +data_a[19] => ram_block3a19.PORTADATAIN +data_a[20] => ram_block3a20.PORTADATAIN +data_a[21] => ram_block3a21.PORTADATAIN +data_a[22] => ram_block3a22.PORTADATAIN +data_a[23] => ram_block3a23.PORTADATAIN +q_b[0] <= ram_block3a0.PORTBDATAOUT +q_b[1] <= ram_block3a1.PORTBDATAOUT +q_b[2] <= ram_block3a2.PORTBDATAOUT +q_b[3] <= ram_block3a3.PORTBDATAOUT +q_b[4] <= ram_block3a4.PORTBDATAOUT +q_b[5] <= ram_block3a5.PORTBDATAOUT +q_b[6] <= ram_block3a6.PORTBDATAOUT +q_b[7] <= ram_block3a7.PORTBDATAOUT +q_b[8] <= ram_block3a8.PORTBDATAOUT +q_b[9] <= ram_block3a9.PORTBDATAOUT +q_b[10] <= ram_block3a10.PORTBDATAOUT +q_b[11] <= ram_block3a11.PORTBDATAOUT +q_b[12] <= ram_block3a12.PORTBDATAOUT +q_b[13] <= ram_block3a13.PORTBDATAOUT +q_b[14] <= ram_block3a14.PORTBDATAOUT +q_b[15] <= ram_block3a15.PORTBDATAOUT +q_b[16] <= ram_block3a16.PORTBDATAOUT +q_b[17] <= ram_block3a17.PORTBDATAOUT +q_b[18] <= ram_block3a18.PORTBDATAOUT +q_b[19] <= ram_block3a19.PORTBDATAOUT +q_b[20] <= ram_block3a20.PORTBDATAOUT +q_b[21] <= ram_block3a21.PORTBDATAOUT +q_b[22] <= ram_block3a22.PORTBDATAOUT +q_b[23] <= ram_block3a23.PORTBDATAOUT +wren_a => ram_block3a0.PORTAWE +wren_a => ram_block3a1.PORTAWE +wren_a => ram_block3a2.PORTAWE +wren_a => ram_block3a3.PORTAWE +wren_a => ram_block3a4.PORTAWE +wren_a => ram_block3a5.PORTAWE +wren_a => ram_block3a6.PORTAWE +wren_a => ram_block3a7.PORTAWE +wren_a => ram_block3a8.PORTAWE +wren_a => ram_block3a9.PORTAWE +wren_a => ram_block3a10.PORTAWE +wren_a => ram_block3a11.PORTAWE +wren_a => ram_block3a12.PORTAWE +wren_a => ram_block3a13.PORTAWE +wren_a => ram_block3a14.PORTAWE +wren_a => ram_block3a15.PORTAWE +wren_a => ram_block3a16.PORTAWE +wren_a => ram_block3a17.PORTAWE +wren_a => ram_block3a18.PORTAWE +wren_a => ram_block3a19.PORTAWE +wren_a => ram_block3a20.PORTAWE +wren_a => ram_block3a21.PORTAWE +wren_a => ram_block3a22.PORTAWE +wren_a => ram_block3a23.PORTAWE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1 +clk_en => counter_reg_bit[10].IN0 +clock => counter_reg_bit[10].CLK +clock => counter_reg_bit[9].CLK +clock => counter_reg_bit[8].CLK +clock => counter_reg_bit[7].CLK +clock => counter_reg_bit[6].CLK +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= counter_reg_bit[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= counter_reg_bit[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= counter_reg_bit[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= counter_reg_bit[9].DB_MAX_OUTPUT_PORT_TYPE +q[10] <= counter_reg_bit[10].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4 +aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE +dataa[0] => data_wire[2].IN0 +dataa[1] => data_wire[2].IN0 +dataa[2] => data_wire[3].IN0 +dataa[3] => data_wire[3].IN0 +dataa[4] => data_wire[4].IN0 +dataa[5] => data_wire[4].IN0 +dataa[6] => data_wire[5].IN0 +dataa[7] => data_wire[5].IN0 +dataa[8] => data_wire[6].IN0 +dataa[9] => data_wire[6].IN0 +dataa[10] => data_wire[7].IN0 +datab[0] => data_wire[2].IN1 +datab[1] => data_wire[2].IN1 +datab[2] => data_wire[3].IN1 +datab[3] => data_wire[3].IN1 +datab[4] => data_wire[4].IN1 +datab[5] => data_wire[4].IN1 +datab[6] => data_wire[5].IN1 +datab[7] => data_wire[5].IN1 +datab[8] => data_wire[6].IN1 +datab[9] => data_wire[6].IN1 +datab[10] => data_wire[7].IN1 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5 +oSEG0[0] <= SEG7_LUT:u0.port0 +oSEG0[1] <= SEG7_LUT:u0.port0 +oSEG0[2] <= SEG7_LUT:u0.port0 +oSEG0[3] <= SEG7_LUT:u0.port0 +oSEG0[4] <= SEG7_LUT:u0.port0 +oSEG0[5] <= SEG7_LUT:u0.port0 +oSEG0[6] <= SEG7_LUT:u0.port0 +oSEG1[0] <= SEG7_LUT:u1.port0 +oSEG1[1] <= SEG7_LUT:u1.port0 +oSEG1[2] <= SEG7_LUT:u1.port0 +oSEG1[3] <= SEG7_LUT:u1.port0 +oSEG1[4] <= SEG7_LUT:u1.port0 +oSEG1[5] <= SEG7_LUT:u1.port0 +oSEG1[6] <= SEG7_LUT:u1.port0 +oSEG2[0] <= SEG7_LUT:u2.port0 +oSEG2[1] <= SEG7_LUT:u2.port0 +oSEG2[2] <= SEG7_LUT:u2.port0 +oSEG2[3] <= SEG7_LUT:u2.port0 +oSEG2[4] <= SEG7_LUT:u2.port0 +oSEG2[5] <= SEG7_LUT:u2.port0 +oSEG2[6] <= SEG7_LUT:u2.port0 +oSEG3[0] <= SEG7_LUT:u3.port0 +oSEG3[1] <= SEG7_LUT:u3.port0 +oSEG3[2] <= SEG7_LUT:u3.port0 +oSEG3[3] <= SEG7_LUT:u3.port0 +oSEG3[4] <= SEG7_LUT:u3.port0 +oSEG3[5] <= SEG7_LUT:u3.port0 +oSEG3[6] <= SEG7_LUT:u3.port0 +oSEG4[0] <= SEG7_LUT:u4.port0 +oSEG4[1] <= SEG7_LUT:u4.port0 +oSEG4[2] <= SEG7_LUT:u4.port0 +oSEG4[3] <= SEG7_LUT:u4.port0 +oSEG4[4] <= SEG7_LUT:u4.port0 +oSEG4[5] <= SEG7_LUT:u4.port0 +oSEG4[6] <= SEG7_LUT:u4.port0 +oSEG5[0] <= SEG7_LUT:u5.port0 +oSEG5[1] <= SEG7_LUT:u5.port0 +oSEG5[2] <= SEG7_LUT:u5.port0 +oSEG5[3] <= SEG7_LUT:u5.port0 +oSEG5[4] <= SEG7_LUT:u5.port0 +oSEG5[5] <= SEG7_LUT:u5.port0 +oSEG5[6] <= SEG7_LUT:u5.port0 +oSEG6[0] <= SEG7_LUT:u6.port0 +oSEG6[1] <= SEG7_LUT:u6.port0 +oSEG6[2] <= SEG7_LUT:u6.port0 +oSEG6[3] <= SEG7_LUT:u6.port0 +oSEG6[4] <= SEG7_LUT:u6.port0 +oSEG6[5] <= SEG7_LUT:u6.port0 +oSEG6[6] <= SEG7_LUT:u6.port0 +oSEG7[0] <= SEG7_LUT:u7.port0 +oSEG7[1] <= SEG7_LUT:u7.port0 +oSEG7[2] <= SEG7_LUT:u7.port0 +oSEG7[3] <= SEG7_LUT:u7.port0 +oSEG7[4] <= SEG7_LUT:u7.port0 +oSEG7[5] <= SEG7_LUT:u7.port0 +oSEG7[6] <= SEG7_LUT:u7.port0 +iDIG[0] => iDIG[0].IN1 +iDIG[1] => iDIG[1].IN1 +iDIG[2] => iDIG[2].IN1 +iDIG[3] => iDIG[3].IN1 +iDIG[4] => iDIG[4].IN1 +iDIG[5] => iDIG[5].IN1 +iDIG[6] => iDIG[6].IN1 +iDIG[7] => iDIG[7].IN1 +iDIG[8] => iDIG[8].IN1 +iDIG[9] => iDIG[9].IN1 +iDIG[10] => iDIG[10].IN1 +iDIG[11] => iDIG[11].IN1 +iDIG[12] => iDIG[12].IN1 +iDIG[13] => iDIG[13].IN1 +iDIG[14] => iDIG[14].IN1 +iDIG[15] => iDIG[15].IN1 +iDIG[16] => iDIG[16].IN1 +iDIG[17] => iDIG[17].IN1 +iDIG[18] => iDIG[18].IN1 +iDIG[19] => iDIG[19].IN1 +iDIG[20] => iDIG[20].IN1 +iDIG[21] => iDIG[21].IN1 +iDIG[22] => iDIG[22].IN1 +iDIG[23] => iDIG[23].IN1 +iDIG[24] => iDIG[24].IN1 +iDIG[25] => iDIG[25].IN1 +iDIG[26] => iDIG[26].IN1 +iDIG[27] => iDIG[27].IN1 +iDIG[28] => iDIG[28].IN1 +iDIG[29] => iDIG[29].IN1 +iDIG[30] => iDIG[30].IN1 +iDIG[31] => iDIG[31].IN1 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u0 +oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE +oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE +oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE +oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE +oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE +oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE +oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +iDIG[0] => Decoder0.IN3 +iDIG[1] => Decoder0.IN2 +iDIG[2] => Decoder0.IN1 +iDIG[3] => Decoder0.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u1 +oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE +oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE +oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE +oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE +oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE +oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE +oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +iDIG[0] => Decoder0.IN3 +iDIG[1] => Decoder0.IN2 +iDIG[2] => Decoder0.IN1 +iDIG[3] => Decoder0.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u2 +oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE +oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE +oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE +oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE +oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE +oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE +oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +iDIG[0] => Decoder0.IN3 +iDIG[1] => Decoder0.IN2 +iDIG[2] => Decoder0.IN1 +iDIG[3] => Decoder0.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u3 +oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE +oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE +oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE +oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE +oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE +oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE +oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +iDIG[0] => Decoder0.IN3 +iDIG[1] => Decoder0.IN2 +iDIG[2] => Decoder0.IN1 +iDIG[3] => Decoder0.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u4 +oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE +oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE +oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE +oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE +oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE +oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE +oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +iDIG[0] => Decoder0.IN3 +iDIG[1] => Decoder0.IN2 +iDIG[2] => Decoder0.IN1 +iDIG[3] => Decoder0.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u5 +oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE +oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE +oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE +oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE +oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE +oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE +oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +iDIG[0] => Decoder0.IN3 +iDIG[1] => Decoder0.IN2 +iDIG[2] => Decoder0.IN1 +iDIG[3] => Decoder0.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u6 +oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE +oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE +oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE +oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE +oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE +oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE +oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +iDIG[0] => Decoder0.IN3 +iDIG[1] => Decoder0.IN2 +iDIG[2] => Decoder0.IN1 +iDIG[3] => Decoder0.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u7 +oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE +oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE +oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE +oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE +oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE +oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE +oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +iDIG[0] => Decoder0.IN3 +iDIG[1] => Decoder0.IN2 +iDIG[2] => Decoder0.IN1 +iDIG[3] => Decoder0.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6 +inclk0 => sub_wire4[0].IN1 +c0 <= altpll:altpll_component.clk +c1 <= altpll:altpll_component.clk + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component +inclk[0] => altpll_9ee2:auto_generated.inclk[0] +inclk[1] => altpll_9ee2:auto_generated.inclk[1] +fbin => ~NO_FANOUT~ +pllena => ~NO_FANOUT~ +clkswitch => ~NO_FANOUT~ +areset => ~NO_FANOUT~ +pfdena => ~NO_FANOUT~ +clkena[0] => ~NO_FANOUT~ +clkena[1] => ~NO_FANOUT~ +clkena[2] => ~NO_FANOUT~ +clkena[3] => ~NO_FANOUT~ +clkena[4] => ~NO_FANOUT~ +clkena[5] => ~NO_FANOUT~ +extclkena[0] => ~NO_FANOUT~ +extclkena[1] => ~NO_FANOUT~ +extclkena[2] => ~NO_FANOUT~ +extclkena[3] => ~NO_FANOUT~ +scanclk => ~NO_FANOUT~ +scanclkena => ~NO_FANOUT~ +scanaclr => ~NO_FANOUT~ +scanread => ~NO_FANOUT~ +scanwrite => ~NO_FANOUT~ +scandata => ~NO_FANOUT~ +phasecounterselect[0] => ~NO_FANOUT~ +phasecounterselect[1] => ~NO_FANOUT~ +phasecounterselect[2] => ~NO_FANOUT~ +phasecounterselect[3] => ~NO_FANOUT~ +phaseupdown => ~NO_FANOUT~ +phasestep => ~NO_FANOUT~ +configupdate => ~NO_FANOUT~ +fbmimicbidir <> <GND> +clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE +clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE +clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE +clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE +clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE +extclk[0] <= <GND> +extclk[1] <= <GND> +extclk[2] <= <GND> +extclk[3] <= <GND> +clkbad[0] <= <GND> +clkbad[1] <= <GND> +enable1 <= <GND> +enable0 <= <GND> +activeclock <= <GND> +clkloss <= <GND> +locked <= <GND> +scandataout <= <GND> +scandone <= <GND> +sclkout0 <= <GND> +sclkout1 <= <GND> +phasedone <= <GND> +vcooverrange <= <GND> +vcounderrange <= <GND> +fbout <= <GND> +fref <= <GND> +icdrclk <= <GND> + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated +clk[0] <= pll1.CLK +clk[1] <= pll1.CLK1 +clk[2] <= pll1.CLK2 +clk[3] <= pll1.CLK3 +clk[4] <= pll1.CLK4 +inclk[0] => pll1.CLK +inclk[1] => pll1.CLK1 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7 +REF_CLK => ~NO_FANOUT~ +RESET_N => RESET_N.IN3 +CLK => CLK.IN7 +WR1_DATA[0] => WR1_DATA[0].IN1 +WR1_DATA[1] => WR1_DATA[1].IN1 +WR1_DATA[2] => WR1_DATA[2].IN1 +WR1_DATA[3] => WR1_DATA[3].IN1 +WR1_DATA[4] => WR1_DATA[4].IN1 +WR1_DATA[5] => WR1_DATA[5].IN1 +WR1_DATA[6] => WR1_DATA[6].IN1 +WR1_DATA[7] => WR1_DATA[7].IN1 +WR1_DATA[8] => WR1_DATA[8].IN1 +WR1_DATA[9] => WR1_DATA[9].IN1 +WR1_DATA[10] => WR1_DATA[10].IN1 +WR1_DATA[11] => WR1_DATA[11].IN1 +WR1_DATA[12] => WR1_DATA[12].IN1 +WR1_DATA[13] => WR1_DATA[13].IN1 +WR1_DATA[14] => WR1_DATA[14].IN1 +WR1_DATA[15] => WR1_DATA[15].IN1 +WR1 => WR1.IN1 +WR1_ADDR[0] => rWR1_ADDR.DATAA +WR1_ADDR[0] => rWR1_ADDR.DATAB +WR1_ADDR[1] => rWR1_ADDR.DATAA +WR1_ADDR[1] => rWR1_ADDR.DATAB +WR1_ADDR[2] => rWR1_ADDR.DATAA +WR1_ADDR[2] => rWR1_ADDR.DATAB +WR1_ADDR[3] => rWR1_ADDR.DATAA +WR1_ADDR[3] => rWR1_ADDR.DATAB +WR1_ADDR[4] => rWR1_ADDR.DATAA +WR1_ADDR[4] => rWR1_ADDR.DATAB +WR1_ADDR[5] => rWR1_ADDR.DATAA +WR1_ADDR[5] => rWR1_ADDR.DATAB +WR1_ADDR[6] => rWR1_ADDR.DATAA +WR1_ADDR[6] => rWR1_ADDR.DATAB +WR1_ADDR[7] => rWR1_ADDR.DATAA +WR1_ADDR[7] => rWR1_ADDR.DATAB +WR1_ADDR[8] => rWR1_ADDR.DATAA +WR1_ADDR[8] => rWR1_ADDR.DATAB +WR1_ADDR[9] => rWR1_ADDR.DATAA +WR1_ADDR[9] => rWR1_ADDR.DATAB +WR1_ADDR[10] => rWR1_ADDR.DATAA +WR1_ADDR[10] => rWR1_ADDR.DATAB +WR1_ADDR[11] => rWR1_ADDR.DATAA +WR1_ADDR[11] => rWR1_ADDR.DATAB +WR1_ADDR[12] => rWR1_ADDR.DATAA +WR1_ADDR[12] => rWR1_ADDR.DATAB +WR1_ADDR[13] => rWR1_ADDR.DATAA +WR1_ADDR[13] => rWR1_ADDR.DATAB +WR1_ADDR[14] => rWR1_ADDR.DATAA +WR1_ADDR[14] => rWR1_ADDR.DATAB +WR1_ADDR[15] => rWR1_ADDR.DATAA +WR1_ADDR[15] => rWR1_ADDR.DATAB +WR1_ADDR[16] => rWR1_ADDR.DATAA +WR1_ADDR[16] => rWR1_ADDR.DATAB +WR1_ADDR[17] => rWR1_ADDR.DATAA +WR1_ADDR[17] => rWR1_ADDR.DATAB +WR1_ADDR[18] => rWR1_ADDR.DATAA +WR1_ADDR[18] => rWR1_ADDR.DATAB +WR1_ADDR[19] => rWR1_ADDR.DATAA +WR1_ADDR[19] => rWR1_ADDR.DATAB +WR1_ADDR[20] => rWR1_ADDR.DATAA +WR1_ADDR[20] => rWR1_ADDR.DATAB +WR1_ADDR[21] => rWR1_ADDR.DATAA +WR1_ADDR[21] => rWR1_ADDR.DATAB +WR1_ADDR[22] => rWR1_ADDR.DATAA +WR1_ADDR[22] => rWR1_ADDR.DATAB +WR1_MAX_ADDR[0] => ~NO_FANOUT~ +WR1_MAX_ADDR[1] => ~NO_FANOUT~ +WR1_MAX_ADDR[2] => ~NO_FANOUT~ +WR1_MAX_ADDR[3] => ~NO_FANOUT~ +WR1_MAX_ADDR[4] => ~NO_FANOUT~ +WR1_MAX_ADDR[5] => ~NO_FANOUT~ +WR1_MAX_ADDR[6] => ~NO_FANOUT~ +WR1_MAX_ADDR[7] => ~NO_FANOUT~ +WR1_MAX_ADDR[8] => ~NO_FANOUT~ +WR1_MAX_ADDR[9] => ~NO_FANOUT~ +WR1_MAX_ADDR[10] => ~NO_FANOUT~ +WR1_MAX_ADDR[11] => ~NO_FANOUT~ +WR1_MAX_ADDR[12] => ~NO_FANOUT~ +WR1_MAX_ADDR[13] => ~NO_FANOUT~ +WR1_MAX_ADDR[14] => ~NO_FANOUT~ +WR1_MAX_ADDR[15] => ~NO_FANOUT~ +WR1_MAX_ADDR[16] => ~NO_FANOUT~ +WR1_MAX_ADDR[17] => ~NO_FANOUT~ +WR1_MAX_ADDR[18] => ~NO_FANOUT~ +WR1_MAX_ADDR[19] => ~NO_FANOUT~ +WR1_MAX_ADDR[20] => ~NO_FANOUT~ +WR1_MAX_ADDR[21] => ~NO_FANOUT~ +WR1_MAX_ADDR[22] => ~NO_FANOUT~ +WR1_LENGTH[0] => rWR1_LENGTH[0].DATAIN +WR1_LENGTH[1] => rWR1_LENGTH[1].DATAIN +WR1_LENGTH[2] => rWR1_LENGTH[2].DATAIN +WR1_LENGTH[3] => rWR1_LENGTH[3].DATAIN +WR1_LENGTH[4] => rWR1_LENGTH[4].DATAIN +WR1_LENGTH[5] => rWR1_LENGTH[5].DATAIN +WR1_LENGTH[6] => rWR1_LENGTH[6].DATAIN +WR1_LENGTH[7] => rWR1_LENGTH[7].DATAIN +WR1_LENGTH[8] => rWR1_LENGTH[8].DATAIN +WR1_LOAD => WR1_LOAD.IN1 +WR1_CLK => WR1_CLK.IN1 +WR2_DATA[0] => WR2_DATA[0].IN1 +WR2_DATA[1] => WR2_DATA[1].IN1 +WR2_DATA[2] => WR2_DATA[2].IN1 +WR2_DATA[3] => WR2_DATA[3].IN1 +WR2_DATA[4] => WR2_DATA[4].IN1 +WR2_DATA[5] => WR2_DATA[5].IN1 +WR2_DATA[6] => WR2_DATA[6].IN1 +WR2_DATA[7] => WR2_DATA[7].IN1 +WR2_DATA[8] => WR2_DATA[8].IN1 +WR2_DATA[9] => WR2_DATA[9].IN1 +WR2_DATA[10] => WR2_DATA[10].IN1 +WR2_DATA[11] => WR2_DATA[11].IN1 +WR2_DATA[12] => WR2_DATA[12].IN1 +WR2_DATA[13] => WR2_DATA[13].IN1 +WR2_DATA[14] => WR2_DATA[14].IN1 +WR2_DATA[15] => WR2_DATA[15].IN1 +WR2 => WR2.IN1 +WR2_ADDR[0] => rWR2_ADDR.DATAA +WR2_ADDR[0] => rWR2_ADDR.DATAB +WR2_ADDR[1] => rWR2_ADDR.DATAA +WR2_ADDR[1] => rWR2_ADDR.DATAB +WR2_ADDR[2] => rWR2_ADDR.DATAA +WR2_ADDR[2] => rWR2_ADDR.DATAB +WR2_ADDR[3] => rWR2_ADDR.DATAA +WR2_ADDR[3] => rWR2_ADDR.DATAB +WR2_ADDR[4] => rWR2_ADDR.DATAA +WR2_ADDR[4] => rWR2_ADDR.DATAB +WR2_ADDR[5] => rWR2_ADDR.DATAA +WR2_ADDR[5] => rWR2_ADDR.DATAB +WR2_ADDR[6] => rWR2_ADDR.DATAA +WR2_ADDR[6] => rWR2_ADDR.DATAB +WR2_ADDR[7] => rWR2_ADDR.DATAA +WR2_ADDR[7] => rWR2_ADDR.DATAB +WR2_ADDR[8] => rWR2_ADDR.DATAA +WR2_ADDR[8] => rWR2_ADDR.DATAB +WR2_ADDR[9] => rWR2_ADDR.DATAA +WR2_ADDR[9] => rWR2_ADDR.DATAB +WR2_ADDR[10] => rWR2_ADDR.DATAA +WR2_ADDR[10] => rWR2_ADDR.DATAB +WR2_ADDR[11] => rWR2_ADDR.DATAA +WR2_ADDR[11] => rWR2_ADDR.DATAB +WR2_ADDR[12] => rWR2_ADDR.DATAA +WR2_ADDR[12] => rWR2_ADDR.DATAB +WR2_ADDR[13] => rWR2_ADDR.DATAA +WR2_ADDR[13] => rWR2_ADDR.DATAB +WR2_ADDR[14] => rWR2_ADDR.DATAA +WR2_ADDR[14] => rWR2_ADDR.DATAB +WR2_ADDR[15] => rWR2_ADDR.DATAA +WR2_ADDR[15] => rWR2_ADDR.DATAB +WR2_ADDR[16] => rWR2_ADDR.DATAA +WR2_ADDR[16] => rWR2_ADDR.DATAB +WR2_ADDR[17] => rWR2_ADDR.DATAA +WR2_ADDR[17] => rWR2_ADDR.DATAB +WR2_ADDR[18] => rWR2_ADDR.DATAA +WR2_ADDR[18] => rWR2_ADDR.DATAB +WR2_ADDR[19] => rWR2_ADDR.DATAA +WR2_ADDR[19] => rWR2_ADDR.DATAB +WR2_ADDR[20] => rWR2_ADDR.DATAA +WR2_ADDR[20] => rWR2_ADDR.DATAB +WR2_ADDR[21] => rWR2_ADDR.DATAA +WR2_ADDR[21] => rWR2_ADDR.DATAB +WR2_ADDR[22] => rWR2_ADDR.DATAA +WR2_ADDR[22] => rWR2_ADDR.DATAB +WR2_MAX_ADDR[0] => ~NO_FANOUT~ +WR2_MAX_ADDR[1] => ~NO_FANOUT~ +WR2_MAX_ADDR[2] => ~NO_FANOUT~ +WR2_MAX_ADDR[3] => ~NO_FANOUT~ +WR2_MAX_ADDR[4] => ~NO_FANOUT~ +WR2_MAX_ADDR[5] => ~NO_FANOUT~ +WR2_MAX_ADDR[6] => ~NO_FANOUT~ +WR2_MAX_ADDR[7] => ~NO_FANOUT~ +WR2_MAX_ADDR[8] => ~NO_FANOUT~ +WR2_MAX_ADDR[9] => ~NO_FANOUT~ +WR2_MAX_ADDR[10] => ~NO_FANOUT~ +WR2_MAX_ADDR[11] => ~NO_FANOUT~ +WR2_MAX_ADDR[12] => ~NO_FANOUT~ +WR2_MAX_ADDR[13] => ~NO_FANOUT~ +WR2_MAX_ADDR[14] => ~NO_FANOUT~ +WR2_MAX_ADDR[15] => ~NO_FANOUT~ +WR2_MAX_ADDR[16] => ~NO_FANOUT~ +WR2_MAX_ADDR[17] => ~NO_FANOUT~ +WR2_MAX_ADDR[18] => ~NO_FANOUT~ +WR2_MAX_ADDR[19] => ~NO_FANOUT~ +WR2_MAX_ADDR[20] => ~NO_FANOUT~ +WR2_MAX_ADDR[21] => ~NO_FANOUT~ +WR2_MAX_ADDR[22] => ~NO_FANOUT~ +WR2_LENGTH[0] => rWR2_LENGTH[0].DATAIN +WR2_LENGTH[1] => rWR2_LENGTH[1].DATAIN +WR2_LENGTH[2] => rWR2_LENGTH[2].DATAIN +WR2_LENGTH[3] => rWR2_LENGTH[3].DATAIN +WR2_LENGTH[4] => rWR2_LENGTH[4].DATAIN +WR2_LENGTH[5] => rWR2_LENGTH[5].DATAIN +WR2_LENGTH[6] => rWR2_LENGTH[6].DATAIN +WR2_LENGTH[7] => rWR2_LENGTH[7].DATAIN +WR2_LENGTH[8] => rWR2_LENGTH[8].DATAIN +WR2_LOAD => WR2_LOAD.IN1 +WR2_CLK => WR2_CLK.IN1 +RD1_DATA[0] <= Sdram_FIFO:read_fifo1.q +RD1_DATA[1] <= Sdram_FIFO:read_fifo1.q +RD1_DATA[2] <= Sdram_FIFO:read_fifo1.q +RD1_DATA[3] <= Sdram_FIFO:read_fifo1.q +RD1_DATA[4] <= Sdram_FIFO:read_fifo1.q +RD1_DATA[5] <= Sdram_FIFO:read_fifo1.q +RD1_DATA[6] <= Sdram_FIFO:read_fifo1.q +RD1_DATA[7] <= Sdram_FIFO:read_fifo1.q +RD1_DATA[8] <= Sdram_FIFO:read_fifo1.q +RD1_DATA[9] <= Sdram_FIFO:read_fifo1.q +RD1_DATA[10] <= Sdram_FIFO:read_fifo1.q +RD1_DATA[11] <= Sdram_FIFO:read_fifo1.q +RD1_DATA[12] <= Sdram_FIFO:read_fifo1.q +RD1_DATA[13] <= Sdram_FIFO:read_fifo1.q +RD1_DATA[14] <= Sdram_FIFO:read_fifo1.q +RD1_DATA[15] <= Sdram_FIFO:read_fifo1.q +RD1 => RD1.IN1 +RD1_ADDR[0] => rRD1_ADDR.DATAA +RD1_ADDR[0] => rRD1_ADDR.DATAB +RD1_ADDR[1] => rRD1_ADDR.DATAA +RD1_ADDR[1] => rRD1_ADDR.DATAB +RD1_ADDR[2] => rRD1_ADDR.DATAA +RD1_ADDR[2] => rRD1_ADDR.DATAB +RD1_ADDR[3] => rRD1_ADDR.DATAA +RD1_ADDR[3] => rRD1_ADDR.DATAB +RD1_ADDR[4] => rRD1_ADDR.DATAA +RD1_ADDR[4] => rRD1_ADDR.DATAB +RD1_ADDR[5] => rRD1_ADDR.DATAA +RD1_ADDR[5] => rRD1_ADDR.DATAB +RD1_ADDR[6] => rRD1_ADDR.DATAA +RD1_ADDR[6] => rRD1_ADDR.DATAB +RD1_ADDR[7] => rRD1_ADDR.DATAA +RD1_ADDR[7] => rRD1_ADDR.DATAB +RD1_ADDR[8] => rRD1_ADDR.DATAA +RD1_ADDR[8] => rRD1_ADDR.DATAB +RD1_ADDR[9] => rRD1_ADDR.DATAA +RD1_ADDR[9] => rRD1_ADDR.DATAB +RD1_ADDR[10] => rRD1_ADDR.DATAA +RD1_ADDR[10] => rRD1_ADDR.DATAB +RD1_ADDR[11] => rRD1_ADDR.DATAA +RD1_ADDR[11] => rRD1_ADDR.DATAB +RD1_ADDR[12] => rRD1_ADDR.DATAA +RD1_ADDR[12] => rRD1_ADDR.DATAB +RD1_ADDR[13] => rRD1_ADDR.DATAA +RD1_ADDR[13] => rRD1_ADDR.DATAB +RD1_ADDR[14] => rRD1_ADDR.DATAA +RD1_ADDR[14] => rRD1_ADDR.DATAB +RD1_ADDR[15] => rRD1_ADDR.DATAA +RD1_ADDR[15] => rRD1_ADDR.DATAB +RD1_ADDR[16] => rRD1_ADDR.DATAA +RD1_ADDR[16] => rRD1_ADDR.DATAB +RD1_ADDR[17] => rRD1_ADDR.DATAA +RD1_ADDR[17] => rRD1_ADDR.DATAB +RD1_ADDR[18] => rRD1_ADDR.DATAA +RD1_ADDR[18] => rRD1_ADDR.DATAB +RD1_ADDR[19] => rRD1_ADDR.DATAA +RD1_ADDR[19] => rRD1_ADDR.DATAB +RD1_ADDR[20] => rRD1_ADDR.DATAA +RD1_ADDR[20] => rRD1_ADDR.DATAB +RD1_ADDR[21] => rRD1_ADDR.DATAA +RD1_ADDR[21] => rRD1_ADDR.DATAB +RD1_ADDR[22] => rRD1_ADDR.DATAA +RD1_ADDR[22] => rRD1_ADDR.DATAB +RD1_MAX_ADDR[0] => ~NO_FANOUT~ +RD1_MAX_ADDR[1] => ~NO_FANOUT~ +RD1_MAX_ADDR[2] => ~NO_FANOUT~ +RD1_MAX_ADDR[3] => ~NO_FANOUT~ +RD1_MAX_ADDR[4] => ~NO_FANOUT~ +RD1_MAX_ADDR[5] => ~NO_FANOUT~ +RD1_MAX_ADDR[6] => ~NO_FANOUT~ +RD1_MAX_ADDR[7] => ~NO_FANOUT~ +RD1_MAX_ADDR[8] => ~NO_FANOUT~ +RD1_MAX_ADDR[9] => ~NO_FANOUT~ +RD1_MAX_ADDR[10] => ~NO_FANOUT~ +RD1_MAX_ADDR[11] => ~NO_FANOUT~ +RD1_MAX_ADDR[12] => ~NO_FANOUT~ +RD1_MAX_ADDR[13] => ~NO_FANOUT~ +RD1_MAX_ADDR[14] => ~NO_FANOUT~ +RD1_MAX_ADDR[15] => ~NO_FANOUT~ +RD1_MAX_ADDR[16] => ~NO_FANOUT~ +RD1_MAX_ADDR[17] => ~NO_FANOUT~ +RD1_MAX_ADDR[18] => ~NO_FANOUT~ +RD1_MAX_ADDR[19] => ~NO_FANOUT~ +RD1_MAX_ADDR[20] => ~NO_FANOUT~ +RD1_MAX_ADDR[21] => ~NO_FANOUT~ +RD1_MAX_ADDR[22] => ~NO_FANOUT~ +RD1_LENGTH[0] => rRD1_LENGTH[0].DATAIN +RD1_LENGTH[1] => rRD1_LENGTH[1].DATAIN +RD1_LENGTH[2] => rRD1_LENGTH[2].DATAIN +RD1_LENGTH[3] => rRD1_LENGTH[3].DATAIN +RD1_LENGTH[4] => rRD1_LENGTH[4].DATAIN +RD1_LENGTH[5] => rRD1_LENGTH[5].DATAIN +RD1_LENGTH[6] => rRD1_LENGTH[6].DATAIN +RD1_LENGTH[7] => rRD1_LENGTH[7].DATAIN +RD1_LENGTH[8] => rRD1_LENGTH[8].DATAIN +RD1_LOAD => RD1_LOAD.IN1 +RD1_CLK => RD1_CLK.IN1 +RD2_DATA[0] <= Sdram_FIFO:read_fifo2.q +RD2_DATA[1] <= Sdram_FIFO:read_fifo2.q +RD2_DATA[2] <= Sdram_FIFO:read_fifo2.q +RD2_DATA[3] <= Sdram_FIFO:read_fifo2.q +RD2_DATA[4] <= Sdram_FIFO:read_fifo2.q +RD2_DATA[5] <= Sdram_FIFO:read_fifo2.q +RD2_DATA[6] <= Sdram_FIFO:read_fifo2.q +RD2_DATA[7] <= Sdram_FIFO:read_fifo2.q +RD2_DATA[8] <= Sdram_FIFO:read_fifo2.q +RD2_DATA[9] <= Sdram_FIFO:read_fifo2.q +RD2_DATA[10] <= Sdram_FIFO:read_fifo2.q +RD2_DATA[11] <= Sdram_FIFO:read_fifo2.q +RD2_DATA[12] <= Sdram_FIFO:read_fifo2.q +RD2_DATA[13] <= Sdram_FIFO:read_fifo2.q +RD2_DATA[14] <= Sdram_FIFO:read_fifo2.q +RD2_DATA[15] <= Sdram_FIFO:read_fifo2.q +RD2 => RD2.IN1 +RD2_ADDR[0] => rRD2_ADDR.DATAA +RD2_ADDR[0] => rRD2_ADDR.DATAB +RD2_ADDR[1] => rRD2_ADDR.DATAA +RD2_ADDR[1] => rRD2_ADDR.DATAB +RD2_ADDR[2] => rRD2_ADDR.DATAA +RD2_ADDR[2] => rRD2_ADDR.DATAB +RD2_ADDR[3] => rRD2_ADDR.DATAA +RD2_ADDR[3] => rRD2_ADDR.DATAB +RD2_ADDR[4] => rRD2_ADDR.DATAA +RD2_ADDR[4] => rRD2_ADDR.DATAB +RD2_ADDR[5] => rRD2_ADDR.DATAA +RD2_ADDR[5] => rRD2_ADDR.DATAB +RD2_ADDR[6] => rRD2_ADDR.DATAA +RD2_ADDR[6] => rRD2_ADDR.DATAB +RD2_ADDR[7] => rRD2_ADDR.DATAA +RD2_ADDR[7] => rRD2_ADDR.DATAB +RD2_ADDR[8] => rRD2_ADDR.DATAA +RD2_ADDR[8] => rRD2_ADDR.DATAB +RD2_ADDR[9] => rRD2_ADDR.DATAA +RD2_ADDR[9] => rRD2_ADDR.DATAB +RD2_ADDR[10] => rRD2_ADDR.DATAA +RD2_ADDR[10] => rRD2_ADDR.DATAB +RD2_ADDR[11] => rRD2_ADDR.DATAA +RD2_ADDR[11] => rRD2_ADDR.DATAB +RD2_ADDR[12] => rRD2_ADDR.DATAA +RD2_ADDR[12] => rRD2_ADDR.DATAB +RD2_ADDR[13] => rRD2_ADDR.DATAA +RD2_ADDR[13] => rRD2_ADDR.DATAB +RD2_ADDR[14] => rRD2_ADDR.DATAA +RD2_ADDR[14] => rRD2_ADDR.DATAB +RD2_ADDR[15] => rRD2_ADDR.DATAA +RD2_ADDR[15] => rRD2_ADDR.DATAB +RD2_ADDR[16] => rRD2_ADDR.DATAA +RD2_ADDR[16] => rRD2_ADDR.DATAB +RD2_ADDR[17] => rRD2_ADDR.DATAA +RD2_ADDR[17] => rRD2_ADDR.DATAB +RD2_ADDR[18] => rRD2_ADDR.DATAA +RD2_ADDR[18] => rRD2_ADDR.DATAB +RD2_ADDR[19] => rRD2_ADDR.DATAA +RD2_ADDR[19] => rRD2_ADDR.DATAB +RD2_ADDR[20] => rRD2_ADDR.DATAA +RD2_ADDR[20] => rRD2_ADDR.DATAB +RD2_ADDR[21] => rRD2_ADDR.DATAA +RD2_ADDR[21] => rRD2_ADDR.DATAB +RD2_ADDR[22] => rRD2_ADDR.DATAA +RD2_ADDR[22] => rRD2_ADDR.DATAB +RD2_MAX_ADDR[0] => ~NO_FANOUT~ +RD2_MAX_ADDR[1] => ~NO_FANOUT~ +RD2_MAX_ADDR[2] => ~NO_FANOUT~ +RD2_MAX_ADDR[3] => ~NO_FANOUT~ +RD2_MAX_ADDR[4] => ~NO_FANOUT~ +RD2_MAX_ADDR[5] => ~NO_FANOUT~ +RD2_MAX_ADDR[6] => ~NO_FANOUT~ +RD2_MAX_ADDR[7] => ~NO_FANOUT~ +RD2_MAX_ADDR[8] => ~NO_FANOUT~ +RD2_MAX_ADDR[9] => ~NO_FANOUT~ +RD2_MAX_ADDR[10] => ~NO_FANOUT~ +RD2_MAX_ADDR[11] => ~NO_FANOUT~ +RD2_MAX_ADDR[12] => ~NO_FANOUT~ +RD2_MAX_ADDR[13] => ~NO_FANOUT~ +RD2_MAX_ADDR[14] => ~NO_FANOUT~ +RD2_MAX_ADDR[15] => ~NO_FANOUT~ +RD2_MAX_ADDR[16] => ~NO_FANOUT~ +RD2_MAX_ADDR[17] => ~NO_FANOUT~ +RD2_MAX_ADDR[18] => ~NO_FANOUT~ +RD2_MAX_ADDR[19] => ~NO_FANOUT~ +RD2_MAX_ADDR[20] => ~NO_FANOUT~ +RD2_MAX_ADDR[21] => ~NO_FANOUT~ +RD2_MAX_ADDR[22] => ~NO_FANOUT~ +RD2_LENGTH[0] => rRD2_LENGTH[0].DATAIN +RD2_LENGTH[1] => rRD2_LENGTH[1].DATAIN +RD2_LENGTH[2] => rRD2_LENGTH[2].DATAIN +RD2_LENGTH[3] => rRD2_LENGTH[3].DATAIN +RD2_LENGTH[4] => rRD2_LENGTH[4].DATAIN +RD2_LENGTH[5] => rRD2_LENGTH[5].DATAIN +RD2_LENGTH[6] => rRD2_LENGTH[6].DATAIN +RD2_LENGTH[7] => rRD2_LENGTH[7].DATAIN +RD2_LENGTH[8] => rRD2_LENGTH[8].DATAIN +RD2_LOAD => RD2_LOAD.IN1 +RD2_CLK => RD2_CLK.IN1 +SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +BA[0] <= BA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +BA[1] <= BA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +CS_N[0] <= CS_N[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +CS_N[1] <= CS_N[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +CKE <= CKE~reg0.DB_MAX_OUTPUT_PORT_TYPE +RAS_N <= RAS_N~reg0.DB_MAX_OUTPUT_PORT_TYPE +CAS_N <= CAS_N~reg0.DB_MAX_OUTPUT_PORT_TYPE +WE_N <= WE_N~reg0.DB_MAX_OUTPUT_PORT_TYPE +DQ[0] <> DQ[0] +DQ[1] <> DQ[1] +DQ[2] <> DQ[2] +DQ[3] <> DQ[3] +DQ[4] <> DQ[4] +DQ[5] <> DQ[5] +DQ[6] <> DQ[6] +DQ[7] <> DQ[7] +DQ[8] <> DQ[8] +DQ[9] <> DQ[9] +DQ[10] <> DQ[10] +DQ[11] <> DQ[11] +DQ[12] <> DQ[12] +DQ[13] <> DQ[13] +DQ[14] <> DQ[14] +DQ[15] <> DQ[15] +DQM[0] <= DQM[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +DQM[1] <= DQM[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1 +CLK => INIT_REQ~reg0.CLK +CLK => LOAD_MODE~reg0.CLK +CLK => PRECHARGE~reg0.CLK +CLK => REFRESH~reg0.CLK +CLK => init_timer[0].CLK +CLK => init_timer[1].CLK +CLK => init_timer[2].CLK +CLK => init_timer[3].CLK +CLK => init_timer[4].CLK +CLK => init_timer[5].CLK +CLK => init_timer[6].CLK +CLK => init_timer[7].CLK +CLK => init_timer[8].CLK +CLK => init_timer[9].CLK +CLK => init_timer[10].CLK +CLK => init_timer[11].CLK +CLK => init_timer[12].CLK +CLK => init_timer[13].CLK +CLK => init_timer[14].CLK +CLK => init_timer[15].CLK +CLK => REF_REQ~reg0.CLK +CLK => timer[0].CLK +CLK => timer[1].CLK +CLK => timer[2].CLK +CLK => timer[3].CLK +CLK => timer[4].CLK +CLK => timer[5].CLK +CLK => timer[6].CLK +CLK => timer[7].CLK +CLK => timer[8].CLK +CLK => timer[9].CLK +CLK => timer[10].CLK +CLK => timer[11].CLK +CLK => timer[12].CLK +CLK => timer[13].CLK +CLK => timer[14].CLK +CLK => timer[15].CLK +CLK => CMD_ACK~reg0.CLK +CLK => SADDR[0]~reg0.CLK +CLK => SADDR[1]~reg0.CLK +CLK => SADDR[2]~reg0.CLK +CLK => SADDR[3]~reg0.CLK +CLK => SADDR[4]~reg0.CLK +CLK => SADDR[5]~reg0.CLK +CLK => SADDR[6]~reg0.CLK +CLK => SADDR[7]~reg0.CLK +CLK => SADDR[8]~reg0.CLK +CLK => SADDR[9]~reg0.CLK +CLK => SADDR[10]~reg0.CLK +CLK => SADDR[11]~reg0.CLK +CLK => SADDR[12]~reg0.CLK +CLK => SADDR[13]~reg0.CLK +CLK => SADDR[14]~reg0.CLK +CLK => SADDR[15]~reg0.CLK +CLK => SADDR[16]~reg0.CLK +CLK => SADDR[17]~reg0.CLK +CLK => SADDR[18]~reg0.CLK +CLK => SADDR[19]~reg0.CLK +CLK => SADDR[20]~reg0.CLK +CLK => SADDR[21]~reg0.CLK +CLK => SADDR[22]~reg0.CLK +CLK => WRITEA~reg0.CLK +CLK => READA~reg0.CLK +CLK => NOP~reg0.CLK +RESET_N => SADDR[0]~reg0.ACLR +RESET_N => SADDR[1]~reg0.ACLR +RESET_N => SADDR[2]~reg0.ACLR +RESET_N => SADDR[3]~reg0.ACLR +RESET_N => SADDR[4]~reg0.ACLR +RESET_N => SADDR[5]~reg0.ACLR +RESET_N => SADDR[6]~reg0.ACLR +RESET_N => SADDR[7]~reg0.ACLR +RESET_N => SADDR[8]~reg0.ACLR +RESET_N => SADDR[9]~reg0.ACLR +RESET_N => SADDR[10]~reg0.ACLR +RESET_N => SADDR[11]~reg0.ACLR +RESET_N => SADDR[12]~reg0.ACLR +RESET_N => SADDR[13]~reg0.ACLR +RESET_N => SADDR[14]~reg0.ACLR +RESET_N => SADDR[15]~reg0.ACLR +RESET_N => SADDR[16]~reg0.ACLR +RESET_N => SADDR[17]~reg0.ACLR +RESET_N => SADDR[18]~reg0.ACLR +RESET_N => SADDR[19]~reg0.ACLR +RESET_N => SADDR[20]~reg0.ACLR +RESET_N => SADDR[21]~reg0.ACLR +RESET_N => SADDR[22]~reg0.ACLR +RESET_N => WRITEA~reg0.ACLR +RESET_N => READA~reg0.ACLR +RESET_N => NOP~reg0.ACLR +RESET_N => INIT_REQ~reg0.ACLR +RESET_N => LOAD_MODE~reg0.ACLR +RESET_N => PRECHARGE~reg0.ACLR +RESET_N => REFRESH~reg0.ACLR +RESET_N => init_timer[0].ACLR +RESET_N => init_timer[1].ACLR +RESET_N => init_timer[2].ACLR +RESET_N => init_timer[3].ACLR +RESET_N => init_timer[4].ACLR +RESET_N => init_timer[5].ACLR +RESET_N => init_timer[6].ACLR +RESET_N => init_timer[7].ACLR +RESET_N => init_timer[8].ACLR +RESET_N => init_timer[9].ACLR +RESET_N => init_timer[10].ACLR +RESET_N => init_timer[11].ACLR +RESET_N => init_timer[12].ACLR +RESET_N => init_timer[13].ACLR +RESET_N => init_timer[14].ACLR +RESET_N => init_timer[15].ACLR +RESET_N => REF_REQ~reg0.ACLR +RESET_N => timer[0].ACLR +RESET_N => timer[1].ACLR +RESET_N => timer[2].ACLR +RESET_N => timer[3].ACLR +RESET_N => timer[4].ACLR +RESET_N => timer[5].ACLR +RESET_N => timer[6].ACLR +RESET_N => timer[7].ACLR +RESET_N => timer[8].ACLR +RESET_N => timer[9].ACLR +RESET_N => timer[10].ACLR +RESET_N => timer[11].ACLR +RESET_N => timer[12].ACLR +RESET_N => timer[13].ACLR +RESET_N => timer[14].ACLR +RESET_N => timer[15].ACLR +RESET_N => CMD_ACK~reg0.ACLR +CMD[0] => Equal0.IN2 +CMD[0] => Equal1.IN0 +CMD[0] => Equal2.IN2 +CMD[1] => Equal0.IN1 +CMD[1] => Equal1.IN2 +CMD[1] => Equal2.IN0 +CMD[2] => Equal0.IN0 +CMD[2] => Equal1.IN1 +CMD[2] => Equal2.IN1 +ADDR[0] => SADDR[0]~reg0.DATAIN +ADDR[1] => SADDR[1]~reg0.DATAIN +ADDR[2] => SADDR[2]~reg0.DATAIN +ADDR[3] => SADDR[3]~reg0.DATAIN +ADDR[4] => SADDR[4]~reg0.DATAIN +ADDR[5] => SADDR[5]~reg0.DATAIN +ADDR[6] => SADDR[6]~reg0.DATAIN +ADDR[7] => SADDR[7]~reg0.DATAIN +ADDR[8] => SADDR[8]~reg0.DATAIN +ADDR[9] => SADDR[9]~reg0.DATAIN +ADDR[10] => SADDR[10]~reg0.DATAIN +ADDR[11] => SADDR[11]~reg0.DATAIN +ADDR[12] => SADDR[12]~reg0.DATAIN +ADDR[13] => SADDR[13]~reg0.DATAIN +ADDR[14] => SADDR[14]~reg0.DATAIN +ADDR[15] => SADDR[15]~reg0.DATAIN +ADDR[16] => SADDR[16]~reg0.DATAIN +ADDR[17] => SADDR[17]~reg0.DATAIN +ADDR[18] => SADDR[18]~reg0.DATAIN +ADDR[19] => SADDR[19]~reg0.DATAIN +ADDR[20] => SADDR[20]~reg0.DATAIN +ADDR[21] => SADDR[21]~reg0.DATAIN +ADDR[22] => SADDR[22]~reg0.DATAIN +REF_ACK => timer.OUTPUTSELECT +REF_ACK => timer.OUTPUTSELECT +REF_ACK => timer.OUTPUTSELECT +REF_ACK => timer.OUTPUTSELECT +REF_ACK => timer.OUTPUTSELECT +REF_ACK => timer.OUTPUTSELECT +REF_ACK => timer.OUTPUTSELECT +REF_ACK => timer.OUTPUTSELECT +REF_ACK => timer.OUTPUTSELECT +REF_ACK => timer.OUTPUTSELECT +REF_ACK => timer.OUTPUTSELECT +REF_ACK => timer.OUTPUTSELECT +REF_ACK => timer.OUTPUTSELECT +REF_ACK => timer.OUTPUTSELECT +REF_ACK => timer.OUTPUTSELECT +REF_ACK => timer.OUTPUTSELECT +REF_ACK => REF_REQ.OUTPUTSELECT +INIT_ACK => ~NO_FANOUT~ +CM_ACK => always1.IN1 +NOP <= NOP~reg0.DB_MAX_OUTPUT_PORT_TYPE +READA <= READA~reg0.DB_MAX_OUTPUT_PORT_TYPE +WRITEA <= WRITEA~reg0.DB_MAX_OUTPUT_PORT_TYPE +REFRESH <= REFRESH~reg0.DB_MAX_OUTPUT_PORT_TYPE +PRECHARGE <= PRECHARGE~reg0.DB_MAX_OUTPUT_PORT_TYPE +LOAD_MODE <= LOAD_MODE~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[0] <= SADDR[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[1] <= SADDR[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[2] <= SADDR[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[3] <= SADDR[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[4] <= SADDR[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[5] <= SADDR[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[6] <= SADDR[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[7] <= SADDR[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[8] <= SADDR[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[9] <= SADDR[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[10] <= SADDR[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[11] <= SADDR[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[12] <= SADDR[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[13] <= SADDR[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[14] <= SADDR[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[15] <= SADDR[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[16] <= SADDR[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[17] <= SADDR[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[18] <= SADDR[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[19] <= SADDR[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[20] <= SADDR[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[21] <= SADDR[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SADDR[22] <= SADDR[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +REF_REQ <= REF_REQ~reg0.DB_MAX_OUTPUT_PORT_TYPE +INIT_REQ <= INIT_REQ~reg0.DB_MAX_OUTPUT_PORT_TYPE +CMD_ACK <= CMD_ACK~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1 +CLK => CKE~reg0.CLK +CLK => WE_N~reg0.CLK +CLK => CAS_N~reg0.CLK +CLK => RAS_N~reg0.CLK +CLK => CS_N[0]~reg0.CLK +CLK => CS_N[1]~reg0.CLK +CLK => BA[0]~reg0.CLK +CLK => BA[1]~reg0.CLK +CLK => SA[0]~reg0.CLK +CLK => SA[1]~reg0.CLK +CLK => SA[2]~reg0.CLK +CLK => SA[3]~reg0.CLK +CLK => SA[4]~reg0.CLK +CLK => SA[5]~reg0.CLK +CLK => SA[6]~reg0.CLK +CLK => SA[7]~reg0.CLK +CLK => SA[8]~reg0.CLK +CLK => SA[9]~reg0.CLK +CLK => SA[10]~reg0.CLK +CLK => SA[11]~reg0.CLK +CLK => REF_ACK~reg0.CLK +CLK => CM_ACK~reg0.CLK +CLK => do_rw.CLK +CLK => rw_shift[0].CLK +CLK => rw_shift[1].CLK +CLK => oe4.CLK +CLK => OE~reg0.CLK +CLK => ex_write.CLK +CLK => ex_read.CLK +CLK => rp_done.CLK +CLK => rp_shift[0].CLK +CLK => rp_shift[1].CLK +CLK => rp_shift[2].CLK +CLK => rp_shift[3].CLK +CLK => rw_flag.CLK +CLK => command_delay[0].CLK +CLK => command_delay[1].CLK +CLK => command_delay[2].CLK +CLK => command_delay[3].CLK +CLK => command_delay[4].CLK +CLK => command_delay[5].CLK +CLK => command_delay[6].CLK +CLK => command_delay[7].CLK +CLK => command_done.CLK +CLK => do_initial.CLK +CLK => do_load_mode.CLK +CLK => do_precharge.CLK +CLK => do_refresh.CLK +CLK => do_writea.CLK +CLK => do_reada.CLK +RESET_N => CKE~reg0.DATAIN +RESET_N => SA.OUTPUTSELECT +RESET_N => SA.OUTPUTSELECT +RESET_N => SA.OUTPUTSELECT +RESET_N => SA.OUTPUTSELECT +RESET_N => SA.OUTPUTSELECT +RESET_N => SA.OUTPUTSELECT +RESET_N => SA.OUTPUTSELECT +RESET_N => SA.OUTPUTSELECT +RESET_N => SA.OUTPUTSELECT +RESET_N => SA.OUTPUTSELECT +RESET_N => SA.OUTPUTSELECT +RESET_N => SA.OUTPUTSELECT +RESET_N => BA.OUTPUTSELECT +RESET_N => BA.OUTPUTSELECT +RESET_N => CS_N.OUTPUTSELECT +RESET_N => CS_N.OUTPUTSELECT +RESET_N => RAS_N.OUTPUTSELECT +RESET_N => CAS_N.OUTPUTSELECT +RESET_N => WE_N.OUTPUTSELECT +RESET_N => REF_ACK~reg0.ACLR +RESET_N => CM_ACK~reg0.ACLR +RESET_N => OE~reg0.ACLR +RESET_N => ex_write.ACLR +RESET_N => ex_read.ACLR +RESET_N => rp_done.ACLR +RESET_N => rp_shift[0].ACLR +RESET_N => rp_shift[1].ACLR +RESET_N => rp_shift[2].ACLR +RESET_N => rp_shift[3].ACLR +RESET_N => rw_flag.ACLR +RESET_N => command_delay[0].ACLR +RESET_N => command_delay[1].ACLR +RESET_N => command_delay[2].ACLR +RESET_N => command_delay[3].ACLR +RESET_N => command_delay[4].ACLR +RESET_N => command_delay[5].ACLR +RESET_N => command_delay[6].ACLR +RESET_N => command_delay[7].ACLR +RESET_N => command_done.ACLR +RESET_N => do_initial.ACLR +RESET_N => do_load_mode.ACLR +RESET_N => do_precharge.ACLR +RESET_N => do_refresh.ACLR +RESET_N => do_writea.ACLR +RESET_N => do_reada.ACLR +RESET_N => do_rw.ACLR +RESET_N => rw_shift[0].ACLR +RESET_N => rw_shift[1].ACLR +RESET_N => oe4.ENA +SADDR[0] => SA.DATAA +SADDR[1] => SA.DATAA +SADDR[2] => SA.DATAA +SADDR[3] => SA.DATAA +SADDR[4] => SA.DATAA +SADDR[5] => SA.DATAA +SADDR[6] => SA.DATAA +SADDR[7] => SA.DATAA +SADDR[8] => SA.DATAB +SADDR[9] => SA.DATAB +SADDR[10] => SA.DATAB +SADDR[11] => SA.DATAB +SADDR[12] => SA.DATAB +SADDR[13] => SA.DATAB +SADDR[14] => SA.DATAB +SADDR[15] => SA.DATAB +SADDR[16] => SA.DATAB +SADDR[17] => SA.DATAB +SADDR[18] => SA.DATAB +SADDR[19] => SA.DATAB +SADDR[20] => BA.DATAA +SADDR[21] => BA.DATAA +SADDR[22] => CS_N.DATAA +SADDR[22] => CS_N.DATAA +NOP => ~NO_FANOUT~ +READA => always0.IN1 +WRITEA => always0.IN1 +REFRESH => always0.IN0 +PRECHARGE => always0.IN1 +LOAD_MODE => always0.IN1 +REF_REQ => always0.IN1 +REF_REQ => always3.IN1 +REF_REQ => always0.IN1 +REF_REQ => always0.IN1 +INIT_REQ => do_reada.OUTPUTSELECT +INIT_REQ => do_writea.OUTPUTSELECT +INIT_REQ => do_refresh.OUTPUTSELECT +INIT_REQ => do_precharge.OUTPUTSELECT +INIT_REQ => do_load_mode.OUTPUTSELECT +INIT_REQ => command_done.OUTPUTSELECT +INIT_REQ => command_delay.OUTPUTSELECT +INIT_REQ => command_delay.OUTPUTSELECT +INIT_REQ => command_delay.OUTPUTSELECT +INIT_REQ => command_delay.OUTPUTSELECT +INIT_REQ => command_delay.OUTPUTSELECT +INIT_REQ => command_delay.OUTPUTSELECT +INIT_REQ => command_delay.OUTPUTSELECT +INIT_REQ => command_delay.OUTPUTSELECT +INIT_REQ => rw_flag.OUTPUTSELECT +INIT_REQ => rp_shift.OUTPUTSELECT +INIT_REQ => rp_shift.OUTPUTSELECT +INIT_REQ => rp_shift.OUTPUTSELECT +INIT_REQ => rp_shift.OUTPUTSELECT +INIT_REQ => rp_done.OUTPUTSELECT +INIT_REQ => ex_read.OUTPUTSELECT +INIT_REQ => ex_write.OUTPUTSELECT +INIT_REQ => do_initial.DATAIN +PM_STOP => rp_shift.OUTPUTSELECT +PM_STOP => rp_shift.OUTPUTSELECT +PM_STOP => rp_shift.OUTPUTSELECT +PM_STOP => rp_shift.OUTPUTSELECT +PM_STOP => rp_done.OUTPUTSELECT +PM_STOP => ex_read.OUTPUTSELECT +PM_STOP => ex_write.OUTPUTSELECT +PM_STOP => always1.IN1 +PM_DONE => ~NO_FANOUT~ +REF_ACK <= REF_ACK~reg0.DB_MAX_OUTPUT_PORT_TYPE +CM_ACK <= CM_ACK~reg0.DB_MAX_OUTPUT_PORT_TYPE +OE <= OE~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +BA[0] <= BA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +BA[1] <= BA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +CS_N[0] <= CS_N[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +CS_N[1] <= CS_N[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +CKE <= CKE~reg0.DB_MAX_OUTPUT_PORT_TYPE +RAS_N <= RAS_N~reg0.DB_MAX_OUTPUT_PORT_TYPE +CAS_N <= CAS_N~reg0.DB_MAX_OUTPUT_PORT_TYPE +WE_N <= WE_N~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1 +CLK => DQM[0]~reg0.CLK +CLK => DQM[1]~reg0.CLK +RESET_N => DQM[0]~reg0.PRESET +RESET_N => DQM[1]~reg0.ACLR +DATAIN[0] => DQOUT[0].DATAIN +DATAIN[1] => DQOUT[1].DATAIN +DATAIN[2] => DQOUT[2].DATAIN +DATAIN[3] => DQOUT[3].DATAIN +DATAIN[4] => DQOUT[4].DATAIN +DATAIN[5] => DQOUT[5].DATAIN +DATAIN[6] => DQOUT[6].DATAIN +DATAIN[7] => DQOUT[7].DATAIN +DATAIN[8] => DQOUT[8].DATAIN +DATAIN[9] => DQOUT[9].DATAIN +DATAIN[10] => DQOUT[10].DATAIN +DATAIN[11] => DQOUT[11].DATAIN +DATAIN[12] => DQOUT[12].DATAIN +DATAIN[13] => DQOUT[13].DATAIN +DATAIN[14] => DQOUT[14].DATAIN +DATAIN[15] => DQOUT[15].DATAIN +DM[0] => DQM[0]~reg0.DATAIN +DM[1] => DQM[1]~reg0.DATAIN +DQOUT[0] <= DATAIN[0].DB_MAX_OUTPUT_PORT_TYPE +DQOUT[1] <= DATAIN[1].DB_MAX_OUTPUT_PORT_TYPE +DQOUT[2] <= DATAIN[2].DB_MAX_OUTPUT_PORT_TYPE +DQOUT[3] <= DATAIN[3].DB_MAX_OUTPUT_PORT_TYPE +DQOUT[4] <= DATAIN[4].DB_MAX_OUTPUT_PORT_TYPE +DQOUT[5] <= DATAIN[5].DB_MAX_OUTPUT_PORT_TYPE +DQOUT[6] <= DATAIN[6].DB_MAX_OUTPUT_PORT_TYPE +DQOUT[7] <= DATAIN[7].DB_MAX_OUTPUT_PORT_TYPE +DQOUT[8] <= DATAIN[8].DB_MAX_OUTPUT_PORT_TYPE +DQOUT[9] <= DATAIN[9].DB_MAX_OUTPUT_PORT_TYPE +DQOUT[10] <= DATAIN[10].DB_MAX_OUTPUT_PORT_TYPE +DQOUT[11] <= DATAIN[11].DB_MAX_OUTPUT_PORT_TYPE +DQOUT[12] <= DATAIN[12].DB_MAX_OUTPUT_PORT_TYPE +DQOUT[13] <= DATAIN[13].DB_MAX_OUTPUT_PORT_TYPE +DQOUT[14] <= DATAIN[14].DB_MAX_OUTPUT_PORT_TYPE +DQOUT[15] <= DATAIN[15].DB_MAX_OUTPUT_PORT_TYPE +DQM[0] <= DQM[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +DQM[1] <= DQM[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1 +aclr => aclr.IN1 +data[0] => data[0].IN1 +data[1] => data[1].IN1 +data[2] => data[2].IN1 +data[3] => data[3].IN1 +data[4] => data[4].IN1 +data[5] => data[5].IN1 +data[6] => data[6].IN1 +data[7] => data[7].IN1 +data[8] => data[8].IN1 +data[9] => data[9].IN1 +data[10] => data[10].IN1 +data[11] => data[11].IN1 +data[12] => data[12].IN1 +data[13] => data[13].IN1 +data[14] => data[14].IN1 +data[15] => data[15].IN1 +rdclk => rdclk.IN1 +rdreq => rdreq.IN1 +wrclk => wrclk.IN1 +wrreq => wrreq.IN1 +q[0] <= dcfifo:dcfifo_component.q +q[1] <= dcfifo:dcfifo_component.q +q[2] <= dcfifo:dcfifo_component.q +q[3] <= dcfifo:dcfifo_component.q +q[4] <= dcfifo:dcfifo_component.q +q[5] <= dcfifo:dcfifo_component.q +q[6] <= dcfifo:dcfifo_component.q +q[7] <= dcfifo:dcfifo_component.q +q[8] <= dcfifo:dcfifo_component.q +q[9] <= dcfifo:dcfifo_component.q +q[10] <= dcfifo:dcfifo_component.q +q[11] <= dcfifo:dcfifo_component.q +q[12] <= dcfifo:dcfifo_component.q +q[13] <= dcfifo:dcfifo_component.q +q[14] <= dcfifo:dcfifo_component.q +q[15] <= dcfifo:dcfifo_component.q +rdempty <= dcfifo:dcfifo_component.rdempty +rdusedw[0] <= dcfifo:dcfifo_component.rdusedw +rdusedw[1] <= dcfifo:dcfifo_component.rdusedw +rdusedw[2] <= dcfifo:dcfifo_component.rdusedw +rdusedw[3] <= dcfifo:dcfifo_component.rdusedw +rdusedw[4] <= dcfifo:dcfifo_component.rdusedw +rdusedw[5] <= dcfifo:dcfifo_component.rdusedw +rdusedw[6] <= dcfifo:dcfifo_component.rdusedw +rdusedw[7] <= dcfifo:dcfifo_component.rdusedw +rdusedw[8] <= dcfifo:dcfifo_component.rdusedw +wrfull <= dcfifo:dcfifo_component.wrfull +wrusedw[0] <= dcfifo:dcfifo_component.wrusedw +wrusedw[1] <= dcfifo:dcfifo_component.wrusedw +wrusedw[2] <= dcfifo:dcfifo_component.wrusedw +wrusedw[3] <= dcfifo:dcfifo_component.wrusedw +wrusedw[4] <= dcfifo:dcfifo_component.wrusedw +wrusedw[5] <= dcfifo:dcfifo_component.wrusedw +wrusedw[6] <= dcfifo:dcfifo_component.wrusedw +wrusedw[7] <= dcfifo:dcfifo_component.wrusedw +wrusedw[8] <= dcfifo:dcfifo_component.wrusedw + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component +data[0] => dcfifo_v5o1:auto_generated.data[0] +data[1] => dcfifo_v5o1:auto_generated.data[1] +data[2] => dcfifo_v5o1:auto_generated.data[2] +data[3] => dcfifo_v5o1:auto_generated.data[3] +data[4] => dcfifo_v5o1:auto_generated.data[4] +data[5] => dcfifo_v5o1:auto_generated.data[5] +data[6] => dcfifo_v5o1:auto_generated.data[6] +data[7] => dcfifo_v5o1:auto_generated.data[7] +data[8] => dcfifo_v5o1:auto_generated.data[8] +data[9] => dcfifo_v5o1:auto_generated.data[9] +data[10] => dcfifo_v5o1:auto_generated.data[10] +data[11] => dcfifo_v5o1:auto_generated.data[11] +data[12] => dcfifo_v5o1:auto_generated.data[12] +data[13] => dcfifo_v5o1:auto_generated.data[13] +data[14] => dcfifo_v5o1:auto_generated.data[14] +data[15] => dcfifo_v5o1:auto_generated.data[15] +q[0] <= dcfifo_v5o1:auto_generated.q[0] +q[1] <= dcfifo_v5o1:auto_generated.q[1] +q[2] <= dcfifo_v5o1:auto_generated.q[2] +q[3] <= dcfifo_v5o1:auto_generated.q[3] +q[4] <= dcfifo_v5o1:auto_generated.q[4] +q[5] <= dcfifo_v5o1:auto_generated.q[5] +q[6] <= dcfifo_v5o1:auto_generated.q[6] +q[7] <= dcfifo_v5o1:auto_generated.q[7] +q[8] <= dcfifo_v5o1:auto_generated.q[8] +q[9] <= dcfifo_v5o1:auto_generated.q[9] +q[10] <= dcfifo_v5o1:auto_generated.q[10] +q[11] <= dcfifo_v5o1:auto_generated.q[11] +q[12] <= dcfifo_v5o1:auto_generated.q[12] +q[13] <= dcfifo_v5o1:auto_generated.q[13] +q[14] <= dcfifo_v5o1:auto_generated.q[14] +q[15] <= dcfifo_v5o1:auto_generated.q[15] +rdclk => dcfifo_v5o1:auto_generated.rdclk +rdreq => dcfifo_v5o1:auto_generated.rdreq +wrclk => dcfifo_v5o1:auto_generated.wrclk +wrreq => dcfifo_v5o1:auto_generated.wrreq +aclr => dcfifo_v5o1:auto_generated.aclr +rdempty <= dcfifo_v5o1:auto_generated.rdempty +rdfull <= <UNC> +wrempty <= <GND> +wrfull <= dcfifo_v5o1:auto_generated.wrfull +rdusedw[0] <= dcfifo_v5o1:auto_generated.rdusedw[0] +rdusedw[1] <= dcfifo_v5o1:auto_generated.rdusedw[1] +rdusedw[2] <= dcfifo_v5o1:auto_generated.rdusedw[2] +rdusedw[3] <= dcfifo_v5o1:auto_generated.rdusedw[3] +rdusedw[4] <= dcfifo_v5o1:auto_generated.rdusedw[4] +rdusedw[5] <= dcfifo_v5o1:auto_generated.rdusedw[5] +rdusedw[6] <= dcfifo_v5o1:auto_generated.rdusedw[6] +rdusedw[7] <= dcfifo_v5o1:auto_generated.rdusedw[7] +rdusedw[8] <= dcfifo_v5o1:auto_generated.rdusedw[8] +wrusedw[0] <= dcfifo_v5o1:auto_generated.wrusedw[0] +wrusedw[1] <= dcfifo_v5o1:auto_generated.wrusedw[1] +wrusedw[2] <= dcfifo_v5o1:auto_generated.wrusedw[2] +wrusedw[3] <= dcfifo_v5o1:auto_generated.wrusedw[3] +wrusedw[4] <= dcfifo_v5o1:auto_generated.wrusedw[4] +wrusedw[5] <= dcfifo_v5o1:auto_generated.wrusedw[5] +wrusedw[6] <= dcfifo_v5o1:auto_generated.wrusedw[6] +wrusedw[7] <= dcfifo_v5o1:auto_generated.wrusedw[7] +wrusedw[8] <= dcfifo_v5o1:auto_generated.wrusedw[8] + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated +aclr => a_graycounter_s57:rdptr_g1p.aclr +aclr => a_graycounter_ojc:wrptr_g1p.aclr +aclr => altsyncram_de51:fifo_ram.aclr1 +aclr => delayed_wrptr_g[9].IN0 +aclr => rdptr_g[9].IN0 +aclr => wrptr_g[9].IN0 +aclr => _.IN0 +aclr => _.IN0 +aclr => _.IN0 +aclr => _.IN0 +aclr => _.IN0 +aclr => _.IN0 +data[0] => altsyncram_de51:fifo_ram.data_a[0] +data[1] => altsyncram_de51:fifo_ram.data_a[1] +data[2] => altsyncram_de51:fifo_ram.data_a[2] +data[3] => altsyncram_de51:fifo_ram.data_a[3] +data[4] => altsyncram_de51:fifo_ram.data_a[4] +data[5] => altsyncram_de51:fifo_ram.data_a[5] +data[6] => altsyncram_de51:fifo_ram.data_a[6] +data[7] => altsyncram_de51:fifo_ram.data_a[7] +data[8] => altsyncram_de51:fifo_ram.data_a[8] +data[9] => altsyncram_de51:fifo_ram.data_a[9] +data[10] => altsyncram_de51:fifo_ram.data_a[10] +data[11] => altsyncram_de51:fifo_ram.data_a[11] +data[12] => altsyncram_de51:fifo_ram.data_a[12] +data[13] => altsyncram_de51:fifo_ram.data_a[13] +data[14] => altsyncram_de51:fifo_ram.data_a[14] +data[15] => altsyncram_de51:fifo_ram.data_a[15] +q[0] <= altsyncram_de51:fifo_ram.q_b[0] +q[1] <= altsyncram_de51:fifo_ram.q_b[1] +q[2] <= altsyncram_de51:fifo_ram.q_b[2] +q[3] <= altsyncram_de51:fifo_ram.q_b[3] +q[4] <= altsyncram_de51:fifo_ram.q_b[4] +q[5] <= altsyncram_de51:fifo_ram.q_b[5] +q[6] <= altsyncram_de51:fifo_ram.q_b[6] +q[7] <= altsyncram_de51:fifo_ram.q_b[7] +q[8] <= altsyncram_de51:fifo_ram.q_b[8] +q[9] <= altsyncram_de51:fifo_ram.q_b[9] +q[10] <= altsyncram_de51:fifo_ram.q_b[10] +q[11] <= altsyncram_de51:fifo_ram.q_b[11] +q[12] <= altsyncram_de51:fifo_ram.q_b[12] +q[13] <= altsyncram_de51:fifo_ram.q_b[13] +q[14] <= altsyncram_de51:fifo_ram.q_b[14] +q[15] <= altsyncram_de51:fifo_ram.q_b[15] +rdclk => a_graycounter_s57:rdptr_g1p.clock +rdclk => altsyncram_de51:fifo_ram.clock1 +rdclk => dffpipe_oe9:rs_brp.clock +rdclk => dffpipe_oe9:rs_bwp.clock +rdclk => alt_synch_pipe_qld:rs_dgwp.clock +rdclk => rdptr_g[9].CLK +rdclk => rdptr_g[8].CLK +rdclk => rdptr_g[7].CLK +rdclk => rdptr_g[6].CLK +rdclk => rdptr_g[5].CLK +rdclk => rdptr_g[4].CLK +rdclk => rdptr_g[3].CLK +rdclk => rdptr_g[2].CLK +rdclk => rdptr_g[1].CLK +rdclk => rdptr_g[0].CLK +rdempty <= int_rdempty.DB_MAX_OUTPUT_PORT_TYPE +rdreq => valid_rdreq.IN0 +rdusedw[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +wrclk => a_graycounter_ojc:wrptr_g1p.clock +wrclk => altsyncram_de51:fifo_ram.clock0 +wrclk => dffpipe_oe9:ws_brp.clock +wrclk => dffpipe_oe9:ws_bwp.clock +wrclk => alt_synch_pipe_rld:ws_dgrp.clock +wrclk => delayed_wrptr_g[9].CLK +wrclk => delayed_wrptr_g[8].CLK +wrclk => delayed_wrptr_g[7].CLK +wrclk => delayed_wrptr_g[6].CLK +wrclk => delayed_wrptr_g[5].CLK +wrclk => delayed_wrptr_g[4].CLK +wrclk => delayed_wrptr_g[3].CLK +wrclk => delayed_wrptr_g[2].CLK +wrclk => delayed_wrptr_g[1].CLK +wrclk => delayed_wrptr_g[0].CLK +wrclk => wrptr_g[9].CLK +wrclk => wrptr_g[8].CLK +wrclk => wrptr_g[7].CLK +wrclk => wrptr_g[6].CLK +wrclk => wrptr_g[5].CLK +wrclk => wrptr_g[4].CLK +wrclk => wrptr_g[3].CLK +wrclk => wrptr_g[2].CLK +wrclk => wrptr_g[1].CLK +wrclk => wrptr_g[0].CLK +wrfull <= int_wrfull.DB_MAX_OUTPUT_PORT_TYPE +wrreq => valid_wrreq.IN0 +wrusedw[0] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[1] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[2] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[3] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[4] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[5] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[6] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[7] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[8] <= op_2.DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin +bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE +bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE +bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE +bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE +bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE +bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE +bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE +bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE +bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE +bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE +gray[0] => xor0.IN0 +gray[1] => xor1.IN0 +gray[2] => xor2.IN0 +gray[3] => xor3.IN0 +gray[4] => xor4.IN0 +gray[5] => xor5.IN0 +gray[6] => xor6.IN0 +gray[7] => xor7.IN0 +gray[8] => xor8.IN1 +gray[9] => bin[9].DATAIN +gray[9] => xor8.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin +bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE +bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE +bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE +bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE +bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE +bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE +bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE +bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE +bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE +bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE +gray[0] => xor0.IN0 +gray[1] => xor1.IN0 +gray[2] => xor2.IN0 +gray[3] => xor3.IN0 +gray[4] => xor4.IN0 +gray[5] => xor5.IN0 +gray[6] => xor6.IN0 +gray[7] => xor7.IN0 +gray[8] => xor8.IN1 +gray[9] => bin[9].DATAIN +gray[9] => xor8.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin +bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE +bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE +bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE +bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE +bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE +bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE +bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE +bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE +bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE +bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE +gray[0] => xor0.IN0 +gray[1] => xor1.IN0 +gray[2] => xor2.IN0 +gray[3] => xor3.IN0 +gray[4] => xor4.IN0 +gray[5] => xor5.IN0 +gray[6] => xor6.IN0 +gray[7] => xor7.IN0 +gray[8] => xor8.IN1 +gray[9] => bin[9].DATAIN +gray[9] => xor8.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin +bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE +bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE +bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE +bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE +bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE +bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE +bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE +bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE +bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE +bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE +gray[0] => xor0.IN0 +gray[1] => xor1.IN0 +gray[2] => xor2.IN0 +gray[3] => xor3.IN0 +gray[4] => xor4.IN0 +gray[5] => xor5.IN0 +gray[6] => xor6.IN0 +gray[7] => xor7.IN0 +gray[8] => xor8.IN1 +gray[9] => bin[9].DATAIN +gray[9] => xor8.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p +aclr => counter5a1.IN0 +aclr => counter5a0.IN0 +aclr => parity6.IN0 +aclr => sub_parity7a[2].IN0 +aclr => sub_parity7a[1].IN0 +aclr => sub_parity7a[0].IN0 +clock => counter5a0.CLK +clock => counter5a1.CLK +clock => counter5a2.CLK +clock => counter5a3.CLK +clock => counter5a4.CLK +clock => counter5a5.CLK +clock => counter5a6.CLK +clock => counter5a7.CLK +clock => counter5a8.CLK +clock => counter5a9.CLK +clock => parity6.CLK +clock => sub_parity7a[2].CLK +clock => sub_parity7a[1].CLK +clock => sub_parity7a[0].CLK +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => cntr_cout[0].IN0 +cnt_en => parity_cout.IN1 +q[0] <= counter5a0.DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter5a1.DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter5a2.DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter5a3.DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter5a4.DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter5a5.DB_MAX_OUTPUT_PORT_TYPE +q[6] <= counter5a6.DB_MAX_OUTPUT_PORT_TYPE +q[7] <= counter5a7.DB_MAX_OUTPUT_PORT_TYPE +q[8] <= counter5a8.DB_MAX_OUTPUT_PORT_TYPE +q[9] <= counter5a9.DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p +aclr => counter8a1.IN0 +aclr => counter8a0.IN0 +aclr => parity9.IN0 +aclr => sub_parity10a[2].IN0 +aclr => sub_parity10a[1].IN0 +aclr => sub_parity10a[0].IN0 +clock => counter8a0.CLK +clock => counter8a1.CLK +clock => counter8a2.CLK +clock => counter8a3.CLK +clock => counter8a4.CLK +clock => counter8a5.CLK +clock => counter8a6.CLK +clock => counter8a7.CLK +clock => counter8a8.CLK +clock => counter8a9.CLK +clock => parity9.CLK +clock => sub_parity10a[2].CLK +clock => sub_parity10a[1].CLK +clock => sub_parity10a[0].CLK +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => cntr_cout[0].IN0 +cnt_en => parity_cout.IN1 +q[0] <= counter8a0.DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter8a1.DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter8a2.DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter8a3.DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter8a4.DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter8a5.DB_MAX_OUTPUT_PORT_TYPE +q[6] <= counter8a6.DB_MAX_OUTPUT_PORT_TYPE +q[7] <= counter8a7.DB_MAX_OUTPUT_PORT_TYPE +q[8] <= counter8a8.DB_MAX_OUTPUT_PORT_TYPE +q[9] <= counter8a9.DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram +aclr1 => ram_block11a0.CLR1 +aclr1 => ram_block11a1.CLR1 +aclr1 => ram_block11a2.CLR1 +aclr1 => ram_block11a3.CLR1 +aclr1 => ram_block11a4.CLR1 +aclr1 => ram_block11a5.CLR1 +aclr1 => ram_block11a6.CLR1 +aclr1 => ram_block11a7.CLR1 +aclr1 => ram_block11a8.CLR1 +aclr1 => ram_block11a9.CLR1 +aclr1 => ram_block11a10.CLR1 +aclr1 => ram_block11a11.CLR1 +aclr1 => ram_block11a12.CLR1 +aclr1 => ram_block11a13.CLR1 +aclr1 => ram_block11a14.CLR1 +aclr1 => ram_block11a15.CLR1 +address_a[0] => ram_block11a0.PORTAADDR +address_a[0] => ram_block11a1.PORTAADDR +address_a[0] => ram_block11a2.PORTAADDR +address_a[0] => ram_block11a3.PORTAADDR +address_a[0] => ram_block11a4.PORTAADDR +address_a[0] => ram_block11a5.PORTAADDR +address_a[0] => ram_block11a6.PORTAADDR +address_a[0] => ram_block11a7.PORTAADDR +address_a[0] => ram_block11a8.PORTAADDR +address_a[0] => ram_block11a9.PORTAADDR +address_a[0] => ram_block11a10.PORTAADDR +address_a[0] => ram_block11a11.PORTAADDR +address_a[0] => ram_block11a12.PORTAADDR +address_a[0] => ram_block11a13.PORTAADDR +address_a[0] => ram_block11a14.PORTAADDR +address_a[0] => ram_block11a15.PORTAADDR +address_a[1] => ram_block11a0.PORTAADDR1 +address_a[1] => ram_block11a1.PORTAADDR1 +address_a[1] => ram_block11a2.PORTAADDR1 +address_a[1] => ram_block11a3.PORTAADDR1 +address_a[1] => ram_block11a4.PORTAADDR1 +address_a[1] => ram_block11a5.PORTAADDR1 +address_a[1] => ram_block11a6.PORTAADDR1 +address_a[1] => ram_block11a7.PORTAADDR1 +address_a[1] => ram_block11a8.PORTAADDR1 +address_a[1] => ram_block11a9.PORTAADDR1 +address_a[1] => ram_block11a10.PORTAADDR1 +address_a[1] => ram_block11a11.PORTAADDR1 +address_a[1] => ram_block11a12.PORTAADDR1 +address_a[1] => ram_block11a13.PORTAADDR1 +address_a[1] => ram_block11a14.PORTAADDR1 +address_a[1] => ram_block11a15.PORTAADDR1 +address_a[2] => ram_block11a0.PORTAADDR2 +address_a[2] => ram_block11a1.PORTAADDR2 +address_a[2] => ram_block11a2.PORTAADDR2 +address_a[2] => ram_block11a3.PORTAADDR2 +address_a[2] => ram_block11a4.PORTAADDR2 +address_a[2] => ram_block11a5.PORTAADDR2 +address_a[2] => ram_block11a6.PORTAADDR2 +address_a[2] => ram_block11a7.PORTAADDR2 +address_a[2] => ram_block11a8.PORTAADDR2 +address_a[2] => ram_block11a9.PORTAADDR2 +address_a[2] => ram_block11a10.PORTAADDR2 +address_a[2] => ram_block11a11.PORTAADDR2 +address_a[2] => ram_block11a12.PORTAADDR2 +address_a[2] => ram_block11a13.PORTAADDR2 +address_a[2] => ram_block11a14.PORTAADDR2 +address_a[2] => ram_block11a15.PORTAADDR2 +address_a[3] => ram_block11a0.PORTAADDR3 +address_a[3] => ram_block11a1.PORTAADDR3 +address_a[3] => ram_block11a2.PORTAADDR3 +address_a[3] => ram_block11a3.PORTAADDR3 +address_a[3] => ram_block11a4.PORTAADDR3 +address_a[3] => ram_block11a5.PORTAADDR3 +address_a[3] => ram_block11a6.PORTAADDR3 +address_a[3] => ram_block11a7.PORTAADDR3 +address_a[3] => ram_block11a8.PORTAADDR3 +address_a[3] => ram_block11a9.PORTAADDR3 +address_a[3] => ram_block11a10.PORTAADDR3 +address_a[3] => ram_block11a11.PORTAADDR3 +address_a[3] => ram_block11a12.PORTAADDR3 +address_a[3] => ram_block11a13.PORTAADDR3 +address_a[3] => ram_block11a14.PORTAADDR3 +address_a[3] => ram_block11a15.PORTAADDR3 +address_a[4] => ram_block11a0.PORTAADDR4 +address_a[4] => ram_block11a1.PORTAADDR4 +address_a[4] => ram_block11a2.PORTAADDR4 +address_a[4] => ram_block11a3.PORTAADDR4 +address_a[4] => ram_block11a4.PORTAADDR4 +address_a[4] => ram_block11a5.PORTAADDR4 +address_a[4] => ram_block11a6.PORTAADDR4 +address_a[4] => ram_block11a7.PORTAADDR4 +address_a[4] => ram_block11a8.PORTAADDR4 +address_a[4] => ram_block11a9.PORTAADDR4 +address_a[4] => ram_block11a10.PORTAADDR4 +address_a[4] => ram_block11a11.PORTAADDR4 +address_a[4] => ram_block11a12.PORTAADDR4 +address_a[4] => ram_block11a13.PORTAADDR4 +address_a[4] => ram_block11a14.PORTAADDR4 +address_a[4] => ram_block11a15.PORTAADDR4 +address_a[5] => ram_block11a0.PORTAADDR5 +address_a[5] => ram_block11a1.PORTAADDR5 +address_a[5] => ram_block11a2.PORTAADDR5 +address_a[5] => ram_block11a3.PORTAADDR5 +address_a[5] => ram_block11a4.PORTAADDR5 +address_a[5] => ram_block11a5.PORTAADDR5 +address_a[5] => ram_block11a6.PORTAADDR5 +address_a[5] => ram_block11a7.PORTAADDR5 +address_a[5] => ram_block11a8.PORTAADDR5 +address_a[5] => ram_block11a9.PORTAADDR5 +address_a[5] => ram_block11a10.PORTAADDR5 +address_a[5] => ram_block11a11.PORTAADDR5 +address_a[5] => ram_block11a12.PORTAADDR5 +address_a[5] => ram_block11a13.PORTAADDR5 +address_a[5] => ram_block11a14.PORTAADDR5 +address_a[5] => ram_block11a15.PORTAADDR5 +address_a[6] => ram_block11a0.PORTAADDR6 +address_a[6] => ram_block11a1.PORTAADDR6 +address_a[6] => ram_block11a2.PORTAADDR6 +address_a[6] => ram_block11a3.PORTAADDR6 +address_a[6] => ram_block11a4.PORTAADDR6 +address_a[6] => ram_block11a5.PORTAADDR6 +address_a[6] => ram_block11a6.PORTAADDR6 +address_a[6] => ram_block11a7.PORTAADDR6 +address_a[6] => ram_block11a8.PORTAADDR6 +address_a[6] => ram_block11a9.PORTAADDR6 +address_a[6] => ram_block11a10.PORTAADDR6 +address_a[6] => ram_block11a11.PORTAADDR6 +address_a[6] => ram_block11a12.PORTAADDR6 +address_a[6] => ram_block11a13.PORTAADDR6 +address_a[6] => ram_block11a14.PORTAADDR6 +address_a[6] => ram_block11a15.PORTAADDR6 +address_a[7] => ram_block11a0.PORTAADDR7 +address_a[7] => ram_block11a1.PORTAADDR7 +address_a[7] => ram_block11a2.PORTAADDR7 +address_a[7] => ram_block11a3.PORTAADDR7 +address_a[7] => ram_block11a4.PORTAADDR7 +address_a[7] => ram_block11a5.PORTAADDR7 +address_a[7] => ram_block11a6.PORTAADDR7 +address_a[7] => ram_block11a7.PORTAADDR7 +address_a[7] => ram_block11a8.PORTAADDR7 +address_a[7] => ram_block11a9.PORTAADDR7 +address_a[7] => ram_block11a10.PORTAADDR7 +address_a[7] => ram_block11a11.PORTAADDR7 +address_a[7] => ram_block11a12.PORTAADDR7 +address_a[7] => ram_block11a13.PORTAADDR7 +address_a[7] => ram_block11a14.PORTAADDR7 +address_a[7] => ram_block11a15.PORTAADDR7 +address_a[8] => ram_block11a0.PORTAADDR8 +address_a[8] => ram_block11a1.PORTAADDR8 +address_a[8] => ram_block11a2.PORTAADDR8 +address_a[8] => ram_block11a3.PORTAADDR8 +address_a[8] => ram_block11a4.PORTAADDR8 +address_a[8] => ram_block11a5.PORTAADDR8 +address_a[8] => ram_block11a6.PORTAADDR8 +address_a[8] => ram_block11a7.PORTAADDR8 +address_a[8] => ram_block11a8.PORTAADDR8 +address_a[8] => ram_block11a9.PORTAADDR8 +address_a[8] => ram_block11a10.PORTAADDR8 +address_a[8] => ram_block11a11.PORTAADDR8 +address_a[8] => ram_block11a12.PORTAADDR8 +address_a[8] => ram_block11a13.PORTAADDR8 +address_a[8] => ram_block11a14.PORTAADDR8 +address_a[8] => ram_block11a15.PORTAADDR8 +address_b[0] => ram_block11a0.PORTBADDR +address_b[0] => ram_block11a1.PORTBADDR +address_b[0] => ram_block11a2.PORTBADDR +address_b[0] => ram_block11a3.PORTBADDR +address_b[0] => ram_block11a4.PORTBADDR +address_b[0] => ram_block11a5.PORTBADDR +address_b[0] => ram_block11a6.PORTBADDR +address_b[0] => ram_block11a7.PORTBADDR +address_b[0] => ram_block11a8.PORTBADDR +address_b[0] => ram_block11a9.PORTBADDR +address_b[0] => ram_block11a10.PORTBADDR +address_b[0] => ram_block11a11.PORTBADDR +address_b[0] => ram_block11a12.PORTBADDR +address_b[0] => ram_block11a13.PORTBADDR +address_b[0] => ram_block11a14.PORTBADDR +address_b[0] => ram_block11a15.PORTBADDR +address_b[1] => ram_block11a0.PORTBADDR1 +address_b[1] => ram_block11a1.PORTBADDR1 +address_b[1] => ram_block11a2.PORTBADDR1 +address_b[1] => ram_block11a3.PORTBADDR1 +address_b[1] => ram_block11a4.PORTBADDR1 +address_b[1] => ram_block11a5.PORTBADDR1 +address_b[1] => ram_block11a6.PORTBADDR1 +address_b[1] => ram_block11a7.PORTBADDR1 +address_b[1] => ram_block11a8.PORTBADDR1 +address_b[1] => ram_block11a9.PORTBADDR1 +address_b[1] => ram_block11a10.PORTBADDR1 +address_b[1] => ram_block11a11.PORTBADDR1 +address_b[1] => ram_block11a12.PORTBADDR1 +address_b[1] => ram_block11a13.PORTBADDR1 +address_b[1] => ram_block11a14.PORTBADDR1 +address_b[1] => ram_block11a15.PORTBADDR1 +address_b[2] => ram_block11a0.PORTBADDR2 +address_b[2] => ram_block11a1.PORTBADDR2 +address_b[2] => ram_block11a2.PORTBADDR2 +address_b[2] => ram_block11a3.PORTBADDR2 +address_b[2] => ram_block11a4.PORTBADDR2 +address_b[2] => ram_block11a5.PORTBADDR2 +address_b[2] => ram_block11a6.PORTBADDR2 +address_b[2] => ram_block11a7.PORTBADDR2 +address_b[2] => ram_block11a8.PORTBADDR2 +address_b[2] => ram_block11a9.PORTBADDR2 +address_b[2] => ram_block11a10.PORTBADDR2 +address_b[2] => ram_block11a11.PORTBADDR2 +address_b[2] => ram_block11a12.PORTBADDR2 +address_b[2] => ram_block11a13.PORTBADDR2 +address_b[2] => ram_block11a14.PORTBADDR2 +address_b[2] => ram_block11a15.PORTBADDR2 +address_b[3] => ram_block11a0.PORTBADDR3 +address_b[3] => ram_block11a1.PORTBADDR3 +address_b[3] => ram_block11a2.PORTBADDR3 +address_b[3] => ram_block11a3.PORTBADDR3 +address_b[3] => ram_block11a4.PORTBADDR3 +address_b[3] => ram_block11a5.PORTBADDR3 +address_b[3] => ram_block11a6.PORTBADDR3 +address_b[3] => ram_block11a7.PORTBADDR3 +address_b[3] => ram_block11a8.PORTBADDR3 +address_b[3] => ram_block11a9.PORTBADDR3 +address_b[3] => ram_block11a10.PORTBADDR3 +address_b[3] => ram_block11a11.PORTBADDR3 +address_b[3] => ram_block11a12.PORTBADDR3 +address_b[3] => ram_block11a13.PORTBADDR3 +address_b[3] => ram_block11a14.PORTBADDR3 +address_b[3] => ram_block11a15.PORTBADDR3 +address_b[4] => ram_block11a0.PORTBADDR4 +address_b[4] => ram_block11a1.PORTBADDR4 +address_b[4] => ram_block11a2.PORTBADDR4 +address_b[4] => ram_block11a3.PORTBADDR4 +address_b[4] => ram_block11a4.PORTBADDR4 +address_b[4] => ram_block11a5.PORTBADDR4 +address_b[4] => ram_block11a6.PORTBADDR4 +address_b[4] => ram_block11a7.PORTBADDR4 +address_b[4] => ram_block11a8.PORTBADDR4 +address_b[4] => ram_block11a9.PORTBADDR4 +address_b[4] => ram_block11a10.PORTBADDR4 +address_b[4] => ram_block11a11.PORTBADDR4 +address_b[4] => ram_block11a12.PORTBADDR4 +address_b[4] => ram_block11a13.PORTBADDR4 +address_b[4] => ram_block11a14.PORTBADDR4 +address_b[4] => ram_block11a15.PORTBADDR4 +address_b[5] => ram_block11a0.PORTBADDR5 +address_b[5] => ram_block11a1.PORTBADDR5 +address_b[5] => ram_block11a2.PORTBADDR5 +address_b[5] => ram_block11a3.PORTBADDR5 +address_b[5] => ram_block11a4.PORTBADDR5 +address_b[5] => ram_block11a5.PORTBADDR5 +address_b[5] => ram_block11a6.PORTBADDR5 +address_b[5] => ram_block11a7.PORTBADDR5 +address_b[5] => ram_block11a8.PORTBADDR5 +address_b[5] => ram_block11a9.PORTBADDR5 +address_b[5] => ram_block11a10.PORTBADDR5 +address_b[5] => ram_block11a11.PORTBADDR5 +address_b[5] => ram_block11a12.PORTBADDR5 +address_b[5] => ram_block11a13.PORTBADDR5 +address_b[5] => ram_block11a14.PORTBADDR5 +address_b[5] => ram_block11a15.PORTBADDR5 +address_b[6] => ram_block11a0.PORTBADDR6 +address_b[6] => ram_block11a1.PORTBADDR6 +address_b[6] => ram_block11a2.PORTBADDR6 +address_b[6] => ram_block11a3.PORTBADDR6 +address_b[6] => ram_block11a4.PORTBADDR6 +address_b[6] => ram_block11a5.PORTBADDR6 +address_b[6] => ram_block11a6.PORTBADDR6 +address_b[6] => ram_block11a7.PORTBADDR6 +address_b[6] => ram_block11a8.PORTBADDR6 +address_b[6] => ram_block11a9.PORTBADDR6 +address_b[6] => ram_block11a10.PORTBADDR6 +address_b[6] => ram_block11a11.PORTBADDR6 +address_b[6] => ram_block11a12.PORTBADDR6 +address_b[6] => ram_block11a13.PORTBADDR6 +address_b[6] => ram_block11a14.PORTBADDR6 +address_b[6] => ram_block11a15.PORTBADDR6 +address_b[7] => ram_block11a0.PORTBADDR7 +address_b[7] => ram_block11a1.PORTBADDR7 +address_b[7] => ram_block11a2.PORTBADDR7 +address_b[7] => ram_block11a3.PORTBADDR7 +address_b[7] => ram_block11a4.PORTBADDR7 +address_b[7] => ram_block11a5.PORTBADDR7 +address_b[7] => ram_block11a6.PORTBADDR7 +address_b[7] => ram_block11a7.PORTBADDR7 +address_b[7] => ram_block11a8.PORTBADDR7 +address_b[7] => ram_block11a9.PORTBADDR7 +address_b[7] => ram_block11a10.PORTBADDR7 +address_b[7] => ram_block11a11.PORTBADDR7 +address_b[7] => ram_block11a12.PORTBADDR7 +address_b[7] => ram_block11a13.PORTBADDR7 +address_b[7] => ram_block11a14.PORTBADDR7 +address_b[7] => ram_block11a15.PORTBADDR7 +address_b[8] => ram_block11a0.PORTBADDR8 +address_b[8] => ram_block11a1.PORTBADDR8 +address_b[8] => ram_block11a2.PORTBADDR8 +address_b[8] => ram_block11a3.PORTBADDR8 +address_b[8] => ram_block11a4.PORTBADDR8 +address_b[8] => ram_block11a5.PORTBADDR8 +address_b[8] => ram_block11a6.PORTBADDR8 +address_b[8] => ram_block11a7.PORTBADDR8 +address_b[8] => ram_block11a8.PORTBADDR8 +address_b[8] => ram_block11a9.PORTBADDR8 +address_b[8] => ram_block11a10.PORTBADDR8 +address_b[8] => ram_block11a11.PORTBADDR8 +address_b[8] => ram_block11a12.PORTBADDR8 +address_b[8] => ram_block11a13.PORTBADDR8 +address_b[8] => ram_block11a14.PORTBADDR8 +address_b[8] => ram_block11a15.PORTBADDR8 +addressstall_b => ram_block11a0.PORTBADDRSTALL +addressstall_b => ram_block11a1.PORTBADDRSTALL +addressstall_b => ram_block11a2.PORTBADDRSTALL +addressstall_b => ram_block11a3.PORTBADDRSTALL +addressstall_b => ram_block11a4.PORTBADDRSTALL +addressstall_b => ram_block11a5.PORTBADDRSTALL +addressstall_b => ram_block11a6.PORTBADDRSTALL +addressstall_b => ram_block11a7.PORTBADDRSTALL +addressstall_b => ram_block11a8.PORTBADDRSTALL +addressstall_b => ram_block11a9.PORTBADDRSTALL +addressstall_b => ram_block11a10.PORTBADDRSTALL +addressstall_b => ram_block11a11.PORTBADDRSTALL +addressstall_b => ram_block11a12.PORTBADDRSTALL +addressstall_b => ram_block11a13.PORTBADDRSTALL +addressstall_b => ram_block11a14.PORTBADDRSTALL +addressstall_b => ram_block11a15.PORTBADDRSTALL +clock0 => ram_block11a0.CLK0 +clock0 => ram_block11a1.CLK0 +clock0 => ram_block11a2.CLK0 +clock0 => ram_block11a3.CLK0 +clock0 => ram_block11a4.CLK0 +clock0 => ram_block11a5.CLK0 +clock0 => ram_block11a6.CLK0 +clock0 => ram_block11a7.CLK0 +clock0 => ram_block11a8.CLK0 +clock0 => ram_block11a9.CLK0 +clock0 => ram_block11a10.CLK0 +clock0 => ram_block11a11.CLK0 +clock0 => ram_block11a12.CLK0 +clock0 => ram_block11a13.CLK0 +clock0 => ram_block11a14.CLK0 +clock0 => ram_block11a15.CLK0 +clock1 => ram_block11a0.CLK1 +clock1 => ram_block11a1.CLK1 +clock1 => ram_block11a2.CLK1 +clock1 => ram_block11a3.CLK1 +clock1 => ram_block11a4.CLK1 +clock1 => ram_block11a5.CLK1 +clock1 => ram_block11a6.CLK1 +clock1 => ram_block11a7.CLK1 +clock1 => ram_block11a8.CLK1 +clock1 => ram_block11a9.CLK1 +clock1 => ram_block11a10.CLK1 +clock1 => ram_block11a11.CLK1 +clock1 => ram_block11a12.CLK1 +clock1 => ram_block11a13.CLK1 +clock1 => ram_block11a14.CLK1 +clock1 => ram_block11a15.CLK1 +clocken1 => ram_block11a0.ENA1 +clocken1 => ram_block11a1.ENA1 +clocken1 => ram_block11a2.ENA1 +clocken1 => ram_block11a3.ENA1 +clocken1 => ram_block11a4.ENA1 +clocken1 => ram_block11a5.ENA1 +clocken1 => ram_block11a6.ENA1 +clocken1 => ram_block11a7.ENA1 +clocken1 => ram_block11a8.ENA1 +clocken1 => ram_block11a9.ENA1 +clocken1 => ram_block11a10.ENA1 +clocken1 => ram_block11a11.ENA1 +clocken1 => ram_block11a12.ENA1 +clocken1 => ram_block11a13.ENA1 +clocken1 => ram_block11a14.ENA1 +clocken1 => ram_block11a15.ENA1 +data_a[0] => ram_block11a0.PORTADATAIN +data_a[1] => ram_block11a1.PORTADATAIN +data_a[2] => ram_block11a2.PORTADATAIN +data_a[3] => ram_block11a3.PORTADATAIN +data_a[4] => ram_block11a4.PORTADATAIN +data_a[5] => ram_block11a5.PORTADATAIN +data_a[6] => ram_block11a6.PORTADATAIN +data_a[7] => ram_block11a7.PORTADATAIN +data_a[8] => ram_block11a8.PORTADATAIN +data_a[9] => ram_block11a9.PORTADATAIN +data_a[10] => ram_block11a10.PORTADATAIN +data_a[11] => ram_block11a11.PORTADATAIN +data_a[12] => ram_block11a12.PORTADATAIN +data_a[13] => ram_block11a13.PORTADATAIN +data_a[14] => ram_block11a14.PORTADATAIN +data_a[15] => ram_block11a15.PORTADATAIN +q_b[0] <= ram_block11a0.PORTBDATAOUT +q_b[1] <= ram_block11a1.PORTBDATAOUT +q_b[2] <= ram_block11a2.PORTBDATAOUT +q_b[3] <= ram_block11a3.PORTBDATAOUT +q_b[4] <= ram_block11a4.PORTBDATAOUT +q_b[5] <= ram_block11a5.PORTBDATAOUT +q_b[6] <= ram_block11a6.PORTBDATAOUT +q_b[7] <= ram_block11a7.PORTBDATAOUT +q_b[8] <= ram_block11a8.PORTBDATAOUT +q_b[9] <= ram_block11a9.PORTBDATAOUT +q_b[10] <= ram_block11a10.PORTBDATAOUT +q_b[11] <= ram_block11a11.PORTBDATAOUT +q_b[12] <= ram_block11a12.PORTBDATAOUT +q_b[13] <= ram_block11a13.PORTBDATAOUT +q_b[14] <= ram_block11a14.PORTBDATAOUT +q_b[15] <= ram_block11a15.PORTBDATAOUT +wren_a => ram_block11a0.PORTAWE +wren_a => ram_block11a0.ENA0 +wren_a => ram_block11a1.PORTAWE +wren_a => ram_block11a1.ENA0 +wren_a => ram_block11a2.PORTAWE +wren_a => ram_block11a2.ENA0 +wren_a => ram_block11a3.PORTAWE +wren_a => ram_block11a3.ENA0 +wren_a => ram_block11a4.PORTAWE +wren_a => ram_block11a4.ENA0 +wren_a => ram_block11a5.PORTAWE +wren_a => ram_block11a5.ENA0 +wren_a => ram_block11a6.PORTAWE +wren_a => ram_block11a6.ENA0 +wren_a => ram_block11a7.PORTAWE +wren_a => ram_block11a7.ENA0 +wren_a => ram_block11a8.PORTAWE +wren_a => ram_block11a8.ENA0 +wren_a => ram_block11a9.PORTAWE +wren_a => ram_block11a9.ENA0 +wren_a => ram_block11a10.PORTAWE +wren_a => ram_block11a10.ENA0 +wren_a => ram_block11a11.PORTAWE +wren_a => ram_block11a11.ENA0 +wren_a => ram_block11a12.PORTAWE +wren_a => ram_block11a12.ENA0 +wren_a => ram_block11a13.PORTAWE +wren_a => ram_block11a13.ENA0 +wren_a => ram_block11a14.PORTAWE +wren_a => ram_block11a14.ENA0 +wren_a => ram_block11a15.PORTAWE +wren_a => ram_block11a15.ENA0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp +clock => dffe12a[9].CLK +clock => dffe12a[8].CLK +clock => dffe12a[7].CLK +clock => dffe12a[6].CLK +clock => dffe12a[5].CLK +clock => dffe12a[4].CLK +clock => dffe12a[3].CLK +clock => dffe12a[2].CLK +clock => dffe12a[1].CLK +clock => dffe12a[0].CLK +clrn => dffe12a[9].ACLR +clrn => dffe12a[8].ACLR +clrn => dffe12a[7].ACLR +clrn => dffe12a[6].ACLR +clrn => dffe12a[5].ACLR +clrn => dffe12a[4].ACLR +clrn => dffe12a[3].ACLR +clrn => dffe12a[2].ACLR +clrn => dffe12a[1].ACLR +clrn => dffe12a[0].ACLR +d[0] => dffe12a[0].IN0 +d[1] => dffe12a[1].IN0 +d[2] => dffe12a[2].IN0 +d[3] => dffe12a[3].IN0 +d[4] => dffe12a[4].IN0 +d[5] => dffe12a[5].IN0 +d[6] => dffe12a[6].IN0 +d[7] => dffe12a[7].IN0 +d[8] => dffe12a[8].IN0 +d[9] => dffe12a[9].IN0 +q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp +clock => dffe12a[9].CLK +clock => dffe12a[8].CLK +clock => dffe12a[7].CLK +clock => dffe12a[6].CLK +clock => dffe12a[5].CLK +clock => dffe12a[4].CLK +clock => dffe12a[3].CLK +clock => dffe12a[2].CLK +clock => dffe12a[1].CLK +clock => dffe12a[0].CLK +clrn => dffe12a[9].ACLR +clrn => dffe12a[8].ACLR +clrn => dffe12a[7].ACLR +clrn => dffe12a[6].ACLR +clrn => dffe12a[5].ACLR +clrn => dffe12a[4].ACLR +clrn => dffe12a[3].ACLR +clrn => dffe12a[2].ACLR +clrn => dffe12a[1].ACLR +clrn => dffe12a[0].ACLR +d[0] => dffe12a[0].IN0 +d[1] => dffe12a[1].IN0 +d[2] => dffe12a[2].IN0 +d[3] => dffe12a[3].IN0 +d[4] => dffe12a[4].IN0 +d[5] => dffe12a[5].IN0 +d[6] => dffe12a[6].IN0 +d[7] => dffe12a[7].IN0 +d[8] => dffe12a[8].IN0 +d[9] => dffe12a[9].IN0 +q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp +clock => dffpipe_pe9:dffpipe13.clock +clrn => dffpipe_pe9:dffpipe13.clrn +d[0] => dffpipe_pe9:dffpipe13.d[0] +d[1] => dffpipe_pe9:dffpipe13.d[1] +d[2] => dffpipe_pe9:dffpipe13.d[2] +d[3] => dffpipe_pe9:dffpipe13.d[3] +d[4] => dffpipe_pe9:dffpipe13.d[4] +d[5] => dffpipe_pe9:dffpipe13.d[5] +d[6] => dffpipe_pe9:dffpipe13.d[6] +d[7] => dffpipe_pe9:dffpipe13.d[7] +d[8] => dffpipe_pe9:dffpipe13.d[8] +d[9] => dffpipe_pe9:dffpipe13.d[9] +q[0] <= dffpipe_pe9:dffpipe13.q[0] +q[1] <= dffpipe_pe9:dffpipe13.q[1] +q[2] <= dffpipe_pe9:dffpipe13.q[2] +q[3] <= dffpipe_pe9:dffpipe13.q[3] +q[4] <= dffpipe_pe9:dffpipe13.q[4] +q[5] <= dffpipe_pe9:dffpipe13.q[5] +q[6] <= dffpipe_pe9:dffpipe13.q[6] +q[7] <= dffpipe_pe9:dffpipe13.q[7] +q[8] <= dffpipe_pe9:dffpipe13.q[8] +q[9] <= dffpipe_pe9:dffpipe13.q[9] + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 +clock => dffe14a[9].CLK +clock => dffe14a[8].CLK +clock => dffe14a[7].CLK +clock => dffe14a[6].CLK +clock => dffe14a[5].CLK +clock => dffe14a[4].CLK +clock => dffe14a[3].CLK +clock => dffe14a[2].CLK +clock => dffe14a[1].CLK +clock => dffe14a[0].CLK +clock => dffe15a[9].CLK +clock => dffe15a[8].CLK +clock => dffe15a[7].CLK +clock => dffe15a[6].CLK +clock => dffe15a[5].CLK +clock => dffe15a[4].CLK +clock => dffe15a[3].CLK +clock => dffe15a[2].CLK +clock => dffe15a[1].CLK +clock => dffe15a[0].CLK +clrn => dffe14a[9].ACLR +clrn => dffe14a[8].ACLR +clrn => dffe14a[7].ACLR +clrn => dffe14a[6].ACLR +clrn => dffe14a[5].ACLR +clrn => dffe14a[4].ACLR +clrn => dffe14a[3].ACLR +clrn => dffe14a[2].ACLR +clrn => dffe14a[1].ACLR +clrn => dffe14a[0].ACLR +clrn => dffe15a[9].ACLR +clrn => dffe15a[8].ACLR +clrn => dffe15a[7].ACLR +clrn => dffe15a[6].ACLR +clrn => dffe15a[5].ACLR +clrn => dffe15a[4].ACLR +clrn => dffe15a[3].ACLR +clrn => dffe15a[2].ACLR +clrn => dffe15a[1].ACLR +clrn => dffe15a[0].ACLR +d[0] => dffe14a[0].IN0 +d[1] => dffe14a[1].IN0 +d[2] => dffe14a[2].IN0 +d[3] => dffe14a[3].IN0 +d[4] => dffe14a[4].IN0 +d[5] => dffe14a[5].IN0 +d[6] => dffe14a[6].IN0 +d[7] => dffe14a[7].IN0 +d[8] => dffe14a[8].IN0 +d[9] => dffe14a[9].IN0 +q[0] <= dffe15a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe15a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe15a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe15a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe15a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe15a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe15a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe15a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe15a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe15a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp +clock => dffe12a[9].CLK +clock => dffe12a[8].CLK +clock => dffe12a[7].CLK +clock => dffe12a[6].CLK +clock => dffe12a[5].CLK +clock => dffe12a[4].CLK +clock => dffe12a[3].CLK +clock => dffe12a[2].CLK +clock => dffe12a[1].CLK +clock => dffe12a[0].CLK +clrn => dffe12a[9].ACLR +clrn => dffe12a[8].ACLR +clrn => dffe12a[7].ACLR +clrn => dffe12a[6].ACLR +clrn => dffe12a[5].ACLR +clrn => dffe12a[4].ACLR +clrn => dffe12a[3].ACLR +clrn => dffe12a[2].ACLR +clrn => dffe12a[1].ACLR +clrn => dffe12a[0].ACLR +d[0] => dffe12a[0].IN0 +d[1] => dffe12a[1].IN0 +d[2] => dffe12a[2].IN0 +d[3] => dffe12a[3].IN0 +d[4] => dffe12a[4].IN0 +d[5] => dffe12a[5].IN0 +d[6] => dffe12a[6].IN0 +d[7] => dffe12a[7].IN0 +d[8] => dffe12a[8].IN0 +d[9] => dffe12a[9].IN0 +q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp +clock => dffe12a[9].CLK +clock => dffe12a[8].CLK +clock => dffe12a[7].CLK +clock => dffe12a[6].CLK +clock => dffe12a[5].CLK +clock => dffe12a[4].CLK +clock => dffe12a[3].CLK +clock => dffe12a[2].CLK +clock => dffe12a[1].CLK +clock => dffe12a[0].CLK +clrn => dffe12a[9].ACLR +clrn => dffe12a[8].ACLR +clrn => dffe12a[7].ACLR +clrn => dffe12a[6].ACLR +clrn => dffe12a[5].ACLR +clrn => dffe12a[4].ACLR +clrn => dffe12a[3].ACLR +clrn => dffe12a[2].ACLR +clrn => dffe12a[1].ACLR +clrn => dffe12a[0].ACLR +d[0] => dffe12a[0].IN0 +d[1] => dffe12a[1].IN0 +d[2] => dffe12a[2].IN0 +d[3] => dffe12a[3].IN0 +d[4] => dffe12a[4].IN0 +d[5] => dffe12a[5].IN0 +d[6] => dffe12a[6].IN0 +d[7] => dffe12a[7].IN0 +d[8] => dffe12a[8].IN0 +d[9] => dffe12a[9].IN0 +q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp +clock => dffpipe_qe9:dffpipe16.clock +clrn => dffpipe_qe9:dffpipe16.clrn +d[0] => dffpipe_qe9:dffpipe16.d[0] +d[1] => dffpipe_qe9:dffpipe16.d[1] +d[2] => dffpipe_qe9:dffpipe16.d[2] +d[3] => dffpipe_qe9:dffpipe16.d[3] +d[4] => dffpipe_qe9:dffpipe16.d[4] +d[5] => dffpipe_qe9:dffpipe16.d[5] +d[6] => dffpipe_qe9:dffpipe16.d[6] +d[7] => dffpipe_qe9:dffpipe16.d[7] +d[8] => dffpipe_qe9:dffpipe16.d[8] +d[9] => dffpipe_qe9:dffpipe16.d[9] +q[0] <= dffpipe_qe9:dffpipe16.q[0] +q[1] <= dffpipe_qe9:dffpipe16.q[1] +q[2] <= dffpipe_qe9:dffpipe16.q[2] +q[3] <= dffpipe_qe9:dffpipe16.q[3] +q[4] <= dffpipe_qe9:dffpipe16.q[4] +q[5] <= dffpipe_qe9:dffpipe16.q[5] +q[6] <= dffpipe_qe9:dffpipe16.q[6] +q[7] <= dffpipe_qe9:dffpipe16.q[7] +q[8] <= dffpipe_qe9:dffpipe16.q[8] +q[9] <= dffpipe_qe9:dffpipe16.q[9] + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 +clock => dffe17a[9].CLK +clock => dffe17a[8].CLK +clock => dffe17a[7].CLK +clock => dffe17a[6].CLK +clock => dffe17a[5].CLK +clock => dffe17a[4].CLK +clock => dffe17a[3].CLK +clock => dffe17a[2].CLK +clock => dffe17a[1].CLK +clock => dffe17a[0].CLK +clock => dffe18a[9].CLK +clock => dffe18a[8].CLK +clock => dffe18a[7].CLK +clock => dffe18a[6].CLK +clock => dffe18a[5].CLK +clock => dffe18a[4].CLK +clock => dffe18a[3].CLK +clock => dffe18a[2].CLK +clock => dffe18a[1].CLK +clock => dffe18a[0].CLK +clrn => dffe17a[9].ACLR +clrn => dffe17a[8].ACLR +clrn => dffe17a[7].ACLR +clrn => dffe17a[6].ACLR +clrn => dffe17a[5].ACLR +clrn => dffe17a[4].ACLR +clrn => dffe17a[3].ACLR +clrn => dffe17a[2].ACLR +clrn => dffe17a[1].ACLR +clrn => dffe17a[0].ACLR +clrn => dffe18a[9].ACLR +clrn => dffe18a[8].ACLR +clrn => dffe18a[7].ACLR +clrn => dffe18a[6].ACLR +clrn => dffe18a[5].ACLR +clrn => dffe18a[4].ACLR +clrn => dffe18a[3].ACLR +clrn => dffe18a[2].ACLR +clrn => dffe18a[1].ACLR +clrn => dffe18a[0].ACLR +d[0] => dffe17a[0].IN0 +d[1] => dffe17a[1].IN0 +d[2] => dffe17a[2].IN0 +d[3] => dffe17a[3].IN0 +d[4] => dffe17a[4].IN0 +d[5] => dffe17a[5].IN0 +d[6] => dffe17a[6].IN0 +d[7] => dffe17a[7].IN0 +d[8] => dffe17a[8].IN0 +d[9] => dffe17a[9].IN0 +q[0] <= dffe18a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe18a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe18a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe18a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe18a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe18a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe18a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe18a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe18a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe18a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp +aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE +dataa[0] => data_wire[2].IN0 +dataa[1] => data_wire[2].IN0 +dataa[2] => data_wire[3].IN0 +dataa[3] => data_wire[3].IN0 +dataa[4] => data_wire[4].IN0 +dataa[5] => data_wire[4].IN0 +dataa[6] => data_wire[5].IN0 +dataa[7] => data_wire[5].IN0 +dataa[8] => data_wire[6].IN0 +dataa[9] => data_wire[6].IN0 +datab[0] => data_wire[2].IN1 +datab[1] => data_wire[2].IN1 +datab[2] => data_wire[3].IN1 +datab[3] => data_wire[3].IN1 +datab[4] => data_wire[4].IN1 +datab[5] => data_wire[4].IN1 +datab[6] => data_wire[5].IN1 +datab[7] => data_wire[5].IN1 +datab[8] => data_wire[6].IN1 +datab[9] => data_wire[6].IN1 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp +aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE +dataa[0] => data_wire[2].IN0 +dataa[1] => data_wire[2].IN0 +dataa[2] => data_wire[3].IN0 +dataa[3] => data_wire[3].IN0 +dataa[4] => data_wire[4].IN0 +dataa[5] => data_wire[4].IN0 +dataa[6] => data_wire[5].IN0 +dataa[7] => data_wire[5].IN0 +dataa[8] => data_wire[6].IN0 +dataa[9] => data_wire[6].IN0 +datab[0] => data_wire[2].IN1 +datab[1] => data_wire[2].IN1 +datab[2] => data_wire[3].IN1 +datab[3] => data_wire[3].IN1 +datab[4] => data_wire[4].IN1 +datab[5] => data_wire[4].IN1 +datab[6] => data_wire[5].IN1 +datab[7] => data_wire[5].IN1 +datab[8] => data_wire[6].IN1 +datab[9] => data_wire[6].IN1 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2 +aclr => aclr.IN1 +data[0] => data[0].IN1 +data[1] => data[1].IN1 +data[2] => data[2].IN1 +data[3] => data[3].IN1 +data[4] => data[4].IN1 +data[5] => data[5].IN1 +data[6] => data[6].IN1 +data[7] => data[7].IN1 +data[8] => data[8].IN1 +data[9] => data[9].IN1 +data[10] => data[10].IN1 +data[11] => data[11].IN1 +data[12] => data[12].IN1 +data[13] => data[13].IN1 +data[14] => data[14].IN1 +data[15] => data[15].IN1 +rdclk => rdclk.IN1 +rdreq => rdreq.IN1 +wrclk => wrclk.IN1 +wrreq => wrreq.IN1 +q[0] <= dcfifo:dcfifo_component.q +q[1] <= dcfifo:dcfifo_component.q +q[2] <= dcfifo:dcfifo_component.q +q[3] <= dcfifo:dcfifo_component.q +q[4] <= dcfifo:dcfifo_component.q +q[5] <= dcfifo:dcfifo_component.q +q[6] <= dcfifo:dcfifo_component.q +q[7] <= dcfifo:dcfifo_component.q +q[8] <= dcfifo:dcfifo_component.q +q[9] <= dcfifo:dcfifo_component.q +q[10] <= dcfifo:dcfifo_component.q +q[11] <= dcfifo:dcfifo_component.q +q[12] <= dcfifo:dcfifo_component.q +q[13] <= dcfifo:dcfifo_component.q +q[14] <= dcfifo:dcfifo_component.q +q[15] <= dcfifo:dcfifo_component.q +rdempty <= dcfifo:dcfifo_component.rdempty +rdusedw[0] <= dcfifo:dcfifo_component.rdusedw +rdusedw[1] <= dcfifo:dcfifo_component.rdusedw +rdusedw[2] <= dcfifo:dcfifo_component.rdusedw +rdusedw[3] <= dcfifo:dcfifo_component.rdusedw +rdusedw[4] <= dcfifo:dcfifo_component.rdusedw +rdusedw[5] <= dcfifo:dcfifo_component.rdusedw +rdusedw[6] <= dcfifo:dcfifo_component.rdusedw +rdusedw[7] <= dcfifo:dcfifo_component.rdusedw +rdusedw[8] <= dcfifo:dcfifo_component.rdusedw +wrfull <= dcfifo:dcfifo_component.wrfull +wrusedw[0] <= dcfifo:dcfifo_component.wrusedw +wrusedw[1] <= dcfifo:dcfifo_component.wrusedw +wrusedw[2] <= dcfifo:dcfifo_component.wrusedw +wrusedw[3] <= dcfifo:dcfifo_component.wrusedw +wrusedw[4] <= dcfifo:dcfifo_component.wrusedw +wrusedw[5] <= dcfifo:dcfifo_component.wrusedw +wrusedw[6] <= dcfifo:dcfifo_component.wrusedw +wrusedw[7] <= dcfifo:dcfifo_component.wrusedw +wrusedw[8] <= dcfifo:dcfifo_component.wrusedw + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component +data[0] => dcfifo_v5o1:auto_generated.data[0] +data[1] => dcfifo_v5o1:auto_generated.data[1] +data[2] => dcfifo_v5o1:auto_generated.data[2] +data[3] => dcfifo_v5o1:auto_generated.data[3] +data[4] => dcfifo_v5o1:auto_generated.data[4] +data[5] => dcfifo_v5o1:auto_generated.data[5] +data[6] => dcfifo_v5o1:auto_generated.data[6] +data[7] => dcfifo_v5o1:auto_generated.data[7] +data[8] => dcfifo_v5o1:auto_generated.data[8] +data[9] => dcfifo_v5o1:auto_generated.data[9] +data[10] => dcfifo_v5o1:auto_generated.data[10] +data[11] => dcfifo_v5o1:auto_generated.data[11] +data[12] => dcfifo_v5o1:auto_generated.data[12] +data[13] => dcfifo_v5o1:auto_generated.data[13] +data[14] => dcfifo_v5o1:auto_generated.data[14] +data[15] => dcfifo_v5o1:auto_generated.data[15] +q[0] <= dcfifo_v5o1:auto_generated.q[0] +q[1] <= dcfifo_v5o1:auto_generated.q[1] +q[2] <= dcfifo_v5o1:auto_generated.q[2] +q[3] <= dcfifo_v5o1:auto_generated.q[3] +q[4] <= dcfifo_v5o1:auto_generated.q[4] +q[5] <= dcfifo_v5o1:auto_generated.q[5] +q[6] <= dcfifo_v5o1:auto_generated.q[6] +q[7] <= dcfifo_v5o1:auto_generated.q[7] +q[8] <= dcfifo_v5o1:auto_generated.q[8] +q[9] <= dcfifo_v5o1:auto_generated.q[9] +q[10] <= dcfifo_v5o1:auto_generated.q[10] +q[11] <= dcfifo_v5o1:auto_generated.q[11] +q[12] <= dcfifo_v5o1:auto_generated.q[12] +q[13] <= dcfifo_v5o1:auto_generated.q[13] +q[14] <= dcfifo_v5o1:auto_generated.q[14] +q[15] <= dcfifo_v5o1:auto_generated.q[15] +rdclk => dcfifo_v5o1:auto_generated.rdclk +rdreq => dcfifo_v5o1:auto_generated.rdreq +wrclk => dcfifo_v5o1:auto_generated.wrclk +wrreq => dcfifo_v5o1:auto_generated.wrreq +aclr => dcfifo_v5o1:auto_generated.aclr +rdempty <= dcfifo_v5o1:auto_generated.rdempty +rdfull <= <UNC> +wrempty <= <GND> +wrfull <= dcfifo_v5o1:auto_generated.wrfull +rdusedw[0] <= dcfifo_v5o1:auto_generated.rdusedw[0] +rdusedw[1] <= dcfifo_v5o1:auto_generated.rdusedw[1] +rdusedw[2] <= dcfifo_v5o1:auto_generated.rdusedw[2] +rdusedw[3] <= dcfifo_v5o1:auto_generated.rdusedw[3] +rdusedw[4] <= dcfifo_v5o1:auto_generated.rdusedw[4] +rdusedw[5] <= dcfifo_v5o1:auto_generated.rdusedw[5] +rdusedw[6] <= dcfifo_v5o1:auto_generated.rdusedw[6] +rdusedw[7] <= dcfifo_v5o1:auto_generated.rdusedw[7] +rdusedw[8] <= dcfifo_v5o1:auto_generated.rdusedw[8] +wrusedw[0] <= dcfifo_v5o1:auto_generated.wrusedw[0] +wrusedw[1] <= dcfifo_v5o1:auto_generated.wrusedw[1] +wrusedw[2] <= dcfifo_v5o1:auto_generated.wrusedw[2] +wrusedw[3] <= dcfifo_v5o1:auto_generated.wrusedw[3] +wrusedw[4] <= dcfifo_v5o1:auto_generated.wrusedw[4] +wrusedw[5] <= dcfifo_v5o1:auto_generated.wrusedw[5] +wrusedw[6] <= dcfifo_v5o1:auto_generated.wrusedw[6] +wrusedw[7] <= dcfifo_v5o1:auto_generated.wrusedw[7] +wrusedw[8] <= dcfifo_v5o1:auto_generated.wrusedw[8] + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated +aclr => a_graycounter_s57:rdptr_g1p.aclr +aclr => a_graycounter_ojc:wrptr_g1p.aclr +aclr => altsyncram_de51:fifo_ram.aclr1 +aclr => delayed_wrptr_g[9].IN0 +aclr => rdptr_g[9].IN0 +aclr => wrptr_g[9].IN0 +aclr => _.IN0 +aclr => _.IN0 +aclr => _.IN0 +aclr => _.IN0 +aclr => _.IN0 +aclr => _.IN0 +data[0] => altsyncram_de51:fifo_ram.data_a[0] +data[1] => altsyncram_de51:fifo_ram.data_a[1] +data[2] => altsyncram_de51:fifo_ram.data_a[2] +data[3] => altsyncram_de51:fifo_ram.data_a[3] +data[4] => altsyncram_de51:fifo_ram.data_a[4] +data[5] => altsyncram_de51:fifo_ram.data_a[5] +data[6] => altsyncram_de51:fifo_ram.data_a[6] +data[7] => altsyncram_de51:fifo_ram.data_a[7] +data[8] => altsyncram_de51:fifo_ram.data_a[8] +data[9] => altsyncram_de51:fifo_ram.data_a[9] +data[10] => altsyncram_de51:fifo_ram.data_a[10] +data[11] => altsyncram_de51:fifo_ram.data_a[11] +data[12] => altsyncram_de51:fifo_ram.data_a[12] +data[13] => altsyncram_de51:fifo_ram.data_a[13] +data[14] => altsyncram_de51:fifo_ram.data_a[14] +data[15] => altsyncram_de51:fifo_ram.data_a[15] +q[0] <= altsyncram_de51:fifo_ram.q_b[0] +q[1] <= altsyncram_de51:fifo_ram.q_b[1] +q[2] <= altsyncram_de51:fifo_ram.q_b[2] +q[3] <= altsyncram_de51:fifo_ram.q_b[3] +q[4] <= altsyncram_de51:fifo_ram.q_b[4] +q[5] <= altsyncram_de51:fifo_ram.q_b[5] +q[6] <= altsyncram_de51:fifo_ram.q_b[6] +q[7] <= altsyncram_de51:fifo_ram.q_b[7] +q[8] <= altsyncram_de51:fifo_ram.q_b[8] +q[9] <= altsyncram_de51:fifo_ram.q_b[9] +q[10] <= altsyncram_de51:fifo_ram.q_b[10] +q[11] <= altsyncram_de51:fifo_ram.q_b[11] +q[12] <= altsyncram_de51:fifo_ram.q_b[12] +q[13] <= altsyncram_de51:fifo_ram.q_b[13] +q[14] <= altsyncram_de51:fifo_ram.q_b[14] +q[15] <= altsyncram_de51:fifo_ram.q_b[15] +rdclk => a_graycounter_s57:rdptr_g1p.clock +rdclk => altsyncram_de51:fifo_ram.clock1 +rdclk => dffpipe_oe9:rs_brp.clock +rdclk => dffpipe_oe9:rs_bwp.clock +rdclk => alt_synch_pipe_qld:rs_dgwp.clock +rdclk => rdptr_g[9].CLK +rdclk => rdptr_g[8].CLK +rdclk => rdptr_g[7].CLK +rdclk => rdptr_g[6].CLK +rdclk => rdptr_g[5].CLK +rdclk => rdptr_g[4].CLK +rdclk => rdptr_g[3].CLK +rdclk => rdptr_g[2].CLK +rdclk => rdptr_g[1].CLK +rdclk => rdptr_g[0].CLK +rdempty <= int_rdempty.DB_MAX_OUTPUT_PORT_TYPE +rdreq => valid_rdreq.IN0 +rdusedw[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +wrclk => a_graycounter_ojc:wrptr_g1p.clock +wrclk => altsyncram_de51:fifo_ram.clock0 +wrclk => dffpipe_oe9:ws_brp.clock +wrclk => dffpipe_oe9:ws_bwp.clock +wrclk => alt_synch_pipe_rld:ws_dgrp.clock +wrclk => delayed_wrptr_g[9].CLK +wrclk => delayed_wrptr_g[8].CLK +wrclk => delayed_wrptr_g[7].CLK +wrclk => delayed_wrptr_g[6].CLK +wrclk => delayed_wrptr_g[5].CLK +wrclk => delayed_wrptr_g[4].CLK +wrclk => delayed_wrptr_g[3].CLK +wrclk => delayed_wrptr_g[2].CLK +wrclk => delayed_wrptr_g[1].CLK +wrclk => delayed_wrptr_g[0].CLK +wrclk => wrptr_g[9].CLK +wrclk => wrptr_g[8].CLK +wrclk => wrptr_g[7].CLK +wrclk => wrptr_g[6].CLK +wrclk => wrptr_g[5].CLK +wrclk => wrptr_g[4].CLK +wrclk => wrptr_g[3].CLK +wrclk => wrptr_g[2].CLK +wrclk => wrptr_g[1].CLK +wrclk => wrptr_g[0].CLK +wrfull <= int_wrfull.DB_MAX_OUTPUT_PORT_TYPE +wrreq => valid_wrreq.IN0 +wrusedw[0] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[1] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[2] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[3] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[4] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[5] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[6] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[7] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[8] <= op_2.DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin +bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE +bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE +bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE +bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE +bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE +bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE +bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE +bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE +bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE +bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE +gray[0] => xor0.IN0 +gray[1] => xor1.IN0 +gray[2] => xor2.IN0 +gray[3] => xor3.IN0 +gray[4] => xor4.IN0 +gray[5] => xor5.IN0 +gray[6] => xor6.IN0 +gray[7] => xor7.IN0 +gray[8] => xor8.IN1 +gray[9] => bin[9].DATAIN +gray[9] => xor8.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin +bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE +bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE +bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE +bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE +bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE +bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE +bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE +bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE +bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE +bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE +gray[0] => xor0.IN0 +gray[1] => xor1.IN0 +gray[2] => xor2.IN0 +gray[3] => xor3.IN0 +gray[4] => xor4.IN0 +gray[5] => xor5.IN0 +gray[6] => xor6.IN0 +gray[7] => xor7.IN0 +gray[8] => xor8.IN1 +gray[9] => bin[9].DATAIN +gray[9] => xor8.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin +bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE +bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE +bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE +bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE +bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE +bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE +bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE +bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE +bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE +bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE +gray[0] => xor0.IN0 +gray[1] => xor1.IN0 +gray[2] => xor2.IN0 +gray[3] => xor3.IN0 +gray[4] => xor4.IN0 +gray[5] => xor5.IN0 +gray[6] => xor6.IN0 +gray[7] => xor7.IN0 +gray[8] => xor8.IN1 +gray[9] => bin[9].DATAIN +gray[9] => xor8.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin +bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE +bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE +bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE +bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE +bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE +bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE +bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE +bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE +bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE +bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE +gray[0] => xor0.IN0 +gray[1] => xor1.IN0 +gray[2] => xor2.IN0 +gray[3] => xor3.IN0 +gray[4] => xor4.IN0 +gray[5] => xor5.IN0 +gray[6] => xor6.IN0 +gray[7] => xor7.IN0 +gray[8] => xor8.IN1 +gray[9] => bin[9].DATAIN +gray[9] => xor8.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p +aclr => counter5a1.IN0 +aclr => counter5a0.IN0 +aclr => parity6.IN0 +aclr => sub_parity7a[2].IN0 +aclr => sub_parity7a[1].IN0 +aclr => sub_parity7a[0].IN0 +clock => counter5a0.CLK +clock => counter5a1.CLK +clock => counter5a2.CLK +clock => counter5a3.CLK +clock => counter5a4.CLK +clock => counter5a5.CLK +clock => counter5a6.CLK +clock => counter5a7.CLK +clock => counter5a8.CLK +clock => counter5a9.CLK +clock => parity6.CLK +clock => sub_parity7a[2].CLK +clock => sub_parity7a[1].CLK +clock => sub_parity7a[0].CLK +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => cntr_cout[0].IN0 +cnt_en => parity_cout.IN1 +q[0] <= counter5a0.DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter5a1.DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter5a2.DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter5a3.DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter5a4.DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter5a5.DB_MAX_OUTPUT_PORT_TYPE +q[6] <= counter5a6.DB_MAX_OUTPUT_PORT_TYPE +q[7] <= counter5a7.DB_MAX_OUTPUT_PORT_TYPE +q[8] <= counter5a8.DB_MAX_OUTPUT_PORT_TYPE +q[9] <= counter5a9.DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p +aclr => counter8a1.IN0 +aclr => counter8a0.IN0 +aclr => parity9.IN0 +aclr => sub_parity10a[2].IN0 +aclr => sub_parity10a[1].IN0 +aclr => sub_parity10a[0].IN0 +clock => counter8a0.CLK +clock => counter8a1.CLK +clock => counter8a2.CLK +clock => counter8a3.CLK +clock => counter8a4.CLK +clock => counter8a5.CLK +clock => counter8a6.CLK +clock => counter8a7.CLK +clock => counter8a8.CLK +clock => counter8a9.CLK +clock => parity9.CLK +clock => sub_parity10a[2].CLK +clock => sub_parity10a[1].CLK +clock => sub_parity10a[0].CLK +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => cntr_cout[0].IN0 +cnt_en => parity_cout.IN1 +q[0] <= counter8a0.DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter8a1.DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter8a2.DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter8a3.DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter8a4.DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter8a5.DB_MAX_OUTPUT_PORT_TYPE +q[6] <= counter8a6.DB_MAX_OUTPUT_PORT_TYPE +q[7] <= counter8a7.DB_MAX_OUTPUT_PORT_TYPE +q[8] <= counter8a8.DB_MAX_OUTPUT_PORT_TYPE +q[9] <= counter8a9.DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram +aclr1 => ram_block11a0.CLR1 +aclr1 => ram_block11a1.CLR1 +aclr1 => ram_block11a2.CLR1 +aclr1 => ram_block11a3.CLR1 +aclr1 => ram_block11a4.CLR1 +aclr1 => ram_block11a5.CLR1 +aclr1 => ram_block11a6.CLR1 +aclr1 => ram_block11a7.CLR1 +aclr1 => ram_block11a8.CLR1 +aclr1 => ram_block11a9.CLR1 +aclr1 => ram_block11a10.CLR1 +aclr1 => ram_block11a11.CLR1 +aclr1 => ram_block11a12.CLR1 +aclr1 => ram_block11a13.CLR1 +aclr1 => ram_block11a14.CLR1 +aclr1 => ram_block11a15.CLR1 +address_a[0] => ram_block11a0.PORTAADDR +address_a[0] => ram_block11a1.PORTAADDR +address_a[0] => ram_block11a2.PORTAADDR +address_a[0] => ram_block11a3.PORTAADDR +address_a[0] => ram_block11a4.PORTAADDR +address_a[0] => ram_block11a5.PORTAADDR +address_a[0] => ram_block11a6.PORTAADDR +address_a[0] => ram_block11a7.PORTAADDR +address_a[0] => ram_block11a8.PORTAADDR +address_a[0] => ram_block11a9.PORTAADDR +address_a[0] => ram_block11a10.PORTAADDR +address_a[0] => ram_block11a11.PORTAADDR +address_a[0] => ram_block11a12.PORTAADDR +address_a[0] => ram_block11a13.PORTAADDR +address_a[0] => ram_block11a14.PORTAADDR +address_a[0] => ram_block11a15.PORTAADDR +address_a[1] => ram_block11a0.PORTAADDR1 +address_a[1] => ram_block11a1.PORTAADDR1 +address_a[1] => ram_block11a2.PORTAADDR1 +address_a[1] => ram_block11a3.PORTAADDR1 +address_a[1] => ram_block11a4.PORTAADDR1 +address_a[1] => ram_block11a5.PORTAADDR1 +address_a[1] => ram_block11a6.PORTAADDR1 +address_a[1] => ram_block11a7.PORTAADDR1 +address_a[1] => ram_block11a8.PORTAADDR1 +address_a[1] => ram_block11a9.PORTAADDR1 +address_a[1] => ram_block11a10.PORTAADDR1 +address_a[1] => ram_block11a11.PORTAADDR1 +address_a[1] => ram_block11a12.PORTAADDR1 +address_a[1] => ram_block11a13.PORTAADDR1 +address_a[1] => ram_block11a14.PORTAADDR1 +address_a[1] => ram_block11a15.PORTAADDR1 +address_a[2] => ram_block11a0.PORTAADDR2 +address_a[2] => ram_block11a1.PORTAADDR2 +address_a[2] => ram_block11a2.PORTAADDR2 +address_a[2] => ram_block11a3.PORTAADDR2 +address_a[2] => ram_block11a4.PORTAADDR2 +address_a[2] => ram_block11a5.PORTAADDR2 +address_a[2] => ram_block11a6.PORTAADDR2 +address_a[2] => ram_block11a7.PORTAADDR2 +address_a[2] => ram_block11a8.PORTAADDR2 +address_a[2] => ram_block11a9.PORTAADDR2 +address_a[2] => ram_block11a10.PORTAADDR2 +address_a[2] => ram_block11a11.PORTAADDR2 +address_a[2] => ram_block11a12.PORTAADDR2 +address_a[2] => ram_block11a13.PORTAADDR2 +address_a[2] => ram_block11a14.PORTAADDR2 +address_a[2] => ram_block11a15.PORTAADDR2 +address_a[3] => ram_block11a0.PORTAADDR3 +address_a[3] => ram_block11a1.PORTAADDR3 +address_a[3] => ram_block11a2.PORTAADDR3 +address_a[3] => ram_block11a3.PORTAADDR3 +address_a[3] => ram_block11a4.PORTAADDR3 +address_a[3] => ram_block11a5.PORTAADDR3 +address_a[3] => ram_block11a6.PORTAADDR3 +address_a[3] => ram_block11a7.PORTAADDR3 +address_a[3] => ram_block11a8.PORTAADDR3 +address_a[3] => ram_block11a9.PORTAADDR3 +address_a[3] => ram_block11a10.PORTAADDR3 +address_a[3] => ram_block11a11.PORTAADDR3 +address_a[3] => ram_block11a12.PORTAADDR3 +address_a[3] => ram_block11a13.PORTAADDR3 +address_a[3] => ram_block11a14.PORTAADDR3 +address_a[3] => ram_block11a15.PORTAADDR3 +address_a[4] => ram_block11a0.PORTAADDR4 +address_a[4] => ram_block11a1.PORTAADDR4 +address_a[4] => ram_block11a2.PORTAADDR4 +address_a[4] => ram_block11a3.PORTAADDR4 +address_a[4] => ram_block11a4.PORTAADDR4 +address_a[4] => ram_block11a5.PORTAADDR4 +address_a[4] => ram_block11a6.PORTAADDR4 +address_a[4] => ram_block11a7.PORTAADDR4 +address_a[4] => ram_block11a8.PORTAADDR4 +address_a[4] => ram_block11a9.PORTAADDR4 +address_a[4] => ram_block11a10.PORTAADDR4 +address_a[4] => ram_block11a11.PORTAADDR4 +address_a[4] => ram_block11a12.PORTAADDR4 +address_a[4] => ram_block11a13.PORTAADDR4 +address_a[4] => ram_block11a14.PORTAADDR4 +address_a[4] => ram_block11a15.PORTAADDR4 +address_a[5] => ram_block11a0.PORTAADDR5 +address_a[5] => ram_block11a1.PORTAADDR5 +address_a[5] => ram_block11a2.PORTAADDR5 +address_a[5] => ram_block11a3.PORTAADDR5 +address_a[5] => ram_block11a4.PORTAADDR5 +address_a[5] => ram_block11a5.PORTAADDR5 +address_a[5] => ram_block11a6.PORTAADDR5 +address_a[5] => ram_block11a7.PORTAADDR5 +address_a[5] => ram_block11a8.PORTAADDR5 +address_a[5] => ram_block11a9.PORTAADDR5 +address_a[5] => ram_block11a10.PORTAADDR5 +address_a[5] => ram_block11a11.PORTAADDR5 +address_a[5] => ram_block11a12.PORTAADDR5 +address_a[5] => ram_block11a13.PORTAADDR5 +address_a[5] => ram_block11a14.PORTAADDR5 +address_a[5] => ram_block11a15.PORTAADDR5 +address_a[6] => ram_block11a0.PORTAADDR6 +address_a[6] => ram_block11a1.PORTAADDR6 +address_a[6] => ram_block11a2.PORTAADDR6 +address_a[6] => ram_block11a3.PORTAADDR6 +address_a[6] => ram_block11a4.PORTAADDR6 +address_a[6] => ram_block11a5.PORTAADDR6 +address_a[6] => ram_block11a6.PORTAADDR6 +address_a[6] => ram_block11a7.PORTAADDR6 +address_a[6] => ram_block11a8.PORTAADDR6 +address_a[6] => ram_block11a9.PORTAADDR6 +address_a[6] => ram_block11a10.PORTAADDR6 +address_a[6] => ram_block11a11.PORTAADDR6 +address_a[6] => ram_block11a12.PORTAADDR6 +address_a[6] => ram_block11a13.PORTAADDR6 +address_a[6] => ram_block11a14.PORTAADDR6 +address_a[6] => ram_block11a15.PORTAADDR6 +address_a[7] => ram_block11a0.PORTAADDR7 +address_a[7] => ram_block11a1.PORTAADDR7 +address_a[7] => ram_block11a2.PORTAADDR7 +address_a[7] => ram_block11a3.PORTAADDR7 +address_a[7] => ram_block11a4.PORTAADDR7 +address_a[7] => ram_block11a5.PORTAADDR7 +address_a[7] => ram_block11a6.PORTAADDR7 +address_a[7] => ram_block11a7.PORTAADDR7 +address_a[7] => ram_block11a8.PORTAADDR7 +address_a[7] => ram_block11a9.PORTAADDR7 +address_a[7] => ram_block11a10.PORTAADDR7 +address_a[7] => ram_block11a11.PORTAADDR7 +address_a[7] => ram_block11a12.PORTAADDR7 +address_a[7] => ram_block11a13.PORTAADDR7 +address_a[7] => ram_block11a14.PORTAADDR7 +address_a[7] => ram_block11a15.PORTAADDR7 +address_a[8] => ram_block11a0.PORTAADDR8 +address_a[8] => ram_block11a1.PORTAADDR8 +address_a[8] => ram_block11a2.PORTAADDR8 +address_a[8] => ram_block11a3.PORTAADDR8 +address_a[8] => ram_block11a4.PORTAADDR8 +address_a[8] => ram_block11a5.PORTAADDR8 +address_a[8] => ram_block11a6.PORTAADDR8 +address_a[8] => ram_block11a7.PORTAADDR8 +address_a[8] => ram_block11a8.PORTAADDR8 +address_a[8] => ram_block11a9.PORTAADDR8 +address_a[8] => ram_block11a10.PORTAADDR8 +address_a[8] => ram_block11a11.PORTAADDR8 +address_a[8] => ram_block11a12.PORTAADDR8 +address_a[8] => ram_block11a13.PORTAADDR8 +address_a[8] => ram_block11a14.PORTAADDR8 +address_a[8] => ram_block11a15.PORTAADDR8 +address_b[0] => ram_block11a0.PORTBADDR +address_b[0] => ram_block11a1.PORTBADDR +address_b[0] => ram_block11a2.PORTBADDR +address_b[0] => ram_block11a3.PORTBADDR +address_b[0] => ram_block11a4.PORTBADDR +address_b[0] => ram_block11a5.PORTBADDR +address_b[0] => ram_block11a6.PORTBADDR +address_b[0] => ram_block11a7.PORTBADDR +address_b[0] => ram_block11a8.PORTBADDR +address_b[0] => ram_block11a9.PORTBADDR +address_b[0] => ram_block11a10.PORTBADDR +address_b[0] => ram_block11a11.PORTBADDR +address_b[0] => ram_block11a12.PORTBADDR +address_b[0] => ram_block11a13.PORTBADDR +address_b[0] => ram_block11a14.PORTBADDR +address_b[0] => ram_block11a15.PORTBADDR +address_b[1] => ram_block11a0.PORTBADDR1 +address_b[1] => ram_block11a1.PORTBADDR1 +address_b[1] => ram_block11a2.PORTBADDR1 +address_b[1] => ram_block11a3.PORTBADDR1 +address_b[1] => ram_block11a4.PORTBADDR1 +address_b[1] => ram_block11a5.PORTBADDR1 +address_b[1] => ram_block11a6.PORTBADDR1 +address_b[1] => ram_block11a7.PORTBADDR1 +address_b[1] => ram_block11a8.PORTBADDR1 +address_b[1] => ram_block11a9.PORTBADDR1 +address_b[1] => ram_block11a10.PORTBADDR1 +address_b[1] => ram_block11a11.PORTBADDR1 +address_b[1] => ram_block11a12.PORTBADDR1 +address_b[1] => ram_block11a13.PORTBADDR1 +address_b[1] => ram_block11a14.PORTBADDR1 +address_b[1] => ram_block11a15.PORTBADDR1 +address_b[2] => ram_block11a0.PORTBADDR2 +address_b[2] => ram_block11a1.PORTBADDR2 +address_b[2] => ram_block11a2.PORTBADDR2 +address_b[2] => ram_block11a3.PORTBADDR2 +address_b[2] => ram_block11a4.PORTBADDR2 +address_b[2] => ram_block11a5.PORTBADDR2 +address_b[2] => ram_block11a6.PORTBADDR2 +address_b[2] => ram_block11a7.PORTBADDR2 +address_b[2] => ram_block11a8.PORTBADDR2 +address_b[2] => ram_block11a9.PORTBADDR2 +address_b[2] => ram_block11a10.PORTBADDR2 +address_b[2] => ram_block11a11.PORTBADDR2 +address_b[2] => ram_block11a12.PORTBADDR2 +address_b[2] => ram_block11a13.PORTBADDR2 +address_b[2] => ram_block11a14.PORTBADDR2 +address_b[2] => ram_block11a15.PORTBADDR2 +address_b[3] => ram_block11a0.PORTBADDR3 +address_b[3] => ram_block11a1.PORTBADDR3 +address_b[3] => ram_block11a2.PORTBADDR3 +address_b[3] => ram_block11a3.PORTBADDR3 +address_b[3] => ram_block11a4.PORTBADDR3 +address_b[3] => ram_block11a5.PORTBADDR3 +address_b[3] => ram_block11a6.PORTBADDR3 +address_b[3] => ram_block11a7.PORTBADDR3 +address_b[3] => ram_block11a8.PORTBADDR3 +address_b[3] => ram_block11a9.PORTBADDR3 +address_b[3] => ram_block11a10.PORTBADDR3 +address_b[3] => ram_block11a11.PORTBADDR3 +address_b[3] => ram_block11a12.PORTBADDR3 +address_b[3] => ram_block11a13.PORTBADDR3 +address_b[3] => ram_block11a14.PORTBADDR3 +address_b[3] => ram_block11a15.PORTBADDR3 +address_b[4] => ram_block11a0.PORTBADDR4 +address_b[4] => ram_block11a1.PORTBADDR4 +address_b[4] => ram_block11a2.PORTBADDR4 +address_b[4] => ram_block11a3.PORTBADDR4 +address_b[4] => ram_block11a4.PORTBADDR4 +address_b[4] => ram_block11a5.PORTBADDR4 +address_b[4] => ram_block11a6.PORTBADDR4 +address_b[4] => ram_block11a7.PORTBADDR4 +address_b[4] => ram_block11a8.PORTBADDR4 +address_b[4] => ram_block11a9.PORTBADDR4 +address_b[4] => ram_block11a10.PORTBADDR4 +address_b[4] => ram_block11a11.PORTBADDR4 +address_b[4] => ram_block11a12.PORTBADDR4 +address_b[4] => ram_block11a13.PORTBADDR4 +address_b[4] => ram_block11a14.PORTBADDR4 +address_b[4] => ram_block11a15.PORTBADDR4 +address_b[5] => ram_block11a0.PORTBADDR5 +address_b[5] => ram_block11a1.PORTBADDR5 +address_b[5] => ram_block11a2.PORTBADDR5 +address_b[5] => ram_block11a3.PORTBADDR5 +address_b[5] => ram_block11a4.PORTBADDR5 +address_b[5] => ram_block11a5.PORTBADDR5 +address_b[5] => ram_block11a6.PORTBADDR5 +address_b[5] => ram_block11a7.PORTBADDR5 +address_b[5] => ram_block11a8.PORTBADDR5 +address_b[5] => ram_block11a9.PORTBADDR5 +address_b[5] => ram_block11a10.PORTBADDR5 +address_b[5] => ram_block11a11.PORTBADDR5 +address_b[5] => ram_block11a12.PORTBADDR5 +address_b[5] => ram_block11a13.PORTBADDR5 +address_b[5] => ram_block11a14.PORTBADDR5 +address_b[5] => ram_block11a15.PORTBADDR5 +address_b[6] => ram_block11a0.PORTBADDR6 +address_b[6] => ram_block11a1.PORTBADDR6 +address_b[6] => ram_block11a2.PORTBADDR6 +address_b[6] => ram_block11a3.PORTBADDR6 +address_b[6] => ram_block11a4.PORTBADDR6 +address_b[6] => ram_block11a5.PORTBADDR6 +address_b[6] => ram_block11a6.PORTBADDR6 +address_b[6] => ram_block11a7.PORTBADDR6 +address_b[6] => ram_block11a8.PORTBADDR6 +address_b[6] => ram_block11a9.PORTBADDR6 +address_b[6] => ram_block11a10.PORTBADDR6 +address_b[6] => ram_block11a11.PORTBADDR6 +address_b[6] => ram_block11a12.PORTBADDR6 +address_b[6] => ram_block11a13.PORTBADDR6 +address_b[6] => ram_block11a14.PORTBADDR6 +address_b[6] => ram_block11a15.PORTBADDR6 +address_b[7] => ram_block11a0.PORTBADDR7 +address_b[7] => ram_block11a1.PORTBADDR7 +address_b[7] => ram_block11a2.PORTBADDR7 +address_b[7] => ram_block11a3.PORTBADDR7 +address_b[7] => ram_block11a4.PORTBADDR7 +address_b[7] => ram_block11a5.PORTBADDR7 +address_b[7] => ram_block11a6.PORTBADDR7 +address_b[7] => ram_block11a7.PORTBADDR7 +address_b[7] => ram_block11a8.PORTBADDR7 +address_b[7] => ram_block11a9.PORTBADDR7 +address_b[7] => ram_block11a10.PORTBADDR7 +address_b[7] => ram_block11a11.PORTBADDR7 +address_b[7] => ram_block11a12.PORTBADDR7 +address_b[7] => ram_block11a13.PORTBADDR7 +address_b[7] => ram_block11a14.PORTBADDR7 +address_b[7] => ram_block11a15.PORTBADDR7 +address_b[8] => ram_block11a0.PORTBADDR8 +address_b[8] => ram_block11a1.PORTBADDR8 +address_b[8] => ram_block11a2.PORTBADDR8 +address_b[8] => ram_block11a3.PORTBADDR8 +address_b[8] => ram_block11a4.PORTBADDR8 +address_b[8] => ram_block11a5.PORTBADDR8 +address_b[8] => ram_block11a6.PORTBADDR8 +address_b[8] => ram_block11a7.PORTBADDR8 +address_b[8] => ram_block11a8.PORTBADDR8 +address_b[8] => ram_block11a9.PORTBADDR8 +address_b[8] => ram_block11a10.PORTBADDR8 +address_b[8] => ram_block11a11.PORTBADDR8 +address_b[8] => ram_block11a12.PORTBADDR8 +address_b[8] => ram_block11a13.PORTBADDR8 +address_b[8] => ram_block11a14.PORTBADDR8 +address_b[8] => ram_block11a15.PORTBADDR8 +addressstall_b => ram_block11a0.PORTBADDRSTALL +addressstall_b => ram_block11a1.PORTBADDRSTALL +addressstall_b => ram_block11a2.PORTBADDRSTALL +addressstall_b => ram_block11a3.PORTBADDRSTALL +addressstall_b => ram_block11a4.PORTBADDRSTALL +addressstall_b => ram_block11a5.PORTBADDRSTALL +addressstall_b => ram_block11a6.PORTBADDRSTALL +addressstall_b => ram_block11a7.PORTBADDRSTALL +addressstall_b => ram_block11a8.PORTBADDRSTALL +addressstall_b => ram_block11a9.PORTBADDRSTALL +addressstall_b => ram_block11a10.PORTBADDRSTALL +addressstall_b => ram_block11a11.PORTBADDRSTALL +addressstall_b => ram_block11a12.PORTBADDRSTALL +addressstall_b => ram_block11a13.PORTBADDRSTALL +addressstall_b => ram_block11a14.PORTBADDRSTALL +addressstall_b => ram_block11a15.PORTBADDRSTALL +clock0 => ram_block11a0.CLK0 +clock0 => ram_block11a1.CLK0 +clock0 => ram_block11a2.CLK0 +clock0 => ram_block11a3.CLK0 +clock0 => ram_block11a4.CLK0 +clock0 => ram_block11a5.CLK0 +clock0 => ram_block11a6.CLK0 +clock0 => ram_block11a7.CLK0 +clock0 => ram_block11a8.CLK0 +clock0 => ram_block11a9.CLK0 +clock0 => ram_block11a10.CLK0 +clock0 => ram_block11a11.CLK0 +clock0 => ram_block11a12.CLK0 +clock0 => ram_block11a13.CLK0 +clock0 => ram_block11a14.CLK0 +clock0 => ram_block11a15.CLK0 +clock1 => ram_block11a0.CLK1 +clock1 => ram_block11a1.CLK1 +clock1 => ram_block11a2.CLK1 +clock1 => ram_block11a3.CLK1 +clock1 => ram_block11a4.CLK1 +clock1 => ram_block11a5.CLK1 +clock1 => ram_block11a6.CLK1 +clock1 => ram_block11a7.CLK1 +clock1 => ram_block11a8.CLK1 +clock1 => ram_block11a9.CLK1 +clock1 => ram_block11a10.CLK1 +clock1 => ram_block11a11.CLK1 +clock1 => ram_block11a12.CLK1 +clock1 => ram_block11a13.CLK1 +clock1 => ram_block11a14.CLK1 +clock1 => ram_block11a15.CLK1 +clocken1 => ram_block11a0.ENA1 +clocken1 => ram_block11a1.ENA1 +clocken1 => ram_block11a2.ENA1 +clocken1 => ram_block11a3.ENA1 +clocken1 => ram_block11a4.ENA1 +clocken1 => ram_block11a5.ENA1 +clocken1 => ram_block11a6.ENA1 +clocken1 => ram_block11a7.ENA1 +clocken1 => ram_block11a8.ENA1 +clocken1 => ram_block11a9.ENA1 +clocken1 => ram_block11a10.ENA1 +clocken1 => ram_block11a11.ENA1 +clocken1 => ram_block11a12.ENA1 +clocken1 => ram_block11a13.ENA1 +clocken1 => ram_block11a14.ENA1 +clocken1 => ram_block11a15.ENA1 +data_a[0] => ram_block11a0.PORTADATAIN +data_a[1] => ram_block11a1.PORTADATAIN +data_a[2] => ram_block11a2.PORTADATAIN +data_a[3] => ram_block11a3.PORTADATAIN +data_a[4] => ram_block11a4.PORTADATAIN +data_a[5] => ram_block11a5.PORTADATAIN +data_a[6] => ram_block11a6.PORTADATAIN +data_a[7] => ram_block11a7.PORTADATAIN +data_a[8] => ram_block11a8.PORTADATAIN +data_a[9] => ram_block11a9.PORTADATAIN +data_a[10] => ram_block11a10.PORTADATAIN +data_a[11] => ram_block11a11.PORTADATAIN +data_a[12] => ram_block11a12.PORTADATAIN +data_a[13] => ram_block11a13.PORTADATAIN +data_a[14] => ram_block11a14.PORTADATAIN +data_a[15] => ram_block11a15.PORTADATAIN +q_b[0] <= ram_block11a0.PORTBDATAOUT +q_b[1] <= ram_block11a1.PORTBDATAOUT +q_b[2] <= ram_block11a2.PORTBDATAOUT +q_b[3] <= ram_block11a3.PORTBDATAOUT +q_b[4] <= ram_block11a4.PORTBDATAOUT +q_b[5] <= ram_block11a5.PORTBDATAOUT +q_b[6] <= ram_block11a6.PORTBDATAOUT +q_b[7] <= ram_block11a7.PORTBDATAOUT +q_b[8] <= ram_block11a8.PORTBDATAOUT +q_b[9] <= ram_block11a9.PORTBDATAOUT +q_b[10] <= ram_block11a10.PORTBDATAOUT +q_b[11] <= ram_block11a11.PORTBDATAOUT +q_b[12] <= ram_block11a12.PORTBDATAOUT +q_b[13] <= ram_block11a13.PORTBDATAOUT +q_b[14] <= ram_block11a14.PORTBDATAOUT +q_b[15] <= ram_block11a15.PORTBDATAOUT +wren_a => ram_block11a0.PORTAWE +wren_a => ram_block11a0.ENA0 +wren_a => ram_block11a1.PORTAWE +wren_a => ram_block11a1.ENA0 +wren_a => ram_block11a2.PORTAWE +wren_a => ram_block11a2.ENA0 +wren_a => ram_block11a3.PORTAWE +wren_a => ram_block11a3.ENA0 +wren_a => ram_block11a4.PORTAWE +wren_a => ram_block11a4.ENA0 +wren_a => ram_block11a5.PORTAWE +wren_a => ram_block11a5.ENA0 +wren_a => ram_block11a6.PORTAWE +wren_a => ram_block11a6.ENA0 +wren_a => ram_block11a7.PORTAWE +wren_a => ram_block11a7.ENA0 +wren_a => ram_block11a8.PORTAWE +wren_a => ram_block11a8.ENA0 +wren_a => ram_block11a9.PORTAWE +wren_a => ram_block11a9.ENA0 +wren_a => ram_block11a10.PORTAWE +wren_a => ram_block11a10.ENA0 +wren_a => ram_block11a11.PORTAWE +wren_a => ram_block11a11.ENA0 +wren_a => ram_block11a12.PORTAWE +wren_a => ram_block11a12.ENA0 +wren_a => ram_block11a13.PORTAWE +wren_a => ram_block11a13.ENA0 +wren_a => ram_block11a14.PORTAWE +wren_a => ram_block11a14.ENA0 +wren_a => ram_block11a15.PORTAWE +wren_a => ram_block11a15.ENA0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp +clock => dffe12a[9].CLK +clock => dffe12a[8].CLK +clock => dffe12a[7].CLK +clock => dffe12a[6].CLK +clock => dffe12a[5].CLK +clock => dffe12a[4].CLK +clock => dffe12a[3].CLK +clock => dffe12a[2].CLK +clock => dffe12a[1].CLK +clock => dffe12a[0].CLK +clrn => dffe12a[9].ACLR +clrn => dffe12a[8].ACLR +clrn => dffe12a[7].ACLR +clrn => dffe12a[6].ACLR +clrn => dffe12a[5].ACLR +clrn => dffe12a[4].ACLR +clrn => dffe12a[3].ACLR +clrn => dffe12a[2].ACLR +clrn => dffe12a[1].ACLR +clrn => dffe12a[0].ACLR +d[0] => dffe12a[0].IN0 +d[1] => dffe12a[1].IN0 +d[2] => dffe12a[2].IN0 +d[3] => dffe12a[3].IN0 +d[4] => dffe12a[4].IN0 +d[5] => dffe12a[5].IN0 +d[6] => dffe12a[6].IN0 +d[7] => dffe12a[7].IN0 +d[8] => dffe12a[8].IN0 +d[9] => dffe12a[9].IN0 +q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp +clock => dffe12a[9].CLK +clock => dffe12a[8].CLK +clock => dffe12a[7].CLK +clock => dffe12a[6].CLK +clock => dffe12a[5].CLK +clock => dffe12a[4].CLK +clock => dffe12a[3].CLK +clock => dffe12a[2].CLK +clock => dffe12a[1].CLK +clock => dffe12a[0].CLK +clrn => dffe12a[9].ACLR +clrn => dffe12a[8].ACLR +clrn => dffe12a[7].ACLR +clrn => dffe12a[6].ACLR +clrn => dffe12a[5].ACLR +clrn => dffe12a[4].ACLR +clrn => dffe12a[3].ACLR +clrn => dffe12a[2].ACLR +clrn => dffe12a[1].ACLR +clrn => dffe12a[0].ACLR +d[0] => dffe12a[0].IN0 +d[1] => dffe12a[1].IN0 +d[2] => dffe12a[2].IN0 +d[3] => dffe12a[3].IN0 +d[4] => dffe12a[4].IN0 +d[5] => dffe12a[5].IN0 +d[6] => dffe12a[6].IN0 +d[7] => dffe12a[7].IN0 +d[8] => dffe12a[8].IN0 +d[9] => dffe12a[9].IN0 +q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp +clock => dffpipe_pe9:dffpipe13.clock +clrn => dffpipe_pe9:dffpipe13.clrn +d[0] => dffpipe_pe9:dffpipe13.d[0] +d[1] => dffpipe_pe9:dffpipe13.d[1] +d[2] => dffpipe_pe9:dffpipe13.d[2] +d[3] => dffpipe_pe9:dffpipe13.d[3] +d[4] => dffpipe_pe9:dffpipe13.d[4] +d[5] => dffpipe_pe9:dffpipe13.d[5] +d[6] => dffpipe_pe9:dffpipe13.d[6] +d[7] => dffpipe_pe9:dffpipe13.d[7] +d[8] => dffpipe_pe9:dffpipe13.d[8] +d[9] => dffpipe_pe9:dffpipe13.d[9] +q[0] <= dffpipe_pe9:dffpipe13.q[0] +q[1] <= dffpipe_pe9:dffpipe13.q[1] +q[2] <= dffpipe_pe9:dffpipe13.q[2] +q[3] <= dffpipe_pe9:dffpipe13.q[3] +q[4] <= dffpipe_pe9:dffpipe13.q[4] +q[5] <= dffpipe_pe9:dffpipe13.q[5] +q[6] <= dffpipe_pe9:dffpipe13.q[6] +q[7] <= dffpipe_pe9:dffpipe13.q[7] +q[8] <= dffpipe_pe9:dffpipe13.q[8] +q[9] <= dffpipe_pe9:dffpipe13.q[9] + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 +clock => dffe14a[9].CLK +clock => dffe14a[8].CLK +clock => dffe14a[7].CLK +clock => dffe14a[6].CLK +clock => dffe14a[5].CLK +clock => dffe14a[4].CLK +clock => dffe14a[3].CLK +clock => dffe14a[2].CLK +clock => dffe14a[1].CLK +clock => dffe14a[0].CLK +clock => dffe15a[9].CLK +clock => dffe15a[8].CLK +clock => dffe15a[7].CLK +clock => dffe15a[6].CLK +clock => dffe15a[5].CLK +clock => dffe15a[4].CLK +clock => dffe15a[3].CLK +clock => dffe15a[2].CLK +clock => dffe15a[1].CLK +clock => dffe15a[0].CLK +clrn => dffe14a[9].ACLR +clrn => dffe14a[8].ACLR +clrn => dffe14a[7].ACLR +clrn => dffe14a[6].ACLR +clrn => dffe14a[5].ACLR +clrn => dffe14a[4].ACLR +clrn => dffe14a[3].ACLR +clrn => dffe14a[2].ACLR +clrn => dffe14a[1].ACLR +clrn => dffe14a[0].ACLR +clrn => dffe15a[9].ACLR +clrn => dffe15a[8].ACLR +clrn => dffe15a[7].ACLR +clrn => dffe15a[6].ACLR +clrn => dffe15a[5].ACLR +clrn => dffe15a[4].ACLR +clrn => dffe15a[3].ACLR +clrn => dffe15a[2].ACLR +clrn => dffe15a[1].ACLR +clrn => dffe15a[0].ACLR +d[0] => dffe14a[0].IN0 +d[1] => dffe14a[1].IN0 +d[2] => dffe14a[2].IN0 +d[3] => dffe14a[3].IN0 +d[4] => dffe14a[4].IN0 +d[5] => dffe14a[5].IN0 +d[6] => dffe14a[6].IN0 +d[7] => dffe14a[7].IN0 +d[8] => dffe14a[8].IN0 +d[9] => dffe14a[9].IN0 +q[0] <= dffe15a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe15a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe15a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe15a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe15a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe15a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe15a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe15a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe15a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe15a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp +clock => dffe12a[9].CLK +clock => dffe12a[8].CLK +clock => dffe12a[7].CLK +clock => dffe12a[6].CLK +clock => dffe12a[5].CLK +clock => dffe12a[4].CLK +clock => dffe12a[3].CLK +clock => dffe12a[2].CLK +clock => dffe12a[1].CLK +clock => dffe12a[0].CLK +clrn => dffe12a[9].ACLR +clrn => dffe12a[8].ACLR +clrn => dffe12a[7].ACLR +clrn => dffe12a[6].ACLR +clrn => dffe12a[5].ACLR +clrn => dffe12a[4].ACLR +clrn => dffe12a[3].ACLR +clrn => dffe12a[2].ACLR +clrn => dffe12a[1].ACLR +clrn => dffe12a[0].ACLR +d[0] => dffe12a[0].IN0 +d[1] => dffe12a[1].IN0 +d[2] => dffe12a[2].IN0 +d[3] => dffe12a[3].IN0 +d[4] => dffe12a[4].IN0 +d[5] => dffe12a[5].IN0 +d[6] => dffe12a[6].IN0 +d[7] => dffe12a[7].IN0 +d[8] => dffe12a[8].IN0 +d[9] => dffe12a[9].IN0 +q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp +clock => dffe12a[9].CLK +clock => dffe12a[8].CLK +clock => dffe12a[7].CLK +clock => dffe12a[6].CLK +clock => dffe12a[5].CLK +clock => dffe12a[4].CLK +clock => dffe12a[3].CLK +clock => dffe12a[2].CLK +clock => dffe12a[1].CLK +clock => dffe12a[0].CLK +clrn => dffe12a[9].ACLR +clrn => dffe12a[8].ACLR +clrn => dffe12a[7].ACLR +clrn => dffe12a[6].ACLR +clrn => dffe12a[5].ACLR +clrn => dffe12a[4].ACLR +clrn => dffe12a[3].ACLR +clrn => dffe12a[2].ACLR +clrn => dffe12a[1].ACLR +clrn => dffe12a[0].ACLR +d[0] => dffe12a[0].IN0 +d[1] => dffe12a[1].IN0 +d[2] => dffe12a[2].IN0 +d[3] => dffe12a[3].IN0 +d[4] => dffe12a[4].IN0 +d[5] => dffe12a[5].IN0 +d[6] => dffe12a[6].IN0 +d[7] => dffe12a[7].IN0 +d[8] => dffe12a[8].IN0 +d[9] => dffe12a[9].IN0 +q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp +clock => dffpipe_qe9:dffpipe16.clock +clrn => dffpipe_qe9:dffpipe16.clrn +d[0] => dffpipe_qe9:dffpipe16.d[0] +d[1] => dffpipe_qe9:dffpipe16.d[1] +d[2] => dffpipe_qe9:dffpipe16.d[2] +d[3] => dffpipe_qe9:dffpipe16.d[3] +d[4] => dffpipe_qe9:dffpipe16.d[4] +d[5] => dffpipe_qe9:dffpipe16.d[5] +d[6] => dffpipe_qe9:dffpipe16.d[6] +d[7] => dffpipe_qe9:dffpipe16.d[7] +d[8] => dffpipe_qe9:dffpipe16.d[8] +d[9] => dffpipe_qe9:dffpipe16.d[9] +q[0] <= dffpipe_qe9:dffpipe16.q[0] +q[1] <= dffpipe_qe9:dffpipe16.q[1] +q[2] <= dffpipe_qe9:dffpipe16.q[2] +q[3] <= dffpipe_qe9:dffpipe16.q[3] +q[4] <= dffpipe_qe9:dffpipe16.q[4] +q[5] <= dffpipe_qe9:dffpipe16.q[5] +q[6] <= dffpipe_qe9:dffpipe16.q[6] +q[7] <= dffpipe_qe9:dffpipe16.q[7] +q[8] <= dffpipe_qe9:dffpipe16.q[8] +q[9] <= dffpipe_qe9:dffpipe16.q[9] + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 +clock => dffe17a[9].CLK +clock => dffe17a[8].CLK +clock => dffe17a[7].CLK +clock => dffe17a[6].CLK +clock => dffe17a[5].CLK +clock => dffe17a[4].CLK +clock => dffe17a[3].CLK +clock => dffe17a[2].CLK +clock => dffe17a[1].CLK +clock => dffe17a[0].CLK +clock => dffe18a[9].CLK +clock => dffe18a[8].CLK +clock => dffe18a[7].CLK +clock => dffe18a[6].CLK +clock => dffe18a[5].CLK +clock => dffe18a[4].CLK +clock => dffe18a[3].CLK +clock => dffe18a[2].CLK +clock => dffe18a[1].CLK +clock => dffe18a[0].CLK +clrn => dffe17a[9].ACLR +clrn => dffe17a[8].ACLR +clrn => dffe17a[7].ACLR +clrn => dffe17a[6].ACLR +clrn => dffe17a[5].ACLR +clrn => dffe17a[4].ACLR +clrn => dffe17a[3].ACLR +clrn => dffe17a[2].ACLR +clrn => dffe17a[1].ACLR +clrn => dffe17a[0].ACLR +clrn => dffe18a[9].ACLR +clrn => dffe18a[8].ACLR +clrn => dffe18a[7].ACLR +clrn => dffe18a[6].ACLR +clrn => dffe18a[5].ACLR +clrn => dffe18a[4].ACLR +clrn => dffe18a[3].ACLR +clrn => dffe18a[2].ACLR +clrn => dffe18a[1].ACLR +clrn => dffe18a[0].ACLR +d[0] => dffe17a[0].IN0 +d[1] => dffe17a[1].IN0 +d[2] => dffe17a[2].IN0 +d[3] => dffe17a[3].IN0 +d[4] => dffe17a[4].IN0 +d[5] => dffe17a[5].IN0 +d[6] => dffe17a[6].IN0 +d[7] => dffe17a[7].IN0 +d[8] => dffe17a[8].IN0 +d[9] => dffe17a[9].IN0 +q[0] <= dffe18a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe18a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe18a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe18a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe18a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe18a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe18a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe18a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe18a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe18a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp +aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE +dataa[0] => data_wire[2].IN0 +dataa[1] => data_wire[2].IN0 +dataa[2] => data_wire[3].IN0 +dataa[3] => data_wire[3].IN0 +dataa[4] => data_wire[4].IN0 +dataa[5] => data_wire[4].IN0 +dataa[6] => data_wire[5].IN0 +dataa[7] => data_wire[5].IN0 +dataa[8] => data_wire[6].IN0 +dataa[9] => data_wire[6].IN0 +datab[0] => data_wire[2].IN1 +datab[1] => data_wire[2].IN1 +datab[2] => data_wire[3].IN1 +datab[3] => data_wire[3].IN1 +datab[4] => data_wire[4].IN1 +datab[5] => data_wire[4].IN1 +datab[6] => data_wire[5].IN1 +datab[7] => data_wire[5].IN1 +datab[8] => data_wire[6].IN1 +datab[9] => data_wire[6].IN1 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp +aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE +dataa[0] => data_wire[2].IN0 +dataa[1] => data_wire[2].IN0 +dataa[2] => data_wire[3].IN0 +dataa[3] => data_wire[3].IN0 +dataa[4] => data_wire[4].IN0 +dataa[5] => data_wire[4].IN0 +dataa[6] => data_wire[5].IN0 +dataa[7] => data_wire[5].IN0 +dataa[8] => data_wire[6].IN0 +dataa[9] => data_wire[6].IN0 +datab[0] => data_wire[2].IN1 +datab[1] => data_wire[2].IN1 +datab[2] => data_wire[3].IN1 +datab[3] => data_wire[3].IN1 +datab[4] => data_wire[4].IN1 +datab[5] => data_wire[4].IN1 +datab[6] => data_wire[5].IN1 +datab[7] => data_wire[5].IN1 +datab[8] => data_wire[6].IN1 +datab[9] => data_wire[6].IN1 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1 +aclr => aclr.IN1 +data[0] => data[0].IN1 +data[1] => data[1].IN1 +data[2] => data[2].IN1 +data[3] => data[3].IN1 +data[4] => data[4].IN1 +data[5] => data[5].IN1 +data[6] => data[6].IN1 +data[7] => data[7].IN1 +data[8] => data[8].IN1 +data[9] => data[9].IN1 +data[10] => data[10].IN1 +data[11] => data[11].IN1 +data[12] => data[12].IN1 +data[13] => data[13].IN1 +data[14] => data[14].IN1 +data[15] => data[15].IN1 +rdclk => rdclk.IN1 +rdreq => rdreq.IN1 +wrclk => wrclk.IN1 +wrreq => wrreq.IN1 +q[0] <= dcfifo:dcfifo_component.q +q[1] <= dcfifo:dcfifo_component.q +q[2] <= dcfifo:dcfifo_component.q +q[3] <= dcfifo:dcfifo_component.q +q[4] <= dcfifo:dcfifo_component.q +q[5] <= dcfifo:dcfifo_component.q +q[6] <= dcfifo:dcfifo_component.q +q[7] <= dcfifo:dcfifo_component.q +q[8] <= dcfifo:dcfifo_component.q +q[9] <= dcfifo:dcfifo_component.q +q[10] <= dcfifo:dcfifo_component.q +q[11] <= dcfifo:dcfifo_component.q +q[12] <= dcfifo:dcfifo_component.q +q[13] <= dcfifo:dcfifo_component.q +q[14] <= dcfifo:dcfifo_component.q +q[15] <= dcfifo:dcfifo_component.q +rdempty <= dcfifo:dcfifo_component.rdempty +rdusedw[0] <= dcfifo:dcfifo_component.rdusedw +rdusedw[1] <= dcfifo:dcfifo_component.rdusedw +rdusedw[2] <= dcfifo:dcfifo_component.rdusedw +rdusedw[3] <= dcfifo:dcfifo_component.rdusedw +rdusedw[4] <= dcfifo:dcfifo_component.rdusedw +rdusedw[5] <= dcfifo:dcfifo_component.rdusedw +rdusedw[6] <= dcfifo:dcfifo_component.rdusedw +rdusedw[7] <= dcfifo:dcfifo_component.rdusedw +rdusedw[8] <= dcfifo:dcfifo_component.rdusedw +wrfull <= dcfifo:dcfifo_component.wrfull +wrusedw[0] <= dcfifo:dcfifo_component.wrusedw +wrusedw[1] <= dcfifo:dcfifo_component.wrusedw +wrusedw[2] <= dcfifo:dcfifo_component.wrusedw +wrusedw[3] <= dcfifo:dcfifo_component.wrusedw +wrusedw[4] <= dcfifo:dcfifo_component.wrusedw +wrusedw[5] <= dcfifo:dcfifo_component.wrusedw +wrusedw[6] <= dcfifo:dcfifo_component.wrusedw +wrusedw[7] <= dcfifo:dcfifo_component.wrusedw +wrusedw[8] <= dcfifo:dcfifo_component.wrusedw + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component +data[0] => dcfifo_v5o1:auto_generated.data[0] +data[1] => dcfifo_v5o1:auto_generated.data[1] +data[2] => dcfifo_v5o1:auto_generated.data[2] +data[3] => dcfifo_v5o1:auto_generated.data[3] +data[4] => dcfifo_v5o1:auto_generated.data[4] +data[5] => dcfifo_v5o1:auto_generated.data[5] +data[6] => dcfifo_v5o1:auto_generated.data[6] +data[7] => dcfifo_v5o1:auto_generated.data[7] +data[8] => dcfifo_v5o1:auto_generated.data[8] +data[9] => dcfifo_v5o1:auto_generated.data[9] +data[10] => dcfifo_v5o1:auto_generated.data[10] +data[11] => dcfifo_v5o1:auto_generated.data[11] +data[12] => dcfifo_v5o1:auto_generated.data[12] +data[13] => dcfifo_v5o1:auto_generated.data[13] +data[14] => dcfifo_v5o1:auto_generated.data[14] +data[15] => dcfifo_v5o1:auto_generated.data[15] +q[0] <= dcfifo_v5o1:auto_generated.q[0] +q[1] <= dcfifo_v5o1:auto_generated.q[1] +q[2] <= dcfifo_v5o1:auto_generated.q[2] +q[3] <= dcfifo_v5o1:auto_generated.q[3] +q[4] <= dcfifo_v5o1:auto_generated.q[4] +q[5] <= dcfifo_v5o1:auto_generated.q[5] +q[6] <= dcfifo_v5o1:auto_generated.q[6] +q[7] <= dcfifo_v5o1:auto_generated.q[7] +q[8] <= dcfifo_v5o1:auto_generated.q[8] +q[9] <= dcfifo_v5o1:auto_generated.q[9] +q[10] <= dcfifo_v5o1:auto_generated.q[10] +q[11] <= dcfifo_v5o1:auto_generated.q[11] +q[12] <= dcfifo_v5o1:auto_generated.q[12] +q[13] <= dcfifo_v5o1:auto_generated.q[13] +q[14] <= dcfifo_v5o1:auto_generated.q[14] +q[15] <= dcfifo_v5o1:auto_generated.q[15] +rdclk => dcfifo_v5o1:auto_generated.rdclk +rdreq => dcfifo_v5o1:auto_generated.rdreq +wrclk => dcfifo_v5o1:auto_generated.wrclk +wrreq => dcfifo_v5o1:auto_generated.wrreq +aclr => dcfifo_v5o1:auto_generated.aclr +rdempty <= dcfifo_v5o1:auto_generated.rdempty +rdfull <= <UNC> +wrempty <= <GND> +wrfull <= dcfifo_v5o1:auto_generated.wrfull +rdusedw[0] <= dcfifo_v5o1:auto_generated.rdusedw[0] +rdusedw[1] <= dcfifo_v5o1:auto_generated.rdusedw[1] +rdusedw[2] <= dcfifo_v5o1:auto_generated.rdusedw[2] +rdusedw[3] <= dcfifo_v5o1:auto_generated.rdusedw[3] +rdusedw[4] <= dcfifo_v5o1:auto_generated.rdusedw[4] +rdusedw[5] <= dcfifo_v5o1:auto_generated.rdusedw[5] +rdusedw[6] <= dcfifo_v5o1:auto_generated.rdusedw[6] +rdusedw[7] <= dcfifo_v5o1:auto_generated.rdusedw[7] +rdusedw[8] <= dcfifo_v5o1:auto_generated.rdusedw[8] +wrusedw[0] <= dcfifo_v5o1:auto_generated.wrusedw[0] +wrusedw[1] <= dcfifo_v5o1:auto_generated.wrusedw[1] +wrusedw[2] <= dcfifo_v5o1:auto_generated.wrusedw[2] +wrusedw[3] <= dcfifo_v5o1:auto_generated.wrusedw[3] +wrusedw[4] <= dcfifo_v5o1:auto_generated.wrusedw[4] +wrusedw[5] <= dcfifo_v5o1:auto_generated.wrusedw[5] +wrusedw[6] <= dcfifo_v5o1:auto_generated.wrusedw[6] +wrusedw[7] <= dcfifo_v5o1:auto_generated.wrusedw[7] +wrusedw[8] <= dcfifo_v5o1:auto_generated.wrusedw[8] + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated +aclr => a_graycounter_s57:rdptr_g1p.aclr +aclr => a_graycounter_ojc:wrptr_g1p.aclr +aclr => altsyncram_de51:fifo_ram.aclr1 +aclr => delayed_wrptr_g[9].IN0 +aclr => rdptr_g[9].IN0 +aclr => wrptr_g[9].IN0 +aclr => _.IN0 +aclr => _.IN0 +aclr => _.IN0 +aclr => _.IN0 +aclr => _.IN0 +aclr => _.IN0 +data[0] => altsyncram_de51:fifo_ram.data_a[0] +data[1] => altsyncram_de51:fifo_ram.data_a[1] +data[2] => altsyncram_de51:fifo_ram.data_a[2] +data[3] => altsyncram_de51:fifo_ram.data_a[3] +data[4] => altsyncram_de51:fifo_ram.data_a[4] +data[5] => altsyncram_de51:fifo_ram.data_a[5] +data[6] => altsyncram_de51:fifo_ram.data_a[6] +data[7] => altsyncram_de51:fifo_ram.data_a[7] +data[8] => altsyncram_de51:fifo_ram.data_a[8] +data[9] => altsyncram_de51:fifo_ram.data_a[9] +data[10] => altsyncram_de51:fifo_ram.data_a[10] +data[11] => altsyncram_de51:fifo_ram.data_a[11] +data[12] => altsyncram_de51:fifo_ram.data_a[12] +data[13] => altsyncram_de51:fifo_ram.data_a[13] +data[14] => altsyncram_de51:fifo_ram.data_a[14] +data[15] => altsyncram_de51:fifo_ram.data_a[15] +q[0] <= altsyncram_de51:fifo_ram.q_b[0] +q[1] <= altsyncram_de51:fifo_ram.q_b[1] +q[2] <= altsyncram_de51:fifo_ram.q_b[2] +q[3] <= altsyncram_de51:fifo_ram.q_b[3] +q[4] <= altsyncram_de51:fifo_ram.q_b[4] +q[5] <= altsyncram_de51:fifo_ram.q_b[5] +q[6] <= altsyncram_de51:fifo_ram.q_b[6] +q[7] <= altsyncram_de51:fifo_ram.q_b[7] +q[8] <= altsyncram_de51:fifo_ram.q_b[8] +q[9] <= altsyncram_de51:fifo_ram.q_b[9] +q[10] <= altsyncram_de51:fifo_ram.q_b[10] +q[11] <= altsyncram_de51:fifo_ram.q_b[11] +q[12] <= altsyncram_de51:fifo_ram.q_b[12] +q[13] <= altsyncram_de51:fifo_ram.q_b[13] +q[14] <= altsyncram_de51:fifo_ram.q_b[14] +q[15] <= altsyncram_de51:fifo_ram.q_b[15] +rdclk => a_graycounter_s57:rdptr_g1p.clock +rdclk => altsyncram_de51:fifo_ram.clock1 +rdclk => dffpipe_oe9:rs_brp.clock +rdclk => dffpipe_oe9:rs_bwp.clock +rdclk => alt_synch_pipe_qld:rs_dgwp.clock +rdclk => rdptr_g[9].CLK +rdclk => rdptr_g[8].CLK +rdclk => rdptr_g[7].CLK +rdclk => rdptr_g[6].CLK +rdclk => rdptr_g[5].CLK +rdclk => rdptr_g[4].CLK +rdclk => rdptr_g[3].CLK +rdclk => rdptr_g[2].CLK +rdclk => rdptr_g[1].CLK +rdclk => rdptr_g[0].CLK +rdempty <= int_rdempty.DB_MAX_OUTPUT_PORT_TYPE +rdreq => valid_rdreq.IN0 +rdusedw[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +wrclk => a_graycounter_ojc:wrptr_g1p.clock +wrclk => altsyncram_de51:fifo_ram.clock0 +wrclk => dffpipe_oe9:ws_brp.clock +wrclk => dffpipe_oe9:ws_bwp.clock +wrclk => alt_synch_pipe_rld:ws_dgrp.clock +wrclk => delayed_wrptr_g[9].CLK +wrclk => delayed_wrptr_g[8].CLK +wrclk => delayed_wrptr_g[7].CLK +wrclk => delayed_wrptr_g[6].CLK +wrclk => delayed_wrptr_g[5].CLK +wrclk => delayed_wrptr_g[4].CLK +wrclk => delayed_wrptr_g[3].CLK +wrclk => delayed_wrptr_g[2].CLK +wrclk => delayed_wrptr_g[1].CLK +wrclk => delayed_wrptr_g[0].CLK +wrclk => wrptr_g[9].CLK +wrclk => wrptr_g[8].CLK +wrclk => wrptr_g[7].CLK +wrclk => wrptr_g[6].CLK +wrclk => wrptr_g[5].CLK +wrclk => wrptr_g[4].CLK +wrclk => wrptr_g[3].CLK +wrclk => wrptr_g[2].CLK +wrclk => wrptr_g[1].CLK +wrclk => wrptr_g[0].CLK +wrfull <= int_wrfull.DB_MAX_OUTPUT_PORT_TYPE +wrreq => valid_wrreq.IN0 +wrusedw[0] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[1] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[2] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[3] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[4] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[5] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[6] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[7] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[8] <= op_2.DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin +bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE +bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE +bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE +bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE +bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE +bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE +bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE +bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE +bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE +bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE +gray[0] => xor0.IN0 +gray[1] => xor1.IN0 +gray[2] => xor2.IN0 +gray[3] => xor3.IN0 +gray[4] => xor4.IN0 +gray[5] => xor5.IN0 +gray[6] => xor6.IN0 +gray[7] => xor7.IN0 +gray[8] => xor8.IN1 +gray[9] => bin[9].DATAIN +gray[9] => xor8.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin +bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE +bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE +bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE +bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE +bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE +bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE +bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE +bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE +bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE +bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE +gray[0] => xor0.IN0 +gray[1] => xor1.IN0 +gray[2] => xor2.IN0 +gray[3] => xor3.IN0 +gray[4] => xor4.IN0 +gray[5] => xor5.IN0 +gray[6] => xor6.IN0 +gray[7] => xor7.IN0 +gray[8] => xor8.IN1 +gray[9] => bin[9].DATAIN +gray[9] => xor8.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin +bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE +bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE +bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE +bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE +bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE +bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE +bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE +bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE +bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE +bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE +gray[0] => xor0.IN0 +gray[1] => xor1.IN0 +gray[2] => xor2.IN0 +gray[3] => xor3.IN0 +gray[4] => xor4.IN0 +gray[5] => xor5.IN0 +gray[6] => xor6.IN0 +gray[7] => xor7.IN0 +gray[8] => xor8.IN1 +gray[9] => bin[9].DATAIN +gray[9] => xor8.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin +bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE +bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE +bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE +bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE +bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE +bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE +bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE +bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE +bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE +bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE +gray[0] => xor0.IN0 +gray[1] => xor1.IN0 +gray[2] => xor2.IN0 +gray[3] => xor3.IN0 +gray[4] => xor4.IN0 +gray[5] => xor5.IN0 +gray[6] => xor6.IN0 +gray[7] => xor7.IN0 +gray[8] => xor8.IN1 +gray[9] => bin[9].DATAIN +gray[9] => xor8.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p +aclr => counter5a1.IN0 +aclr => counter5a0.IN0 +aclr => parity6.IN0 +aclr => sub_parity7a[2].IN0 +aclr => sub_parity7a[1].IN0 +aclr => sub_parity7a[0].IN0 +clock => counter5a0.CLK +clock => counter5a1.CLK +clock => counter5a2.CLK +clock => counter5a3.CLK +clock => counter5a4.CLK +clock => counter5a5.CLK +clock => counter5a6.CLK +clock => counter5a7.CLK +clock => counter5a8.CLK +clock => counter5a9.CLK +clock => parity6.CLK +clock => sub_parity7a[2].CLK +clock => sub_parity7a[1].CLK +clock => sub_parity7a[0].CLK +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => cntr_cout[0].IN0 +cnt_en => parity_cout.IN1 +q[0] <= counter5a0.DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter5a1.DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter5a2.DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter5a3.DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter5a4.DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter5a5.DB_MAX_OUTPUT_PORT_TYPE +q[6] <= counter5a6.DB_MAX_OUTPUT_PORT_TYPE +q[7] <= counter5a7.DB_MAX_OUTPUT_PORT_TYPE +q[8] <= counter5a8.DB_MAX_OUTPUT_PORT_TYPE +q[9] <= counter5a9.DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p +aclr => counter8a1.IN0 +aclr => counter8a0.IN0 +aclr => parity9.IN0 +aclr => sub_parity10a[2].IN0 +aclr => sub_parity10a[1].IN0 +aclr => sub_parity10a[0].IN0 +clock => counter8a0.CLK +clock => counter8a1.CLK +clock => counter8a2.CLK +clock => counter8a3.CLK +clock => counter8a4.CLK +clock => counter8a5.CLK +clock => counter8a6.CLK +clock => counter8a7.CLK +clock => counter8a8.CLK +clock => counter8a9.CLK +clock => parity9.CLK +clock => sub_parity10a[2].CLK +clock => sub_parity10a[1].CLK +clock => sub_parity10a[0].CLK +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => cntr_cout[0].IN0 +cnt_en => parity_cout.IN1 +q[0] <= counter8a0.DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter8a1.DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter8a2.DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter8a3.DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter8a4.DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter8a5.DB_MAX_OUTPUT_PORT_TYPE +q[6] <= counter8a6.DB_MAX_OUTPUT_PORT_TYPE +q[7] <= counter8a7.DB_MAX_OUTPUT_PORT_TYPE +q[8] <= counter8a8.DB_MAX_OUTPUT_PORT_TYPE +q[9] <= counter8a9.DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram +aclr1 => ram_block11a0.CLR1 +aclr1 => ram_block11a1.CLR1 +aclr1 => ram_block11a2.CLR1 +aclr1 => ram_block11a3.CLR1 +aclr1 => ram_block11a4.CLR1 +aclr1 => ram_block11a5.CLR1 +aclr1 => ram_block11a6.CLR1 +aclr1 => ram_block11a7.CLR1 +aclr1 => ram_block11a8.CLR1 +aclr1 => ram_block11a9.CLR1 +aclr1 => ram_block11a10.CLR1 +aclr1 => ram_block11a11.CLR1 +aclr1 => ram_block11a12.CLR1 +aclr1 => ram_block11a13.CLR1 +aclr1 => ram_block11a14.CLR1 +aclr1 => ram_block11a15.CLR1 +address_a[0] => ram_block11a0.PORTAADDR +address_a[0] => ram_block11a1.PORTAADDR +address_a[0] => ram_block11a2.PORTAADDR +address_a[0] => ram_block11a3.PORTAADDR +address_a[0] => ram_block11a4.PORTAADDR +address_a[0] => ram_block11a5.PORTAADDR +address_a[0] => ram_block11a6.PORTAADDR +address_a[0] => ram_block11a7.PORTAADDR +address_a[0] => ram_block11a8.PORTAADDR +address_a[0] => ram_block11a9.PORTAADDR +address_a[0] => ram_block11a10.PORTAADDR +address_a[0] => ram_block11a11.PORTAADDR +address_a[0] => ram_block11a12.PORTAADDR +address_a[0] => ram_block11a13.PORTAADDR +address_a[0] => ram_block11a14.PORTAADDR +address_a[0] => ram_block11a15.PORTAADDR +address_a[1] => ram_block11a0.PORTAADDR1 +address_a[1] => ram_block11a1.PORTAADDR1 +address_a[1] => ram_block11a2.PORTAADDR1 +address_a[1] => ram_block11a3.PORTAADDR1 +address_a[1] => ram_block11a4.PORTAADDR1 +address_a[1] => ram_block11a5.PORTAADDR1 +address_a[1] => ram_block11a6.PORTAADDR1 +address_a[1] => ram_block11a7.PORTAADDR1 +address_a[1] => ram_block11a8.PORTAADDR1 +address_a[1] => ram_block11a9.PORTAADDR1 +address_a[1] => ram_block11a10.PORTAADDR1 +address_a[1] => ram_block11a11.PORTAADDR1 +address_a[1] => ram_block11a12.PORTAADDR1 +address_a[1] => ram_block11a13.PORTAADDR1 +address_a[1] => ram_block11a14.PORTAADDR1 +address_a[1] => ram_block11a15.PORTAADDR1 +address_a[2] => ram_block11a0.PORTAADDR2 +address_a[2] => ram_block11a1.PORTAADDR2 +address_a[2] => ram_block11a2.PORTAADDR2 +address_a[2] => ram_block11a3.PORTAADDR2 +address_a[2] => ram_block11a4.PORTAADDR2 +address_a[2] => ram_block11a5.PORTAADDR2 +address_a[2] => ram_block11a6.PORTAADDR2 +address_a[2] => ram_block11a7.PORTAADDR2 +address_a[2] => ram_block11a8.PORTAADDR2 +address_a[2] => ram_block11a9.PORTAADDR2 +address_a[2] => ram_block11a10.PORTAADDR2 +address_a[2] => ram_block11a11.PORTAADDR2 +address_a[2] => ram_block11a12.PORTAADDR2 +address_a[2] => ram_block11a13.PORTAADDR2 +address_a[2] => ram_block11a14.PORTAADDR2 +address_a[2] => ram_block11a15.PORTAADDR2 +address_a[3] => ram_block11a0.PORTAADDR3 +address_a[3] => ram_block11a1.PORTAADDR3 +address_a[3] => ram_block11a2.PORTAADDR3 +address_a[3] => ram_block11a3.PORTAADDR3 +address_a[3] => ram_block11a4.PORTAADDR3 +address_a[3] => ram_block11a5.PORTAADDR3 +address_a[3] => ram_block11a6.PORTAADDR3 +address_a[3] => ram_block11a7.PORTAADDR3 +address_a[3] => ram_block11a8.PORTAADDR3 +address_a[3] => ram_block11a9.PORTAADDR3 +address_a[3] => ram_block11a10.PORTAADDR3 +address_a[3] => ram_block11a11.PORTAADDR3 +address_a[3] => ram_block11a12.PORTAADDR3 +address_a[3] => ram_block11a13.PORTAADDR3 +address_a[3] => ram_block11a14.PORTAADDR3 +address_a[3] => ram_block11a15.PORTAADDR3 +address_a[4] => ram_block11a0.PORTAADDR4 +address_a[4] => ram_block11a1.PORTAADDR4 +address_a[4] => ram_block11a2.PORTAADDR4 +address_a[4] => ram_block11a3.PORTAADDR4 +address_a[4] => ram_block11a4.PORTAADDR4 +address_a[4] => ram_block11a5.PORTAADDR4 +address_a[4] => ram_block11a6.PORTAADDR4 +address_a[4] => ram_block11a7.PORTAADDR4 +address_a[4] => ram_block11a8.PORTAADDR4 +address_a[4] => ram_block11a9.PORTAADDR4 +address_a[4] => ram_block11a10.PORTAADDR4 +address_a[4] => ram_block11a11.PORTAADDR4 +address_a[4] => ram_block11a12.PORTAADDR4 +address_a[4] => ram_block11a13.PORTAADDR4 +address_a[4] => ram_block11a14.PORTAADDR4 +address_a[4] => ram_block11a15.PORTAADDR4 +address_a[5] => ram_block11a0.PORTAADDR5 +address_a[5] => ram_block11a1.PORTAADDR5 +address_a[5] => ram_block11a2.PORTAADDR5 +address_a[5] => ram_block11a3.PORTAADDR5 +address_a[5] => ram_block11a4.PORTAADDR5 +address_a[5] => ram_block11a5.PORTAADDR5 +address_a[5] => ram_block11a6.PORTAADDR5 +address_a[5] => ram_block11a7.PORTAADDR5 +address_a[5] => ram_block11a8.PORTAADDR5 +address_a[5] => ram_block11a9.PORTAADDR5 +address_a[5] => ram_block11a10.PORTAADDR5 +address_a[5] => ram_block11a11.PORTAADDR5 +address_a[5] => ram_block11a12.PORTAADDR5 +address_a[5] => ram_block11a13.PORTAADDR5 +address_a[5] => ram_block11a14.PORTAADDR5 +address_a[5] => ram_block11a15.PORTAADDR5 +address_a[6] => ram_block11a0.PORTAADDR6 +address_a[6] => ram_block11a1.PORTAADDR6 +address_a[6] => ram_block11a2.PORTAADDR6 +address_a[6] => ram_block11a3.PORTAADDR6 +address_a[6] => ram_block11a4.PORTAADDR6 +address_a[6] => ram_block11a5.PORTAADDR6 +address_a[6] => ram_block11a6.PORTAADDR6 +address_a[6] => ram_block11a7.PORTAADDR6 +address_a[6] => ram_block11a8.PORTAADDR6 +address_a[6] => ram_block11a9.PORTAADDR6 +address_a[6] => ram_block11a10.PORTAADDR6 +address_a[6] => ram_block11a11.PORTAADDR6 +address_a[6] => ram_block11a12.PORTAADDR6 +address_a[6] => ram_block11a13.PORTAADDR6 +address_a[6] => ram_block11a14.PORTAADDR6 +address_a[6] => ram_block11a15.PORTAADDR6 +address_a[7] => ram_block11a0.PORTAADDR7 +address_a[7] => ram_block11a1.PORTAADDR7 +address_a[7] => ram_block11a2.PORTAADDR7 +address_a[7] => ram_block11a3.PORTAADDR7 +address_a[7] => ram_block11a4.PORTAADDR7 +address_a[7] => ram_block11a5.PORTAADDR7 +address_a[7] => ram_block11a6.PORTAADDR7 +address_a[7] => ram_block11a7.PORTAADDR7 +address_a[7] => ram_block11a8.PORTAADDR7 +address_a[7] => ram_block11a9.PORTAADDR7 +address_a[7] => ram_block11a10.PORTAADDR7 +address_a[7] => ram_block11a11.PORTAADDR7 +address_a[7] => ram_block11a12.PORTAADDR7 +address_a[7] => ram_block11a13.PORTAADDR7 +address_a[7] => ram_block11a14.PORTAADDR7 +address_a[7] => ram_block11a15.PORTAADDR7 +address_a[8] => ram_block11a0.PORTAADDR8 +address_a[8] => ram_block11a1.PORTAADDR8 +address_a[8] => ram_block11a2.PORTAADDR8 +address_a[8] => ram_block11a3.PORTAADDR8 +address_a[8] => ram_block11a4.PORTAADDR8 +address_a[8] => ram_block11a5.PORTAADDR8 +address_a[8] => ram_block11a6.PORTAADDR8 +address_a[8] => ram_block11a7.PORTAADDR8 +address_a[8] => ram_block11a8.PORTAADDR8 +address_a[8] => ram_block11a9.PORTAADDR8 +address_a[8] => ram_block11a10.PORTAADDR8 +address_a[8] => ram_block11a11.PORTAADDR8 +address_a[8] => ram_block11a12.PORTAADDR8 +address_a[8] => ram_block11a13.PORTAADDR8 +address_a[8] => ram_block11a14.PORTAADDR8 +address_a[8] => ram_block11a15.PORTAADDR8 +address_b[0] => ram_block11a0.PORTBADDR +address_b[0] => ram_block11a1.PORTBADDR +address_b[0] => ram_block11a2.PORTBADDR +address_b[0] => ram_block11a3.PORTBADDR +address_b[0] => ram_block11a4.PORTBADDR +address_b[0] => ram_block11a5.PORTBADDR +address_b[0] => ram_block11a6.PORTBADDR +address_b[0] => ram_block11a7.PORTBADDR +address_b[0] => ram_block11a8.PORTBADDR +address_b[0] => ram_block11a9.PORTBADDR +address_b[0] => ram_block11a10.PORTBADDR +address_b[0] => ram_block11a11.PORTBADDR +address_b[0] => ram_block11a12.PORTBADDR +address_b[0] => ram_block11a13.PORTBADDR +address_b[0] => ram_block11a14.PORTBADDR +address_b[0] => ram_block11a15.PORTBADDR +address_b[1] => ram_block11a0.PORTBADDR1 +address_b[1] => ram_block11a1.PORTBADDR1 +address_b[1] => ram_block11a2.PORTBADDR1 +address_b[1] => ram_block11a3.PORTBADDR1 +address_b[1] => ram_block11a4.PORTBADDR1 +address_b[1] => ram_block11a5.PORTBADDR1 +address_b[1] => ram_block11a6.PORTBADDR1 +address_b[1] => ram_block11a7.PORTBADDR1 +address_b[1] => ram_block11a8.PORTBADDR1 +address_b[1] => ram_block11a9.PORTBADDR1 +address_b[1] => ram_block11a10.PORTBADDR1 +address_b[1] => ram_block11a11.PORTBADDR1 +address_b[1] => ram_block11a12.PORTBADDR1 +address_b[1] => ram_block11a13.PORTBADDR1 +address_b[1] => ram_block11a14.PORTBADDR1 +address_b[1] => ram_block11a15.PORTBADDR1 +address_b[2] => ram_block11a0.PORTBADDR2 +address_b[2] => ram_block11a1.PORTBADDR2 +address_b[2] => ram_block11a2.PORTBADDR2 +address_b[2] => ram_block11a3.PORTBADDR2 +address_b[2] => ram_block11a4.PORTBADDR2 +address_b[2] => ram_block11a5.PORTBADDR2 +address_b[2] => ram_block11a6.PORTBADDR2 +address_b[2] => ram_block11a7.PORTBADDR2 +address_b[2] => ram_block11a8.PORTBADDR2 +address_b[2] => ram_block11a9.PORTBADDR2 +address_b[2] => ram_block11a10.PORTBADDR2 +address_b[2] => ram_block11a11.PORTBADDR2 +address_b[2] => ram_block11a12.PORTBADDR2 +address_b[2] => ram_block11a13.PORTBADDR2 +address_b[2] => ram_block11a14.PORTBADDR2 +address_b[2] => ram_block11a15.PORTBADDR2 +address_b[3] => ram_block11a0.PORTBADDR3 +address_b[3] => ram_block11a1.PORTBADDR3 +address_b[3] => ram_block11a2.PORTBADDR3 +address_b[3] => ram_block11a3.PORTBADDR3 +address_b[3] => ram_block11a4.PORTBADDR3 +address_b[3] => ram_block11a5.PORTBADDR3 +address_b[3] => ram_block11a6.PORTBADDR3 +address_b[3] => ram_block11a7.PORTBADDR3 +address_b[3] => ram_block11a8.PORTBADDR3 +address_b[3] => ram_block11a9.PORTBADDR3 +address_b[3] => ram_block11a10.PORTBADDR3 +address_b[3] => ram_block11a11.PORTBADDR3 +address_b[3] => ram_block11a12.PORTBADDR3 +address_b[3] => ram_block11a13.PORTBADDR3 +address_b[3] => ram_block11a14.PORTBADDR3 +address_b[3] => ram_block11a15.PORTBADDR3 +address_b[4] => ram_block11a0.PORTBADDR4 +address_b[4] => ram_block11a1.PORTBADDR4 +address_b[4] => ram_block11a2.PORTBADDR4 +address_b[4] => ram_block11a3.PORTBADDR4 +address_b[4] => ram_block11a4.PORTBADDR4 +address_b[4] => ram_block11a5.PORTBADDR4 +address_b[4] => ram_block11a6.PORTBADDR4 +address_b[4] => ram_block11a7.PORTBADDR4 +address_b[4] => ram_block11a8.PORTBADDR4 +address_b[4] => ram_block11a9.PORTBADDR4 +address_b[4] => ram_block11a10.PORTBADDR4 +address_b[4] => ram_block11a11.PORTBADDR4 +address_b[4] => ram_block11a12.PORTBADDR4 +address_b[4] => ram_block11a13.PORTBADDR4 +address_b[4] => ram_block11a14.PORTBADDR4 +address_b[4] => ram_block11a15.PORTBADDR4 +address_b[5] => ram_block11a0.PORTBADDR5 +address_b[5] => ram_block11a1.PORTBADDR5 +address_b[5] => ram_block11a2.PORTBADDR5 +address_b[5] => ram_block11a3.PORTBADDR5 +address_b[5] => ram_block11a4.PORTBADDR5 +address_b[5] => ram_block11a5.PORTBADDR5 +address_b[5] => ram_block11a6.PORTBADDR5 +address_b[5] => ram_block11a7.PORTBADDR5 +address_b[5] => ram_block11a8.PORTBADDR5 +address_b[5] => ram_block11a9.PORTBADDR5 +address_b[5] => ram_block11a10.PORTBADDR5 +address_b[5] => ram_block11a11.PORTBADDR5 +address_b[5] => ram_block11a12.PORTBADDR5 +address_b[5] => ram_block11a13.PORTBADDR5 +address_b[5] => ram_block11a14.PORTBADDR5 +address_b[5] => ram_block11a15.PORTBADDR5 +address_b[6] => ram_block11a0.PORTBADDR6 +address_b[6] => ram_block11a1.PORTBADDR6 +address_b[6] => ram_block11a2.PORTBADDR6 +address_b[6] => ram_block11a3.PORTBADDR6 +address_b[6] => ram_block11a4.PORTBADDR6 +address_b[6] => ram_block11a5.PORTBADDR6 +address_b[6] => ram_block11a6.PORTBADDR6 +address_b[6] => ram_block11a7.PORTBADDR6 +address_b[6] => ram_block11a8.PORTBADDR6 +address_b[6] => ram_block11a9.PORTBADDR6 +address_b[6] => ram_block11a10.PORTBADDR6 +address_b[6] => ram_block11a11.PORTBADDR6 +address_b[6] => ram_block11a12.PORTBADDR6 +address_b[6] => ram_block11a13.PORTBADDR6 +address_b[6] => ram_block11a14.PORTBADDR6 +address_b[6] => ram_block11a15.PORTBADDR6 +address_b[7] => ram_block11a0.PORTBADDR7 +address_b[7] => ram_block11a1.PORTBADDR7 +address_b[7] => ram_block11a2.PORTBADDR7 +address_b[7] => ram_block11a3.PORTBADDR7 +address_b[7] => ram_block11a4.PORTBADDR7 +address_b[7] => ram_block11a5.PORTBADDR7 +address_b[7] => ram_block11a6.PORTBADDR7 +address_b[7] => ram_block11a7.PORTBADDR7 +address_b[7] => ram_block11a8.PORTBADDR7 +address_b[7] => ram_block11a9.PORTBADDR7 +address_b[7] => ram_block11a10.PORTBADDR7 +address_b[7] => ram_block11a11.PORTBADDR7 +address_b[7] => ram_block11a12.PORTBADDR7 +address_b[7] => ram_block11a13.PORTBADDR7 +address_b[7] => ram_block11a14.PORTBADDR7 +address_b[7] => ram_block11a15.PORTBADDR7 +address_b[8] => ram_block11a0.PORTBADDR8 +address_b[8] => ram_block11a1.PORTBADDR8 +address_b[8] => ram_block11a2.PORTBADDR8 +address_b[8] => ram_block11a3.PORTBADDR8 +address_b[8] => ram_block11a4.PORTBADDR8 +address_b[8] => ram_block11a5.PORTBADDR8 +address_b[8] => ram_block11a6.PORTBADDR8 +address_b[8] => ram_block11a7.PORTBADDR8 +address_b[8] => ram_block11a8.PORTBADDR8 +address_b[8] => ram_block11a9.PORTBADDR8 +address_b[8] => ram_block11a10.PORTBADDR8 +address_b[8] => ram_block11a11.PORTBADDR8 +address_b[8] => ram_block11a12.PORTBADDR8 +address_b[8] => ram_block11a13.PORTBADDR8 +address_b[8] => ram_block11a14.PORTBADDR8 +address_b[8] => ram_block11a15.PORTBADDR8 +addressstall_b => ram_block11a0.PORTBADDRSTALL +addressstall_b => ram_block11a1.PORTBADDRSTALL +addressstall_b => ram_block11a2.PORTBADDRSTALL +addressstall_b => ram_block11a3.PORTBADDRSTALL +addressstall_b => ram_block11a4.PORTBADDRSTALL +addressstall_b => ram_block11a5.PORTBADDRSTALL +addressstall_b => ram_block11a6.PORTBADDRSTALL +addressstall_b => ram_block11a7.PORTBADDRSTALL +addressstall_b => ram_block11a8.PORTBADDRSTALL +addressstall_b => ram_block11a9.PORTBADDRSTALL +addressstall_b => ram_block11a10.PORTBADDRSTALL +addressstall_b => ram_block11a11.PORTBADDRSTALL +addressstall_b => ram_block11a12.PORTBADDRSTALL +addressstall_b => ram_block11a13.PORTBADDRSTALL +addressstall_b => ram_block11a14.PORTBADDRSTALL +addressstall_b => ram_block11a15.PORTBADDRSTALL +clock0 => ram_block11a0.CLK0 +clock0 => ram_block11a1.CLK0 +clock0 => ram_block11a2.CLK0 +clock0 => ram_block11a3.CLK0 +clock0 => ram_block11a4.CLK0 +clock0 => ram_block11a5.CLK0 +clock0 => ram_block11a6.CLK0 +clock0 => ram_block11a7.CLK0 +clock0 => ram_block11a8.CLK0 +clock0 => ram_block11a9.CLK0 +clock0 => ram_block11a10.CLK0 +clock0 => ram_block11a11.CLK0 +clock0 => ram_block11a12.CLK0 +clock0 => ram_block11a13.CLK0 +clock0 => ram_block11a14.CLK0 +clock0 => ram_block11a15.CLK0 +clock1 => ram_block11a0.CLK1 +clock1 => ram_block11a1.CLK1 +clock1 => ram_block11a2.CLK1 +clock1 => ram_block11a3.CLK1 +clock1 => ram_block11a4.CLK1 +clock1 => ram_block11a5.CLK1 +clock1 => ram_block11a6.CLK1 +clock1 => ram_block11a7.CLK1 +clock1 => ram_block11a8.CLK1 +clock1 => ram_block11a9.CLK1 +clock1 => ram_block11a10.CLK1 +clock1 => ram_block11a11.CLK1 +clock1 => ram_block11a12.CLK1 +clock1 => ram_block11a13.CLK1 +clock1 => ram_block11a14.CLK1 +clock1 => ram_block11a15.CLK1 +clocken1 => ram_block11a0.ENA1 +clocken1 => ram_block11a1.ENA1 +clocken1 => ram_block11a2.ENA1 +clocken1 => ram_block11a3.ENA1 +clocken1 => ram_block11a4.ENA1 +clocken1 => ram_block11a5.ENA1 +clocken1 => ram_block11a6.ENA1 +clocken1 => ram_block11a7.ENA1 +clocken1 => ram_block11a8.ENA1 +clocken1 => ram_block11a9.ENA1 +clocken1 => ram_block11a10.ENA1 +clocken1 => ram_block11a11.ENA1 +clocken1 => ram_block11a12.ENA1 +clocken1 => ram_block11a13.ENA1 +clocken1 => ram_block11a14.ENA1 +clocken1 => ram_block11a15.ENA1 +data_a[0] => ram_block11a0.PORTADATAIN +data_a[1] => ram_block11a1.PORTADATAIN +data_a[2] => ram_block11a2.PORTADATAIN +data_a[3] => ram_block11a3.PORTADATAIN +data_a[4] => ram_block11a4.PORTADATAIN +data_a[5] => ram_block11a5.PORTADATAIN +data_a[6] => ram_block11a6.PORTADATAIN +data_a[7] => ram_block11a7.PORTADATAIN +data_a[8] => ram_block11a8.PORTADATAIN +data_a[9] => ram_block11a9.PORTADATAIN +data_a[10] => ram_block11a10.PORTADATAIN +data_a[11] => ram_block11a11.PORTADATAIN +data_a[12] => ram_block11a12.PORTADATAIN +data_a[13] => ram_block11a13.PORTADATAIN +data_a[14] => ram_block11a14.PORTADATAIN +data_a[15] => ram_block11a15.PORTADATAIN +q_b[0] <= ram_block11a0.PORTBDATAOUT +q_b[1] <= ram_block11a1.PORTBDATAOUT +q_b[2] <= ram_block11a2.PORTBDATAOUT +q_b[3] <= ram_block11a3.PORTBDATAOUT +q_b[4] <= ram_block11a4.PORTBDATAOUT +q_b[5] <= ram_block11a5.PORTBDATAOUT +q_b[6] <= ram_block11a6.PORTBDATAOUT +q_b[7] <= ram_block11a7.PORTBDATAOUT +q_b[8] <= ram_block11a8.PORTBDATAOUT +q_b[9] <= ram_block11a9.PORTBDATAOUT +q_b[10] <= ram_block11a10.PORTBDATAOUT +q_b[11] <= ram_block11a11.PORTBDATAOUT +q_b[12] <= ram_block11a12.PORTBDATAOUT +q_b[13] <= ram_block11a13.PORTBDATAOUT +q_b[14] <= ram_block11a14.PORTBDATAOUT +q_b[15] <= ram_block11a15.PORTBDATAOUT +wren_a => ram_block11a0.PORTAWE +wren_a => ram_block11a0.ENA0 +wren_a => ram_block11a1.PORTAWE +wren_a => ram_block11a1.ENA0 +wren_a => ram_block11a2.PORTAWE +wren_a => ram_block11a2.ENA0 +wren_a => ram_block11a3.PORTAWE +wren_a => ram_block11a3.ENA0 +wren_a => ram_block11a4.PORTAWE +wren_a => ram_block11a4.ENA0 +wren_a => ram_block11a5.PORTAWE +wren_a => ram_block11a5.ENA0 +wren_a => ram_block11a6.PORTAWE +wren_a => ram_block11a6.ENA0 +wren_a => ram_block11a7.PORTAWE +wren_a => ram_block11a7.ENA0 +wren_a => ram_block11a8.PORTAWE +wren_a => ram_block11a8.ENA0 +wren_a => ram_block11a9.PORTAWE +wren_a => ram_block11a9.ENA0 +wren_a => ram_block11a10.PORTAWE +wren_a => ram_block11a10.ENA0 +wren_a => ram_block11a11.PORTAWE +wren_a => ram_block11a11.ENA0 +wren_a => ram_block11a12.PORTAWE +wren_a => ram_block11a12.ENA0 +wren_a => ram_block11a13.PORTAWE +wren_a => ram_block11a13.ENA0 +wren_a => ram_block11a14.PORTAWE +wren_a => ram_block11a14.ENA0 +wren_a => ram_block11a15.PORTAWE +wren_a => ram_block11a15.ENA0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp +clock => dffe12a[9].CLK +clock => dffe12a[8].CLK +clock => dffe12a[7].CLK +clock => dffe12a[6].CLK +clock => dffe12a[5].CLK +clock => dffe12a[4].CLK +clock => dffe12a[3].CLK +clock => dffe12a[2].CLK +clock => dffe12a[1].CLK +clock => dffe12a[0].CLK +clrn => dffe12a[9].ACLR +clrn => dffe12a[8].ACLR +clrn => dffe12a[7].ACLR +clrn => dffe12a[6].ACLR +clrn => dffe12a[5].ACLR +clrn => dffe12a[4].ACLR +clrn => dffe12a[3].ACLR +clrn => dffe12a[2].ACLR +clrn => dffe12a[1].ACLR +clrn => dffe12a[0].ACLR +d[0] => dffe12a[0].IN0 +d[1] => dffe12a[1].IN0 +d[2] => dffe12a[2].IN0 +d[3] => dffe12a[3].IN0 +d[4] => dffe12a[4].IN0 +d[5] => dffe12a[5].IN0 +d[6] => dffe12a[6].IN0 +d[7] => dffe12a[7].IN0 +d[8] => dffe12a[8].IN0 +d[9] => dffe12a[9].IN0 +q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp +clock => dffe12a[9].CLK +clock => dffe12a[8].CLK +clock => dffe12a[7].CLK +clock => dffe12a[6].CLK +clock => dffe12a[5].CLK +clock => dffe12a[4].CLK +clock => dffe12a[3].CLK +clock => dffe12a[2].CLK +clock => dffe12a[1].CLK +clock => dffe12a[0].CLK +clrn => dffe12a[9].ACLR +clrn => dffe12a[8].ACLR +clrn => dffe12a[7].ACLR +clrn => dffe12a[6].ACLR +clrn => dffe12a[5].ACLR +clrn => dffe12a[4].ACLR +clrn => dffe12a[3].ACLR +clrn => dffe12a[2].ACLR +clrn => dffe12a[1].ACLR +clrn => dffe12a[0].ACLR +d[0] => dffe12a[0].IN0 +d[1] => dffe12a[1].IN0 +d[2] => dffe12a[2].IN0 +d[3] => dffe12a[3].IN0 +d[4] => dffe12a[4].IN0 +d[5] => dffe12a[5].IN0 +d[6] => dffe12a[6].IN0 +d[7] => dffe12a[7].IN0 +d[8] => dffe12a[8].IN0 +d[9] => dffe12a[9].IN0 +q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp +clock => dffpipe_pe9:dffpipe13.clock +clrn => dffpipe_pe9:dffpipe13.clrn +d[0] => dffpipe_pe9:dffpipe13.d[0] +d[1] => dffpipe_pe9:dffpipe13.d[1] +d[2] => dffpipe_pe9:dffpipe13.d[2] +d[3] => dffpipe_pe9:dffpipe13.d[3] +d[4] => dffpipe_pe9:dffpipe13.d[4] +d[5] => dffpipe_pe9:dffpipe13.d[5] +d[6] => dffpipe_pe9:dffpipe13.d[6] +d[7] => dffpipe_pe9:dffpipe13.d[7] +d[8] => dffpipe_pe9:dffpipe13.d[8] +d[9] => dffpipe_pe9:dffpipe13.d[9] +q[0] <= dffpipe_pe9:dffpipe13.q[0] +q[1] <= dffpipe_pe9:dffpipe13.q[1] +q[2] <= dffpipe_pe9:dffpipe13.q[2] +q[3] <= dffpipe_pe9:dffpipe13.q[3] +q[4] <= dffpipe_pe9:dffpipe13.q[4] +q[5] <= dffpipe_pe9:dffpipe13.q[5] +q[6] <= dffpipe_pe9:dffpipe13.q[6] +q[7] <= dffpipe_pe9:dffpipe13.q[7] +q[8] <= dffpipe_pe9:dffpipe13.q[8] +q[9] <= dffpipe_pe9:dffpipe13.q[9] + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 +clock => dffe14a[9].CLK +clock => dffe14a[8].CLK +clock => dffe14a[7].CLK +clock => dffe14a[6].CLK +clock => dffe14a[5].CLK +clock => dffe14a[4].CLK +clock => dffe14a[3].CLK +clock => dffe14a[2].CLK +clock => dffe14a[1].CLK +clock => dffe14a[0].CLK +clock => dffe15a[9].CLK +clock => dffe15a[8].CLK +clock => dffe15a[7].CLK +clock => dffe15a[6].CLK +clock => dffe15a[5].CLK +clock => dffe15a[4].CLK +clock => dffe15a[3].CLK +clock => dffe15a[2].CLK +clock => dffe15a[1].CLK +clock => dffe15a[0].CLK +clrn => dffe14a[9].ACLR +clrn => dffe14a[8].ACLR +clrn => dffe14a[7].ACLR +clrn => dffe14a[6].ACLR +clrn => dffe14a[5].ACLR +clrn => dffe14a[4].ACLR +clrn => dffe14a[3].ACLR +clrn => dffe14a[2].ACLR +clrn => dffe14a[1].ACLR +clrn => dffe14a[0].ACLR +clrn => dffe15a[9].ACLR +clrn => dffe15a[8].ACLR +clrn => dffe15a[7].ACLR +clrn => dffe15a[6].ACLR +clrn => dffe15a[5].ACLR +clrn => dffe15a[4].ACLR +clrn => dffe15a[3].ACLR +clrn => dffe15a[2].ACLR +clrn => dffe15a[1].ACLR +clrn => dffe15a[0].ACLR +d[0] => dffe14a[0].IN0 +d[1] => dffe14a[1].IN0 +d[2] => dffe14a[2].IN0 +d[3] => dffe14a[3].IN0 +d[4] => dffe14a[4].IN0 +d[5] => dffe14a[5].IN0 +d[6] => dffe14a[6].IN0 +d[7] => dffe14a[7].IN0 +d[8] => dffe14a[8].IN0 +d[9] => dffe14a[9].IN0 +q[0] <= dffe15a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe15a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe15a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe15a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe15a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe15a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe15a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe15a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe15a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe15a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp +clock => dffe12a[9].CLK +clock => dffe12a[8].CLK +clock => dffe12a[7].CLK +clock => dffe12a[6].CLK +clock => dffe12a[5].CLK +clock => dffe12a[4].CLK +clock => dffe12a[3].CLK +clock => dffe12a[2].CLK +clock => dffe12a[1].CLK +clock => dffe12a[0].CLK +clrn => dffe12a[9].ACLR +clrn => dffe12a[8].ACLR +clrn => dffe12a[7].ACLR +clrn => dffe12a[6].ACLR +clrn => dffe12a[5].ACLR +clrn => dffe12a[4].ACLR +clrn => dffe12a[3].ACLR +clrn => dffe12a[2].ACLR +clrn => dffe12a[1].ACLR +clrn => dffe12a[0].ACLR +d[0] => dffe12a[0].IN0 +d[1] => dffe12a[1].IN0 +d[2] => dffe12a[2].IN0 +d[3] => dffe12a[3].IN0 +d[4] => dffe12a[4].IN0 +d[5] => dffe12a[5].IN0 +d[6] => dffe12a[6].IN0 +d[7] => dffe12a[7].IN0 +d[8] => dffe12a[8].IN0 +d[9] => dffe12a[9].IN0 +q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp +clock => dffe12a[9].CLK +clock => dffe12a[8].CLK +clock => dffe12a[7].CLK +clock => dffe12a[6].CLK +clock => dffe12a[5].CLK +clock => dffe12a[4].CLK +clock => dffe12a[3].CLK +clock => dffe12a[2].CLK +clock => dffe12a[1].CLK +clock => dffe12a[0].CLK +clrn => dffe12a[9].ACLR +clrn => dffe12a[8].ACLR +clrn => dffe12a[7].ACLR +clrn => dffe12a[6].ACLR +clrn => dffe12a[5].ACLR +clrn => dffe12a[4].ACLR +clrn => dffe12a[3].ACLR +clrn => dffe12a[2].ACLR +clrn => dffe12a[1].ACLR +clrn => dffe12a[0].ACLR +d[0] => dffe12a[0].IN0 +d[1] => dffe12a[1].IN0 +d[2] => dffe12a[2].IN0 +d[3] => dffe12a[3].IN0 +d[4] => dffe12a[4].IN0 +d[5] => dffe12a[5].IN0 +d[6] => dffe12a[6].IN0 +d[7] => dffe12a[7].IN0 +d[8] => dffe12a[8].IN0 +d[9] => dffe12a[9].IN0 +q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp +clock => dffpipe_qe9:dffpipe16.clock +clrn => dffpipe_qe9:dffpipe16.clrn +d[0] => dffpipe_qe9:dffpipe16.d[0] +d[1] => dffpipe_qe9:dffpipe16.d[1] +d[2] => dffpipe_qe9:dffpipe16.d[2] +d[3] => dffpipe_qe9:dffpipe16.d[3] +d[4] => dffpipe_qe9:dffpipe16.d[4] +d[5] => dffpipe_qe9:dffpipe16.d[5] +d[6] => dffpipe_qe9:dffpipe16.d[6] +d[7] => dffpipe_qe9:dffpipe16.d[7] +d[8] => dffpipe_qe9:dffpipe16.d[8] +d[9] => dffpipe_qe9:dffpipe16.d[9] +q[0] <= dffpipe_qe9:dffpipe16.q[0] +q[1] <= dffpipe_qe9:dffpipe16.q[1] +q[2] <= dffpipe_qe9:dffpipe16.q[2] +q[3] <= dffpipe_qe9:dffpipe16.q[3] +q[4] <= dffpipe_qe9:dffpipe16.q[4] +q[5] <= dffpipe_qe9:dffpipe16.q[5] +q[6] <= dffpipe_qe9:dffpipe16.q[6] +q[7] <= dffpipe_qe9:dffpipe16.q[7] +q[8] <= dffpipe_qe9:dffpipe16.q[8] +q[9] <= dffpipe_qe9:dffpipe16.q[9] + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 +clock => dffe17a[9].CLK +clock => dffe17a[8].CLK +clock => dffe17a[7].CLK +clock => dffe17a[6].CLK +clock => dffe17a[5].CLK +clock => dffe17a[4].CLK +clock => dffe17a[3].CLK +clock => dffe17a[2].CLK +clock => dffe17a[1].CLK +clock => dffe17a[0].CLK +clock => dffe18a[9].CLK +clock => dffe18a[8].CLK +clock => dffe18a[7].CLK +clock => dffe18a[6].CLK +clock => dffe18a[5].CLK +clock => dffe18a[4].CLK +clock => dffe18a[3].CLK +clock => dffe18a[2].CLK +clock => dffe18a[1].CLK +clock => dffe18a[0].CLK +clrn => dffe17a[9].ACLR +clrn => dffe17a[8].ACLR +clrn => dffe17a[7].ACLR +clrn => dffe17a[6].ACLR +clrn => dffe17a[5].ACLR +clrn => dffe17a[4].ACLR +clrn => dffe17a[3].ACLR +clrn => dffe17a[2].ACLR +clrn => dffe17a[1].ACLR +clrn => dffe17a[0].ACLR +clrn => dffe18a[9].ACLR +clrn => dffe18a[8].ACLR +clrn => dffe18a[7].ACLR +clrn => dffe18a[6].ACLR +clrn => dffe18a[5].ACLR +clrn => dffe18a[4].ACLR +clrn => dffe18a[3].ACLR +clrn => dffe18a[2].ACLR +clrn => dffe18a[1].ACLR +clrn => dffe18a[0].ACLR +d[0] => dffe17a[0].IN0 +d[1] => dffe17a[1].IN0 +d[2] => dffe17a[2].IN0 +d[3] => dffe17a[3].IN0 +d[4] => dffe17a[4].IN0 +d[5] => dffe17a[5].IN0 +d[6] => dffe17a[6].IN0 +d[7] => dffe17a[7].IN0 +d[8] => dffe17a[8].IN0 +d[9] => dffe17a[9].IN0 +q[0] <= dffe18a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe18a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe18a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe18a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe18a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe18a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe18a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe18a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe18a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe18a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp +aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE +dataa[0] => data_wire[2].IN0 +dataa[1] => data_wire[2].IN0 +dataa[2] => data_wire[3].IN0 +dataa[3] => data_wire[3].IN0 +dataa[4] => data_wire[4].IN0 +dataa[5] => data_wire[4].IN0 +dataa[6] => data_wire[5].IN0 +dataa[7] => data_wire[5].IN0 +dataa[8] => data_wire[6].IN0 +dataa[9] => data_wire[6].IN0 +datab[0] => data_wire[2].IN1 +datab[1] => data_wire[2].IN1 +datab[2] => data_wire[3].IN1 +datab[3] => data_wire[3].IN1 +datab[4] => data_wire[4].IN1 +datab[5] => data_wire[4].IN1 +datab[6] => data_wire[5].IN1 +datab[7] => data_wire[5].IN1 +datab[8] => data_wire[6].IN1 +datab[9] => data_wire[6].IN1 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp +aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE +dataa[0] => data_wire[2].IN0 +dataa[1] => data_wire[2].IN0 +dataa[2] => data_wire[3].IN0 +dataa[3] => data_wire[3].IN0 +dataa[4] => data_wire[4].IN0 +dataa[5] => data_wire[4].IN0 +dataa[6] => data_wire[5].IN0 +dataa[7] => data_wire[5].IN0 +dataa[8] => data_wire[6].IN0 +dataa[9] => data_wire[6].IN0 +datab[0] => data_wire[2].IN1 +datab[1] => data_wire[2].IN1 +datab[2] => data_wire[3].IN1 +datab[3] => data_wire[3].IN1 +datab[4] => data_wire[4].IN1 +datab[5] => data_wire[4].IN1 +datab[6] => data_wire[5].IN1 +datab[7] => data_wire[5].IN1 +datab[8] => data_wire[6].IN1 +datab[9] => data_wire[6].IN1 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2 +aclr => aclr.IN1 +data[0] => data[0].IN1 +data[1] => data[1].IN1 +data[2] => data[2].IN1 +data[3] => data[3].IN1 +data[4] => data[4].IN1 +data[5] => data[5].IN1 +data[6] => data[6].IN1 +data[7] => data[7].IN1 +data[8] => data[8].IN1 +data[9] => data[9].IN1 +data[10] => data[10].IN1 +data[11] => data[11].IN1 +data[12] => data[12].IN1 +data[13] => data[13].IN1 +data[14] => data[14].IN1 +data[15] => data[15].IN1 +rdclk => rdclk.IN1 +rdreq => rdreq.IN1 +wrclk => wrclk.IN1 +wrreq => wrreq.IN1 +q[0] <= dcfifo:dcfifo_component.q +q[1] <= dcfifo:dcfifo_component.q +q[2] <= dcfifo:dcfifo_component.q +q[3] <= dcfifo:dcfifo_component.q +q[4] <= dcfifo:dcfifo_component.q +q[5] <= dcfifo:dcfifo_component.q +q[6] <= dcfifo:dcfifo_component.q +q[7] <= dcfifo:dcfifo_component.q +q[8] <= dcfifo:dcfifo_component.q +q[9] <= dcfifo:dcfifo_component.q +q[10] <= dcfifo:dcfifo_component.q +q[11] <= dcfifo:dcfifo_component.q +q[12] <= dcfifo:dcfifo_component.q +q[13] <= dcfifo:dcfifo_component.q +q[14] <= dcfifo:dcfifo_component.q +q[15] <= dcfifo:dcfifo_component.q +rdempty <= dcfifo:dcfifo_component.rdempty +rdusedw[0] <= dcfifo:dcfifo_component.rdusedw +rdusedw[1] <= dcfifo:dcfifo_component.rdusedw +rdusedw[2] <= dcfifo:dcfifo_component.rdusedw +rdusedw[3] <= dcfifo:dcfifo_component.rdusedw +rdusedw[4] <= dcfifo:dcfifo_component.rdusedw +rdusedw[5] <= dcfifo:dcfifo_component.rdusedw +rdusedw[6] <= dcfifo:dcfifo_component.rdusedw +rdusedw[7] <= dcfifo:dcfifo_component.rdusedw +rdusedw[8] <= dcfifo:dcfifo_component.rdusedw +wrfull <= dcfifo:dcfifo_component.wrfull +wrusedw[0] <= dcfifo:dcfifo_component.wrusedw +wrusedw[1] <= dcfifo:dcfifo_component.wrusedw +wrusedw[2] <= dcfifo:dcfifo_component.wrusedw +wrusedw[3] <= dcfifo:dcfifo_component.wrusedw +wrusedw[4] <= dcfifo:dcfifo_component.wrusedw +wrusedw[5] <= dcfifo:dcfifo_component.wrusedw +wrusedw[6] <= dcfifo:dcfifo_component.wrusedw +wrusedw[7] <= dcfifo:dcfifo_component.wrusedw +wrusedw[8] <= dcfifo:dcfifo_component.wrusedw + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component +data[0] => dcfifo_v5o1:auto_generated.data[0] +data[1] => dcfifo_v5o1:auto_generated.data[1] +data[2] => dcfifo_v5o1:auto_generated.data[2] +data[3] => dcfifo_v5o1:auto_generated.data[3] +data[4] => dcfifo_v5o1:auto_generated.data[4] +data[5] => dcfifo_v5o1:auto_generated.data[5] +data[6] => dcfifo_v5o1:auto_generated.data[6] +data[7] => dcfifo_v5o1:auto_generated.data[7] +data[8] => dcfifo_v5o1:auto_generated.data[8] +data[9] => dcfifo_v5o1:auto_generated.data[9] +data[10] => dcfifo_v5o1:auto_generated.data[10] +data[11] => dcfifo_v5o1:auto_generated.data[11] +data[12] => dcfifo_v5o1:auto_generated.data[12] +data[13] => dcfifo_v5o1:auto_generated.data[13] +data[14] => dcfifo_v5o1:auto_generated.data[14] +data[15] => dcfifo_v5o1:auto_generated.data[15] +q[0] <= dcfifo_v5o1:auto_generated.q[0] +q[1] <= dcfifo_v5o1:auto_generated.q[1] +q[2] <= dcfifo_v5o1:auto_generated.q[2] +q[3] <= dcfifo_v5o1:auto_generated.q[3] +q[4] <= dcfifo_v5o1:auto_generated.q[4] +q[5] <= dcfifo_v5o1:auto_generated.q[5] +q[6] <= dcfifo_v5o1:auto_generated.q[6] +q[7] <= dcfifo_v5o1:auto_generated.q[7] +q[8] <= dcfifo_v5o1:auto_generated.q[8] +q[9] <= dcfifo_v5o1:auto_generated.q[9] +q[10] <= dcfifo_v5o1:auto_generated.q[10] +q[11] <= dcfifo_v5o1:auto_generated.q[11] +q[12] <= dcfifo_v5o1:auto_generated.q[12] +q[13] <= dcfifo_v5o1:auto_generated.q[13] +q[14] <= dcfifo_v5o1:auto_generated.q[14] +q[15] <= dcfifo_v5o1:auto_generated.q[15] +rdclk => dcfifo_v5o1:auto_generated.rdclk +rdreq => dcfifo_v5o1:auto_generated.rdreq +wrclk => dcfifo_v5o1:auto_generated.wrclk +wrreq => dcfifo_v5o1:auto_generated.wrreq +aclr => dcfifo_v5o1:auto_generated.aclr +rdempty <= dcfifo_v5o1:auto_generated.rdempty +rdfull <= <UNC> +wrempty <= <GND> +wrfull <= dcfifo_v5o1:auto_generated.wrfull +rdusedw[0] <= dcfifo_v5o1:auto_generated.rdusedw[0] +rdusedw[1] <= dcfifo_v5o1:auto_generated.rdusedw[1] +rdusedw[2] <= dcfifo_v5o1:auto_generated.rdusedw[2] +rdusedw[3] <= dcfifo_v5o1:auto_generated.rdusedw[3] +rdusedw[4] <= dcfifo_v5o1:auto_generated.rdusedw[4] +rdusedw[5] <= dcfifo_v5o1:auto_generated.rdusedw[5] +rdusedw[6] <= dcfifo_v5o1:auto_generated.rdusedw[6] +rdusedw[7] <= dcfifo_v5o1:auto_generated.rdusedw[7] +rdusedw[8] <= dcfifo_v5o1:auto_generated.rdusedw[8] +wrusedw[0] <= dcfifo_v5o1:auto_generated.wrusedw[0] +wrusedw[1] <= dcfifo_v5o1:auto_generated.wrusedw[1] +wrusedw[2] <= dcfifo_v5o1:auto_generated.wrusedw[2] +wrusedw[3] <= dcfifo_v5o1:auto_generated.wrusedw[3] +wrusedw[4] <= dcfifo_v5o1:auto_generated.wrusedw[4] +wrusedw[5] <= dcfifo_v5o1:auto_generated.wrusedw[5] +wrusedw[6] <= dcfifo_v5o1:auto_generated.wrusedw[6] +wrusedw[7] <= dcfifo_v5o1:auto_generated.wrusedw[7] +wrusedw[8] <= dcfifo_v5o1:auto_generated.wrusedw[8] + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated +aclr => a_graycounter_s57:rdptr_g1p.aclr +aclr => a_graycounter_ojc:wrptr_g1p.aclr +aclr => altsyncram_de51:fifo_ram.aclr1 +aclr => delayed_wrptr_g[9].IN0 +aclr => rdptr_g[9].IN0 +aclr => wrptr_g[9].IN0 +aclr => _.IN0 +aclr => _.IN0 +aclr => _.IN0 +aclr => _.IN0 +aclr => _.IN0 +aclr => _.IN0 +data[0] => altsyncram_de51:fifo_ram.data_a[0] +data[1] => altsyncram_de51:fifo_ram.data_a[1] +data[2] => altsyncram_de51:fifo_ram.data_a[2] +data[3] => altsyncram_de51:fifo_ram.data_a[3] +data[4] => altsyncram_de51:fifo_ram.data_a[4] +data[5] => altsyncram_de51:fifo_ram.data_a[5] +data[6] => altsyncram_de51:fifo_ram.data_a[6] +data[7] => altsyncram_de51:fifo_ram.data_a[7] +data[8] => altsyncram_de51:fifo_ram.data_a[8] +data[9] => altsyncram_de51:fifo_ram.data_a[9] +data[10] => altsyncram_de51:fifo_ram.data_a[10] +data[11] => altsyncram_de51:fifo_ram.data_a[11] +data[12] => altsyncram_de51:fifo_ram.data_a[12] +data[13] => altsyncram_de51:fifo_ram.data_a[13] +data[14] => altsyncram_de51:fifo_ram.data_a[14] +data[15] => altsyncram_de51:fifo_ram.data_a[15] +q[0] <= altsyncram_de51:fifo_ram.q_b[0] +q[1] <= altsyncram_de51:fifo_ram.q_b[1] +q[2] <= altsyncram_de51:fifo_ram.q_b[2] +q[3] <= altsyncram_de51:fifo_ram.q_b[3] +q[4] <= altsyncram_de51:fifo_ram.q_b[4] +q[5] <= altsyncram_de51:fifo_ram.q_b[5] +q[6] <= altsyncram_de51:fifo_ram.q_b[6] +q[7] <= altsyncram_de51:fifo_ram.q_b[7] +q[8] <= altsyncram_de51:fifo_ram.q_b[8] +q[9] <= altsyncram_de51:fifo_ram.q_b[9] +q[10] <= altsyncram_de51:fifo_ram.q_b[10] +q[11] <= altsyncram_de51:fifo_ram.q_b[11] +q[12] <= altsyncram_de51:fifo_ram.q_b[12] +q[13] <= altsyncram_de51:fifo_ram.q_b[13] +q[14] <= altsyncram_de51:fifo_ram.q_b[14] +q[15] <= altsyncram_de51:fifo_ram.q_b[15] +rdclk => a_graycounter_s57:rdptr_g1p.clock +rdclk => altsyncram_de51:fifo_ram.clock1 +rdclk => dffpipe_oe9:rs_brp.clock +rdclk => dffpipe_oe9:rs_bwp.clock +rdclk => alt_synch_pipe_qld:rs_dgwp.clock +rdclk => rdptr_g[9].CLK +rdclk => rdptr_g[8].CLK +rdclk => rdptr_g[7].CLK +rdclk => rdptr_g[6].CLK +rdclk => rdptr_g[5].CLK +rdclk => rdptr_g[4].CLK +rdclk => rdptr_g[3].CLK +rdclk => rdptr_g[2].CLK +rdclk => rdptr_g[1].CLK +rdclk => rdptr_g[0].CLK +rdempty <= int_rdempty.DB_MAX_OUTPUT_PORT_TYPE +rdreq => valid_rdreq.IN0 +rdusedw[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +rdusedw[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE +wrclk => a_graycounter_ojc:wrptr_g1p.clock +wrclk => altsyncram_de51:fifo_ram.clock0 +wrclk => dffpipe_oe9:ws_brp.clock +wrclk => dffpipe_oe9:ws_bwp.clock +wrclk => alt_synch_pipe_rld:ws_dgrp.clock +wrclk => delayed_wrptr_g[9].CLK +wrclk => delayed_wrptr_g[8].CLK +wrclk => delayed_wrptr_g[7].CLK +wrclk => delayed_wrptr_g[6].CLK +wrclk => delayed_wrptr_g[5].CLK +wrclk => delayed_wrptr_g[4].CLK +wrclk => delayed_wrptr_g[3].CLK +wrclk => delayed_wrptr_g[2].CLK +wrclk => delayed_wrptr_g[1].CLK +wrclk => delayed_wrptr_g[0].CLK +wrclk => wrptr_g[9].CLK +wrclk => wrptr_g[8].CLK +wrclk => wrptr_g[7].CLK +wrclk => wrptr_g[6].CLK +wrclk => wrptr_g[5].CLK +wrclk => wrptr_g[4].CLK +wrclk => wrptr_g[3].CLK +wrclk => wrptr_g[2].CLK +wrclk => wrptr_g[1].CLK +wrclk => wrptr_g[0].CLK +wrfull <= int_wrfull.DB_MAX_OUTPUT_PORT_TYPE +wrreq => valid_wrreq.IN0 +wrusedw[0] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[1] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[2] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[3] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[4] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[5] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[6] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[7] <= op_2.DB_MAX_OUTPUT_PORT_TYPE +wrusedw[8] <= op_2.DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin +bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE +bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE +bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE +bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE +bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE +bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE +bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE +bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE +bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE +bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE +gray[0] => xor0.IN0 +gray[1] => xor1.IN0 +gray[2] => xor2.IN0 +gray[3] => xor3.IN0 +gray[4] => xor4.IN0 +gray[5] => xor5.IN0 +gray[6] => xor6.IN0 +gray[7] => xor7.IN0 +gray[8] => xor8.IN1 +gray[9] => bin[9].DATAIN +gray[9] => xor8.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin +bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE +bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE +bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE +bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE +bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE +bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE +bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE +bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE +bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE +bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE +gray[0] => xor0.IN0 +gray[1] => xor1.IN0 +gray[2] => xor2.IN0 +gray[3] => xor3.IN0 +gray[4] => xor4.IN0 +gray[5] => xor5.IN0 +gray[6] => xor6.IN0 +gray[7] => xor7.IN0 +gray[8] => xor8.IN1 +gray[9] => bin[9].DATAIN +gray[9] => xor8.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin +bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE +bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE +bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE +bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE +bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE +bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE +bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE +bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE +bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE +bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE +gray[0] => xor0.IN0 +gray[1] => xor1.IN0 +gray[2] => xor2.IN0 +gray[3] => xor3.IN0 +gray[4] => xor4.IN0 +gray[5] => xor5.IN0 +gray[6] => xor6.IN0 +gray[7] => xor7.IN0 +gray[8] => xor8.IN1 +gray[9] => bin[9].DATAIN +gray[9] => xor8.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin +bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE +bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE +bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE +bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE +bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE +bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE +bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE +bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE +bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE +bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE +gray[0] => xor0.IN0 +gray[1] => xor1.IN0 +gray[2] => xor2.IN0 +gray[3] => xor3.IN0 +gray[4] => xor4.IN0 +gray[5] => xor5.IN0 +gray[6] => xor6.IN0 +gray[7] => xor7.IN0 +gray[8] => xor8.IN1 +gray[9] => bin[9].DATAIN +gray[9] => xor8.IN0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p +aclr => counter5a1.IN0 +aclr => counter5a0.IN0 +aclr => parity6.IN0 +aclr => sub_parity7a[2].IN0 +aclr => sub_parity7a[1].IN0 +aclr => sub_parity7a[0].IN0 +clock => counter5a0.CLK +clock => counter5a1.CLK +clock => counter5a2.CLK +clock => counter5a3.CLK +clock => counter5a4.CLK +clock => counter5a5.CLK +clock => counter5a6.CLK +clock => counter5a7.CLK +clock => counter5a8.CLK +clock => counter5a9.CLK +clock => parity6.CLK +clock => sub_parity7a[2].CLK +clock => sub_parity7a[1].CLK +clock => sub_parity7a[0].CLK +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => cntr_cout[0].IN0 +cnt_en => parity_cout.IN1 +q[0] <= counter5a0.DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter5a1.DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter5a2.DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter5a3.DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter5a4.DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter5a5.DB_MAX_OUTPUT_PORT_TYPE +q[6] <= counter5a6.DB_MAX_OUTPUT_PORT_TYPE +q[7] <= counter5a7.DB_MAX_OUTPUT_PORT_TYPE +q[8] <= counter5a8.DB_MAX_OUTPUT_PORT_TYPE +q[9] <= counter5a9.DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p +aclr => counter8a1.IN0 +aclr => counter8a0.IN0 +aclr => parity9.IN0 +aclr => sub_parity10a[2].IN0 +aclr => sub_parity10a[1].IN0 +aclr => sub_parity10a[0].IN0 +clock => counter8a0.CLK +clock => counter8a1.CLK +clock => counter8a2.CLK +clock => counter8a3.CLK +clock => counter8a4.CLK +clock => counter8a5.CLK +clock => counter8a6.CLK +clock => counter8a7.CLK +clock => counter8a8.CLK +clock => counter8a9.CLK +clock => parity9.CLK +clock => sub_parity10a[2].CLK +clock => sub_parity10a[1].CLK +clock => sub_parity10a[0].CLK +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => _.IN0 +cnt_en => cntr_cout[0].IN0 +cnt_en => parity_cout.IN1 +q[0] <= counter8a0.DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter8a1.DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter8a2.DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter8a3.DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter8a4.DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter8a5.DB_MAX_OUTPUT_PORT_TYPE +q[6] <= counter8a6.DB_MAX_OUTPUT_PORT_TYPE +q[7] <= counter8a7.DB_MAX_OUTPUT_PORT_TYPE +q[8] <= counter8a8.DB_MAX_OUTPUT_PORT_TYPE +q[9] <= counter8a9.DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram +aclr1 => ram_block11a0.CLR1 +aclr1 => ram_block11a1.CLR1 +aclr1 => ram_block11a2.CLR1 +aclr1 => ram_block11a3.CLR1 +aclr1 => ram_block11a4.CLR1 +aclr1 => ram_block11a5.CLR1 +aclr1 => ram_block11a6.CLR1 +aclr1 => ram_block11a7.CLR1 +aclr1 => ram_block11a8.CLR1 +aclr1 => ram_block11a9.CLR1 +aclr1 => ram_block11a10.CLR1 +aclr1 => ram_block11a11.CLR1 +aclr1 => ram_block11a12.CLR1 +aclr1 => ram_block11a13.CLR1 +aclr1 => ram_block11a14.CLR1 +aclr1 => ram_block11a15.CLR1 +address_a[0] => ram_block11a0.PORTAADDR +address_a[0] => ram_block11a1.PORTAADDR +address_a[0] => ram_block11a2.PORTAADDR +address_a[0] => ram_block11a3.PORTAADDR +address_a[0] => ram_block11a4.PORTAADDR +address_a[0] => ram_block11a5.PORTAADDR +address_a[0] => ram_block11a6.PORTAADDR +address_a[0] => ram_block11a7.PORTAADDR +address_a[0] => ram_block11a8.PORTAADDR +address_a[0] => ram_block11a9.PORTAADDR +address_a[0] => ram_block11a10.PORTAADDR +address_a[0] => ram_block11a11.PORTAADDR +address_a[0] => ram_block11a12.PORTAADDR +address_a[0] => ram_block11a13.PORTAADDR +address_a[0] => ram_block11a14.PORTAADDR +address_a[0] => ram_block11a15.PORTAADDR +address_a[1] => ram_block11a0.PORTAADDR1 +address_a[1] => ram_block11a1.PORTAADDR1 +address_a[1] => ram_block11a2.PORTAADDR1 +address_a[1] => ram_block11a3.PORTAADDR1 +address_a[1] => ram_block11a4.PORTAADDR1 +address_a[1] => ram_block11a5.PORTAADDR1 +address_a[1] => ram_block11a6.PORTAADDR1 +address_a[1] => ram_block11a7.PORTAADDR1 +address_a[1] => ram_block11a8.PORTAADDR1 +address_a[1] => ram_block11a9.PORTAADDR1 +address_a[1] => ram_block11a10.PORTAADDR1 +address_a[1] => ram_block11a11.PORTAADDR1 +address_a[1] => ram_block11a12.PORTAADDR1 +address_a[1] => ram_block11a13.PORTAADDR1 +address_a[1] => ram_block11a14.PORTAADDR1 +address_a[1] => ram_block11a15.PORTAADDR1 +address_a[2] => ram_block11a0.PORTAADDR2 +address_a[2] => ram_block11a1.PORTAADDR2 +address_a[2] => ram_block11a2.PORTAADDR2 +address_a[2] => ram_block11a3.PORTAADDR2 +address_a[2] => ram_block11a4.PORTAADDR2 +address_a[2] => ram_block11a5.PORTAADDR2 +address_a[2] => ram_block11a6.PORTAADDR2 +address_a[2] => ram_block11a7.PORTAADDR2 +address_a[2] => ram_block11a8.PORTAADDR2 +address_a[2] => ram_block11a9.PORTAADDR2 +address_a[2] => ram_block11a10.PORTAADDR2 +address_a[2] => ram_block11a11.PORTAADDR2 +address_a[2] => ram_block11a12.PORTAADDR2 +address_a[2] => ram_block11a13.PORTAADDR2 +address_a[2] => ram_block11a14.PORTAADDR2 +address_a[2] => ram_block11a15.PORTAADDR2 +address_a[3] => ram_block11a0.PORTAADDR3 +address_a[3] => ram_block11a1.PORTAADDR3 +address_a[3] => ram_block11a2.PORTAADDR3 +address_a[3] => ram_block11a3.PORTAADDR3 +address_a[3] => ram_block11a4.PORTAADDR3 +address_a[3] => ram_block11a5.PORTAADDR3 +address_a[3] => ram_block11a6.PORTAADDR3 +address_a[3] => ram_block11a7.PORTAADDR3 +address_a[3] => ram_block11a8.PORTAADDR3 +address_a[3] => ram_block11a9.PORTAADDR3 +address_a[3] => ram_block11a10.PORTAADDR3 +address_a[3] => ram_block11a11.PORTAADDR3 +address_a[3] => ram_block11a12.PORTAADDR3 +address_a[3] => ram_block11a13.PORTAADDR3 +address_a[3] => ram_block11a14.PORTAADDR3 +address_a[3] => ram_block11a15.PORTAADDR3 +address_a[4] => ram_block11a0.PORTAADDR4 +address_a[4] => ram_block11a1.PORTAADDR4 +address_a[4] => ram_block11a2.PORTAADDR4 +address_a[4] => ram_block11a3.PORTAADDR4 +address_a[4] => ram_block11a4.PORTAADDR4 +address_a[4] => ram_block11a5.PORTAADDR4 +address_a[4] => ram_block11a6.PORTAADDR4 +address_a[4] => ram_block11a7.PORTAADDR4 +address_a[4] => ram_block11a8.PORTAADDR4 +address_a[4] => ram_block11a9.PORTAADDR4 +address_a[4] => ram_block11a10.PORTAADDR4 +address_a[4] => ram_block11a11.PORTAADDR4 +address_a[4] => ram_block11a12.PORTAADDR4 +address_a[4] => ram_block11a13.PORTAADDR4 +address_a[4] => ram_block11a14.PORTAADDR4 +address_a[4] => ram_block11a15.PORTAADDR4 +address_a[5] => ram_block11a0.PORTAADDR5 +address_a[5] => ram_block11a1.PORTAADDR5 +address_a[5] => ram_block11a2.PORTAADDR5 +address_a[5] => ram_block11a3.PORTAADDR5 +address_a[5] => ram_block11a4.PORTAADDR5 +address_a[5] => ram_block11a5.PORTAADDR5 +address_a[5] => ram_block11a6.PORTAADDR5 +address_a[5] => ram_block11a7.PORTAADDR5 +address_a[5] => ram_block11a8.PORTAADDR5 +address_a[5] => ram_block11a9.PORTAADDR5 +address_a[5] => ram_block11a10.PORTAADDR5 +address_a[5] => ram_block11a11.PORTAADDR5 +address_a[5] => ram_block11a12.PORTAADDR5 +address_a[5] => ram_block11a13.PORTAADDR5 +address_a[5] => ram_block11a14.PORTAADDR5 +address_a[5] => ram_block11a15.PORTAADDR5 +address_a[6] => ram_block11a0.PORTAADDR6 +address_a[6] => ram_block11a1.PORTAADDR6 +address_a[6] => ram_block11a2.PORTAADDR6 +address_a[6] => ram_block11a3.PORTAADDR6 +address_a[6] => ram_block11a4.PORTAADDR6 +address_a[6] => ram_block11a5.PORTAADDR6 +address_a[6] => ram_block11a6.PORTAADDR6 +address_a[6] => ram_block11a7.PORTAADDR6 +address_a[6] => ram_block11a8.PORTAADDR6 +address_a[6] => ram_block11a9.PORTAADDR6 +address_a[6] => ram_block11a10.PORTAADDR6 +address_a[6] => ram_block11a11.PORTAADDR6 +address_a[6] => ram_block11a12.PORTAADDR6 +address_a[6] => ram_block11a13.PORTAADDR6 +address_a[6] => ram_block11a14.PORTAADDR6 +address_a[6] => ram_block11a15.PORTAADDR6 +address_a[7] => ram_block11a0.PORTAADDR7 +address_a[7] => ram_block11a1.PORTAADDR7 +address_a[7] => ram_block11a2.PORTAADDR7 +address_a[7] => ram_block11a3.PORTAADDR7 +address_a[7] => ram_block11a4.PORTAADDR7 +address_a[7] => ram_block11a5.PORTAADDR7 +address_a[7] => ram_block11a6.PORTAADDR7 +address_a[7] => ram_block11a7.PORTAADDR7 +address_a[7] => ram_block11a8.PORTAADDR7 +address_a[7] => ram_block11a9.PORTAADDR7 +address_a[7] => ram_block11a10.PORTAADDR7 +address_a[7] => ram_block11a11.PORTAADDR7 +address_a[7] => ram_block11a12.PORTAADDR7 +address_a[7] => ram_block11a13.PORTAADDR7 +address_a[7] => ram_block11a14.PORTAADDR7 +address_a[7] => ram_block11a15.PORTAADDR7 +address_a[8] => ram_block11a0.PORTAADDR8 +address_a[8] => ram_block11a1.PORTAADDR8 +address_a[8] => ram_block11a2.PORTAADDR8 +address_a[8] => ram_block11a3.PORTAADDR8 +address_a[8] => ram_block11a4.PORTAADDR8 +address_a[8] => ram_block11a5.PORTAADDR8 +address_a[8] => ram_block11a6.PORTAADDR8 +address_a[8] => ram_block11a7.PORTAADDR8 +address_a[8] => ram_block11a8.PORTAADDR8 +address_a[8] => ram_block11a9.PORTAADDR8 +address_a[8] => ram_block11a10.PORTAADDR8 +address_a[8] => ram_block11a11.PORTAADDR8 +address_a[8] => ram_block11a12.PORTAADDR8 +address_a[8] => ram_block11a13.PORTAADDR8 +address_a[8] => ram_block11a14.PORTAADDR8 +address_a[8] => ram_block11a15.PORTAADDR8 +address_b[0] => ram_block11a0.PORTBADDR +address_b[0] => ram_block11a1.PORTBADDR +address_b[0] => ram_block11a2.PORTBADDR +address_b[0] => ram_block11a3.PORTBADDR +address_b[0] => ram_block11a4.PORTBADDR +address_b[0] => ram_block11a5.PORTBADDR +address_b[0] => ram_block11a6.PORTBADDR +address_b[0] => ram_block11a7.PORTBADDR +address_b[0] => ram_block11a8.PORTBADDR +address_b[0] => ram_block11a9.PORTBADDR +address_b[0] => ram_block11a10.PORTBADDR +address_b[0] => ram_block11a11.PORTBADDR +address_b[0] => ram_block11a12.PORTBADDR +address_b[0] => ram_block11a13.PORTBADDR +address_b[0] => ram_block11a14.PORTBADDR +address_b[0] => ram_block11a15.PORTBADDR +address_b[1] => ram_block11a0.PORTBADDR1 +address_b[1] => ram_block11a1.PORTBADDR1 +address_b[1] => ram_block11a2.PORTBADDR1 +address_b[1] => ram_block11a3.PORTBADDR1 +address_b[1] => ram_block11a4.PORTBADDR1 +address_b[1] => ram_block11a5.PORTBADDR1 +address_b[1] => ram_block11a6.PORTBADDR1 +address_b[1] => ram_block11a7.PORTBADDR1 +address_b[1] => ram_block11a8.PORTBADDR1 +address_b[1] => ram_block11a9.PORTBADDR1 +address_b[1] => ram_block11a10.PORTBADDR1 +address_b[1] => ram_block11a11.PORTBADDR1 +address_b[1] => ram_block11a12.PORTBADDR1 +address_b[1] => ram_block11a13.PORTBADDR1 +address_b[1] => ram_block11a14.PORTBADDR1 +address_b[1] => ram_block11a15.PORTBADDR1 +address_b[2] => ram_block11a0.PORTBADDR2 +address_b[2] => ram_block11a1.PORTBADDR2 +address_b[2] => ram_block11a2.PORTBADDR2 +address_b[2] => ram_block11a3.PORTBADDR2 +address_b[2] => ram_block11a4.PORTBADDR2 +address_b[2] => ram_block11a5.PORTBADDR2 +address_b[2] => ram_block11a6.PORTBADDR2 +address_b[2] => ram_block11a7.PORTBADDR2 +address_b[2] => ram_block11a8.PORTBADDR2 +address_b[2] => ram_block11a9.PORTBADDR2 +address_b[2] => ram_block11a10.PORTBADDR2 +address_b[2] => ram_block11a11.PORTBADDR2 +address_b[2] => ram_block11a12.PORTBADDR2 +address_b[2] => ram_block11a13.PORTBADDR2 +address_b[2] => ram_block11a14.PORTBADDR2 +address_b[2] => ram_block11a15.PORTBADDR2 +address_b[3] => ram_block11a0.PORTBADDR3 +address_b[3] => ram_block11a1.PORTBADDR3 +address_b[3] => ram_block11a2.PORTBADDR3 +address_b[3] => ram_block11a3.PORTBADDR3 +address_b[3] => ram_block11a4.PORTBADDR3 +address_b[3] => ram_block11a5.PORTBADDR3 +address_b[3] => ram_block11a6.PORTBADDR3 +address_b[3] => ram_block11a7.PORTBADDR3 +address_b[3] => ram_block11a8.PORTBADDR3 +address_b[3] => ram_block11a9.PORTBADDR3 +address_b[3] => ram_block11a10.PORTBADDR3 +address_b[3] => ram_block11a11.PORTBADDR3 +address_b[3] => ram_block11a12.PORTBADDR3 +address_b[3] => ram_block11a13.PORTBADDR3 +address_b[3] => ram_block11a14.PORTBADDR3 +address_b[3] => ram_block11a15.PORTBADDR3 +address_b[4] => ram_block11a0.PORTBADDR4 +address_b[4] => ram_block11a1.PORTBADDR4 +address_b[4] => ram_block11a2.PORTBADDR4 +address_b[4] => ram_block11a3.PORTBADDR4 +address_b[4] => ram_block11a4.PORTBADDR4 +address_b[4] => ram_block11a5.PORTBADDR4 +address_b[4] => ram_block11a6.PORTBADDR4 +address_b[4] => ram_block11a7.PORTBADDR4 +address_b[4] => ram_block11a8.PORTBADDR4 +address_b[4] => ram_block11a9.PORTBADDR4 +address_b[4] => ram_block11a10.PORTBADDR4 +address_b[4] => ram_block11a11.PORTBADDR4 +address_b[4] => ram_block11a12.PORTBADDR4 +address_b[4] => ram_block11a13.PORTBADDR4 +address_b[4] => ram_block11a14.PORTBADDR4 +address_b[4] => ram_block11a15.PORTBADDR4 +address_b[5] => ram_block11a0.PORTBADDR5 +address_b[5] => ram_block11a1.PORTBADDR5 +address_b[5] => ram_block11a2.PORTBADDR5 +address_b[5] => ram_block11a3.PORTBADDR5 +address_b[5] => ram_block11a4.PORTBADDR5 +address_b[5] => ram_block11a5.PORTBADDR5 +address_b[5] => ram_block11a6.PORTBADDR5 +address_b[5] => ram_block11a7.PORTBADDR5 +address_b[5] => ram_block11a8.PORTBADDR5 +address_b[5] => ram_block11a9.PORTBADDR5 +address_b[5] => ram_block11a10.PORTBADDR5 +address_b[5] => ram_block11a11.PORTBADDR5 +address_b[5] => ram_block11a12.PORTBADDR5 +address_b[5] => ram_block11a13.PORTBADDR5 +address_b[5] => ram_block11a14.PORTBADDR5 +address_b[5] => ram_block11a15.PORTBADDR5 +address_b[6] => ram_block11a0.PORTBADDR6 +address_b[6] => ram_block11a1.PORTBADDR6 +address_b[6] => ram_block11a2.PORTBADDR6 +address_b[6] => ram_block11a3.PORTBADDR6 +address_b[6] => ram_block11a4.PORTBADDR6 +address_b[6] => ram_block11a5.PORTBADDR6 +address_b[6] => ram_block11a6.PORTBADDR6 +address_b[6] => ram_block11a7.PORTBADDR6 +address_b[6] => ram_block11a8.PORTBADDR6 +address_b[6] => ram_block11a9.PORTBADDR6 +address_b[6] => ram_block11a10.PORTBADDR6 +address_b[6] => ram_block11a11.PORTBADDR6 +address_b[6] => ram_block11a12.PORTBADDR6 +address_b[6] => ram_block11a13.PORTBADDR6 +address_b[6] => ram_block11a14.PORTBADDR6 +address_b[6] => ram_block11a15.PORTBADDR6 +address_b[7] => ram_block11a0.PORTBADDR7 +address_b[7] => ram_block11a1.PORTBADDR7 +address_b[7] => ram_block11a2.PORTBADDR7 +address_b[7] => ram_block11a3.PORTBADDR7 +address_b[7] => ram_block11a4.PORTBADDR7 +address_b[7] => ram_block11a5.PORTBADDR7 +address_b[7] => ram_block11a6.PORTBADDR7 +address_b[7] => ram_block11a7.PORTBADDR7 +address_b[7] => ram_block11a8.PORTBADDR7 +address_b[7] => ram_block11a9.PORTBADDR7 +address_b[7] => ram_block11a10.PORTBADDR7 +address_b[7] => ram_block11a11.PORTBADDR7 +address_b[7] => ram_block11a12.PORTBADDR7 +address_b[7] => ram_block11a13.PORTBADDR7 +address_b[7] => ram_block11a14.PORTBADDR7 +address_b[7] => ram_block11a15.PORTBADDR7 +address_b[8] => ram_block11a0.PORTBADDR8 +address_b[8] => ram_block11a1.PORTBADDR8 +address_b[8] => ram_block11a2.PORTBADDR8 +address_b[8] => ram_block11a3.PORTBADDR8 +address_b[8] => ram_block11a4.PORTBADDR8 +address_b[8] => ram_block11a5.PORTBADDR8 +address_b[8] => ram_block11a6.PORTBADDR8 +address_b[8] => ram_block11a7.PORTBADDR8 +address_b[8] => ram_block11a8.PORTBADDR8 +address_b[8] => ram_block11a9.PORTBADDR8 +address_b[8] => ram_block11a10.PORTBADDR8 +address_b[8] => ram_block11a11.PORTBADDR8 +address_b[8] => ram_block11a12.PORTBADDR8 +address_b[8] => ram_block11a13.PORTBADDR8 +address_b[8] => ram_block11a14.PORTBADDR8 +address_b[8] => ram_block11a15.PORTBADDR8 +addressstall_b => ram_block11a0.PORTBADDRSTALL +addressstall_b => ram_block11a1.PORTBADDRSTALL +addressstall_b => ram_block11a2.PORTBADDRSTALL +addressstall_b => ram_block11a3.PORTBADDRSTALL +addressstall_b => ram_block11a4.PORTBADDRSTALL +addressstall_b => ram_block11a5.PORTBADDRSTALL +addressstall_b => ram_block11a6.PORTBADDRSTALL +addressstall_b => ram_block11a7.PORTBADDRSTALL +addressstall_b => ram_block11a8.PORTBADDRSTALL +addressstall_b => ram_block11a9.PORTBADDRSTALL +addressstall_b => ram_block11a10.PORTBADDRSTALL +addressstall_b => ram_block11a11.PORTBADDRSTALL +addressstall_b => ram_block11a12.PORTBADDRSTALL +addressstall_b => ram_block11a13.PORTBADDRSTALL +addressstall_b => ram_block11a14.PORTBADDRSTALL +addressstall_b => ram_block11a15.PORTBADDRSTALL +clock0 => ram_block11a0.CLK0 +clock0 => ram_block11a1.CLK0 +clock0 => ram_block11a2.CLK0 +clock0 => ram_block11a3.CLK0 +clock0 => ram_block11a4.CLK0 +clock0 => ram_block11a5.CLK0 +clock0 => ram_block11a6.CLK0 +clock0 => ram_block11a7.CLK0 +clock0 => ram_block11a8.CLK0 +clock0 => ram_block11a9.CLK0 +clock0 => ram_block11a10.CLK0 +clock0 => ram_block11a11.CLK0 +clock0 => ram_block11a12.CLK0 +clock0 => ram_block11a13.CLK0 +clock0 => ram_block11a14.CLK0 +clock0 => ram_block11a15.CLK0 +clock1 => ram_block11a0.CLK1 +clock1 => ram_block11a1.CLK1 +clock1 => ram_block11a2.CLK1 +clock1 => ram_block11a3.CLK1 +clock1 => ram_block11a4.CLK1 +clock1 => ram_block11a5.CLK1 +clock1 => ram_block11a6.CLK1 +clock1 => ram_block11a7.CLK1 +clock1 => ram_block11a8.CLK1 +clock1 => ram_block11a9.CLK1 +clock1 => ram_block11a10.CLK1 +clock1 => ram_block11a11.CLK1 +clock1 => ram_block11a12.CLK1 +clock1 => ram_block11a13.CLK1 +clock1 => ram_block11a14.CLK1 +clock1 => ram_block11a15.CLK1 +clocken1 => ram_block11a0.ENA1 +clocken1 => ram_block11a1.ENA1 +clocken1 => ram_block11a2.ENA1 +clocken1 => ram_block11a3.ENA1 +clocken1 => ram_block11a4.ENA1 +clocken1 => ram_block11a5.ENA1 +clocken1 => ram_block11a6.ENA1 +clocken1 => ram_block11a7.ENA1 +clocken1 => ram_block11a8.ENA1 +clocken1 => ram_block11a9.ENA1 +clocken1 => ram_block11a10.ENA1 +clocken1 => ram_block11a11.ENA1 +clocken1 => ram_block11a12.ENA1 +clocken1 => ram_block11a13.ENA1 +clocken1 => ram_block11a14.ENA1 +clocken1 => ram_block11a15.ENA1 +data_a[0] => ram_block11a0.PORTADATAIN +data_a[1] => ram_block11a1.PORTADATAIN +data_a[2] => ram_block11a2.PORTADATAIN +data_a[3] => ram_block11a3.PORTADATAIN +data_a[4] => ram_block11a4.PORTADATAIN +data_a[5] => ram_block11a5.PORTADATAIN +data_a[6] => ram_block11a6.PORTADATAIN +data_a[7] => ram_block11a7.PORTADATAIN +data_a[8] => ram_block11a8.PORTADATAIN +data_a[9] => ram_block11a9.PORTADATAIN +data_a[10] => ram_block11a10.PORTADATAIN +data_a[11] => ram_block11a11.PORTADATAIN +data_a[12] => ram_block11a12.PORTADATAIN +data_a[13] => ram_block11a13.PORTADATAIN +data_a[14] => ram_block11a14.PORTADATAIN +data_a[15] => ram_block11a15.PORTADATAIN +q_b[0] <= ram_block11a0.PORTBDATAOUT +q_b[1] <= ram_block11a1.PORTBDATAOUT +q_b[2] <= ram_block11a2.PORTBDATAOUT +q_b[3] <= ram_block11a3.PORTBDATAOUT +q_b[4] <= ram_block11a4.PORTBDATAOUT +q_b[5] <= ram_block11a5.PORTBDATAOUT +q_b[6] <= ram_block11a6.PORTBDATAOUT +q_b[7] <= ram_block11a7.PORTBDATAOUT +q_b[8] <= ram_block11a8.PORTBDATAOUT +q_b[9] <= ram_block11a9.PORTBDATAOUT +q_b[10] <= ram_block11a10.PORTBDATAOUT +q_b[11] <= ram_block11a11.PORTBDATAOUT +q_b[12] <= ram_block11a12.PORTBDATAOUT +q_b[13] <= ram_block11a13.PORTBDATAOUT +q_b[14] <= ram_block11a14.PORTBDATAOUT +q_b[15] <= ram_block11a15.PORTBDATAOUT +wren_a => ram_block11a0.PORTAWE +wren_a => ram_block11a0.ENA0 +wren_a => ram_block11a1.PORTAWE +wren_a => ram_block11a1.ENA0 +wren_a => ram_block11a2.PORTAWE +wren_a => ram_block11a2.ENA0 +wren_a => ram_block11a3.PORTAWE +wren_a => ram_block11a3.ENA0 +wren_a => ram_block11a4.PORTAWE +wren_a => ram_block11a4.ENA0 +wren_a => ram_block11a5.PORTAWE +wren_a => ram_block11a5.ENA0 +wren_a => ram_block11a6.PORTAWE +wren_a => ram_block11a6.ENA0 +wren_a => ram_block11a7.PORTAWE +wren_a => ram_block11a7.ENA0 +wren_a => ram_block11a8.PORTAWE +wren_a => ram_block11a8.ENA0 +wren_a => ram_block11a9.PORTAWE +wren_a => ram_block11a9.ENA0 +wren_a => ram_block11a10.PORTAWE +wren_a => ram_block11a10.ENA0 +wren_a => ram_block11a11.PORTAWE +wren_a => ram_block11a11.ENA0 +wren_a => ram_block11a12.PORTAWE +wren_a => ram_block11a12.ENA0 +wren_a => ram_block11a13.PORTAWE +wren_a => ram_block11a13.ENA0 +wren_a => ram_block11a14.PORTAWE +wren_a => ram_block11a14.ENA0 +wren_a => ram_block11a15.PORTAWE +wren_a => ram_block11a15.ENA0 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp +clock => dffe12a[9].CLK +clock => dffe12a[8].CLK +clock => dffe12a[7].CLK +clock => dffe12a[6].CLK +clock => dffe12a[5].CLK +clock => dffe12a[4].CLK +clock => dffe12a[3].CLK +clock => dffe12a[2].CLK +clock => dffe12a[1].CLK +clock => dffe12a[0].CLK +clrn => dffe12a[9].ACLR +clrn => dffe12a[8].ACLR +clrn => dffe12a[7].ACLR +clrn => dffe12a[6].ACLR +clrn => dffe12a[5].ACLR +clrn => dffe12a[4].ACLR +clrn => dffe12a[3].ACLR +clrn => dffe12a[2].ACLR +clrn => dffe12a[1].ACLR +clrn => dffe12a[0].ACLR +d[0] => dffe12a[0].IN0 +d[1] => dffe12a[1].IN0 +d[2] => dffe12a[2].IN0 +d[3] => dffe12a[3].IN0 +d[4] => dffe12a[4].IN0 +d[5] => dffe12a[5].IN0 +d[6] => dffe12a[6].IN0 +d[7] => dffe12a[7].IN0 +d[8] => dffe12a[8].IN0 +d[9] => dffe12a[9].IN0 +q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp +clock => dffe12a[9].CLK +clock => dffe12a[8].CLK +clock => dffe12a[7].CLK +clock => dffe12a[6].CLK +clock => dffe12a[5].CLK +clock => dffe12a[4].CLK +clock => dffe12a[3].CLK +clock => dffe12a[2].CLK +clock => dffe12a[1].CLK +clock => dffe12a[0].CLK +clrn => dffe12a[9].ACLR +clrn => dffe12a[8].ACLR +clrn => dffe12a[7].ACLR +clrn => dffe12a[6].ACLR +clrn => dffe12a[5].ACLR +clrn => dffe12a[4].ACLR +clrn => dffe12a[3].ACLR +clrn => dffe12a[2].ACLR +clrn => dffe12a[1].ACLR +clrn => dffe12a[0].ACLR +d[0] => dffe12a[0].IN0 +d[1] => dffe12a[1].IN0 +d[2] => dffe12a[2].IN0 +d[3] => dffe12a[3].IN0 +d[4] => dffe12a[4].IN0 +d[5] => dffe12a[5].IN0 +d[6] => dffe12a[6].IN0 +d[7] => dffe12a[7].IN0 +d[8] => dffe12a[8].IN0 +d[9] => dffe12a[9].IN0 +q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp +clock => dffpipe_pe9:dffpipe13.clock +clrn => dffpipe_pe9:dffpipe13.clrn +d[0] => dffpipe_pe9:dffpipe13.d[0] +d[1] => dffpipe_pe9:dffpipe13.d[1] +d[2] => dffpipe_pe9:dffpipe13.d[2] +d[3] => dffpipe_pe9:dffpipe13.d[3] +d[4] => dffpipe_pe9:dffpipe13.d[4] +d[5] => dffpipe_pe9:dffpipe13.d[5] +d[6] => dffpipe_pe9:dffpipe13.d[6] +d[7] => dffpipe_pe9:dffpipe13.d[7] +d[8] => dffpipe_pe9:dffpipe13.d[8] +d[9] => dffpipe_pe9:dffpipe13.d[9] +q[0] <= dffpipe_pe9:dffpipe13.q[0] +q[1] <= dffpipe_pe9:dffpipe13.q[1] +q[2] <= dffpipe_pe9:dffpipe13.q[2] +q[3] <= dffpipe_pe9:dffpipe13.q[3] +q[4] <= dffpipe_pe9:dffpipe13.q[4] +q[5] <= dffpipe_pe9:dffpipe13.q[5] +q[6] <= dffpipe_pe9:dffpipe13.q[6] +q[7] <= dffpipe_pe9:dffpipe13.q[7] +q[8] <= dffpipe_pe9:dffpipe13.q[8] +q[9] <= dffpipe_pe9:dffpipe13.q[9] + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 +clock => dffe14a[9].CLK +clock => dffe14a[8].CLK +clock => dffe14a[7].CLK +clock => dffe14a[6].CLK +clock => dffe14a[5].CLK +clock => dffe14a[4].CLK +clock => dffe14a[3].CLK +clock => dffe14a[2].CLK +clock => dffe14a[1].CLK +clock => dffe14a[0].CLK +clock => dffe15a[9].CLK +clock => dffe15a[8].CLK +clock => dffe15a[7].CLK +clock => dffe15a[6].CLK +clock => dffe15a[5].CLK +clock => dffe15a[4].CLK +clock => dffe15a[3].CLK +clock => dffe15a[2].CLK +clock => dffe15a[1].CLK +clock => dffe15a[0].CLK +clrn => dffe14a[9].ACLR +clrn => dffe14a[8].ACLR +clrn => dffe14a[7].ACLR +clrn => dffe14a[6].ACLR +clrn => dffe14a[5].ACLR +clrn => dffe14a[4].ACLR +clrn => dffe14a[3].ACLR +clrn => dffe14a[2].ACLR +clrn => dffe14a[1].ACLR +clrn => dffe14a[0].ACLR +clrn => dffe15a[9].ACLR +clrn => dffe15a[8].ACLR +clrn => dffe15a[7].ACLR +clrn => dffe15a[6].ACLR +clrn => dffe15a[5].ACLR +clrn => dffe15a[4].ACLR +clrn => dffe15a[3].ACLR +clrn => dffe15a[2].ACLR +clrn => dffe15a[1].ACLR +clrn => dffe15a[0].ACLR +d[0] => dffe14a[0].IN0 +d[1] => dffe14a[1].IN0 +d[2] => dffe14a[2].IN0 +d[3] => dffe14a[3].IN0 +d[4] => dffe14a[4].IN0 +d[5] => dffe14a[5].IN0 +d[6] => dffe14a[6].IN0 +d[7] => dffe14a[7].IN0 +d[8] => dffe14a[8].IN0 +d[9] => dffe14a[9].IN0 +q[0] <= dffe15a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe15a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe15a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe15a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe15a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe15a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe15a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe15a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe15a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe15a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp +clock => dffe12a[9].CLK +clock => dffe12a[8].CLK +clock => dffe12a[7].CLK +clock => dffe12a[6].CLK +clock => dffe12a[5].CLK +clock => dffe12a[4].CLK +clock => dffe12a[3].CLK +clock => dffe12a[2].CLK +clock => dffe12a[1].CLK +clock => dffe12a[0].CLK +clrn => dffe12a[9].ACLR +clrn => dffe12a[8].ACLR +clrn => dffe12a[7].ACLR +clrn => dffe12a[6].ACLR +clrn => dffe12a[5].ACLR +clrn => dffe12a[4].ACLR +clrn => dffe12a[3].ACLR +clrn => dffe12a[2].ACLR +clrn => dffe12a[1].ACLR +clrn => dffe12a[0].ACLR +d[0] => dffe12a[0].IN0 +d[1] => dffe12a[1].IN0 +d[2] => dffe12a[2].IN0 +d[3] => dffe12a[3].IN0 +d[4] => dffe12a[4].IN0 +d[5] => dffe12a[5].IN0 +d[6] => dffe12a[6].IN0 +d[7] => dffe12a[7].IN0 +d[8] => dffe12a[8].IN0 +d[9] => dffe12a[9].IN0 +q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp +clock => dffe12a[9].CLK +clock => dffe12a[8].CLK +clock => dffe12a[7].CLK +clock => dffe12a[6].CLK +clock => dffe12a[5].CLK +clock => dffe12a[4].CLK +clock => dffe12a[3].CLK +clock => dffe12a[2].CLK +clock => dffe12a[1].CLK +clock => dffe12a[0].CLK +clrn => dffe12a[9].ACLR +clrn => dffe12a[8].ACLR +clrn => dffe12a[7].ACLR +clrn => dffe12a[6].ACLR +clrn => dffe12a[5].ACLR +clrn => dffe12a[4].ACLR +clrn => dffe12a[3].ACLR +clrn => dffe12a[2].ACLR +clrn => dffe12a[1].ACLR +clrn => dffe12a[0].ACLR +d[0] => dffe12a[0].IN0 +d[1] => dffe12a[1].IN0 +d[2] => dffe12a[2].IN0 +d[3] => dffe12a[3].IN0 +d[4] => dffe12a[4].IN0 +d[5] => dffe12a[5].IN0 +d[6] => dffe12a[6].IN0 +d[7] => dffe12a[7].IN0 +d[8] => dffe12a[8].IN0 +d[9] => dffe12a[9].IN0 +q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp +clock => dffpipe_qe9:dffpipe16.clock +clrn => dffpipe_qe9:dffpipe16.clrn +d[0] => dffpipe_qe9:dffpipe16.d[0] +d[1] => dffpipe_qe9:dffpipe16.d[1] +d[2] => dffpipe_qe9:dffpipe16.d[2] +d[3] => dffpipe_qe9:dffpipe16.d[3] +d[4] => dffpipe_qe9:dffpipe16.d[4] +d[5] => dffpipe_qe9:dffpipe16.d[5] +d[6] => dffpipe_qe9:dffpipe16.d[6] +d[7] => dffpipe_qe9:dffpipe16.d[7] +d[8] => dffpipe_qe9:dffpipe16.d[8] +d[9] => dffpipe_qe9:dffpipe16.d[9] +q[0] <= dffpipe_qe9:dffpipe16.q[0] +q[1] <= dffpipe_qe9:dffpipe16.q[1] +q[2] <= dffpipe_qe9:dffpipe16.q[2] +q[3] <= dffpipe_qe9:dffpipe16.q[3] +q[4] <= dffpipe_qe9:dffpipe16.q[4] +q[5] <= dffpipe_qe9:dffpipe16.q[5] +q[6] <= dffpipe_qe9:dffpipe16.q[6] +q[7] <= dffpipe_qe9:dffpipe16.q[7] +q[8] <= dffpipe_qe9:dffpipe16.q[8] +q[9] <= dffpipe_qe9:dffpipe16.q[9] + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 +clock => dffe17a[9].CLK +clock => dffe17a[8].CLK +clock => dffe17a[7].CLK +clock => dffe17a[6].CLK +clock => dffe17a[5].CLK +clock => dffe17a[4].CLK +clock => dffe17a[3].CLK +clock => dffe17a[2].CLK +clock => dffe17a[1].CLK +clock => dffe17a[0].CLK +clock => dffe18a[9].CLK +clock => dffe18a[8].CLK +clock => dffe18a[7].CLK +clock => dffe18a[6].CLK +clock => dffe18a[5].CLK +clock => dffe18a[4].CLK +clock => dffe18a[3].CLK +clock => dffe18a[2].CLK +clock => dffe18a[1].CLK +clock => dffe18a[0].CLK +clrn => dffe17a[9].ACLR +clrn => dffe17a[8].ACLR +clrn => dffe17a[7].ACLR +clrn => dffe17a[6].ACLR +clrn => dffe17a[5].ACLR +clrn => dffe17a[4].ACLR +clrn => dffe17a[3].ACLR +clrn => dffe17a[2].ACLR +clrn => dffe17a[1].ACLR +clrn => dffe17a[0].ACLR +clrn => dffe18a[9].ACLR +clrn => dffe18a[8].ACLR +clrn => dffe18a[7].ACLR +clrn => dffe18a[6].ACLR +clrn => dffe18a[5].ACLR +clrn => dffe18a[4].ACLR +clrn => dffe18a[3].ACLR +clrn => dffe18a[2].ACLR +clrn => dffe18a[1].ACLR +clrn => dffe18a[0].ACLR +d[0] => dffe17a[0].IN0 +d[1] => dffe17a[1].IN0 +d[2] => dffe17a[2].IN0 +d[3] => dffe17a[3].IN0 +d[4] => dffe17a[4].IN0 +d[5] => dffe17a[5].IN0 +d[6] => dffe17a[6].IN0 +d[7] => dffe17a[7].IN0 +d[8] => dffe17a[8].IN0 +d[9] => dffe17a[9].IN0 +q[0] <= dffe18a[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= dffe18a[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= dffe18a[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= dffe18a[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= dffe18a[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= dffe18a[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= dffe18a[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= dffe18a[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= dffe18a[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= dffe18a[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp +aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE +dataa[0] => data_wire[2].IN0 +dataa[1] => data_wire[2].IN0 +dataa[2] => data_wire[3].IN0 +dataa[3] => data_wire[3].IN0 +dataa[4] => data_wire[4].IN0 +dataa[5] => data_wire[4].IN0 +dataa[6] => data_wire[5].IN0 +dataa[7] => data_wire[5].IN0 +dataa[8] => data_wire[6].IN0 +dataa[9] => data_wire[6].IN0 +datab[0] => data_wire[2].IN1 +datab[1] => data_wire[2].IN1 +datab[2] => data_wire[3].IN1 +datab[3] => data_wire[3].IN1 +datab[4] => data_wire[4].IN1 +datab[5] => data_wire[4].IN1 +datab[6] => data_wire[5].IN1 +datab[7] => data_wire[5].IN1 +datab[8] => data_wire[6].IN1 +datab[9] => data_wire[6].IN1 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp +aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE +dataa[0] => data_wire[2].IN0 +dataa[1] => data_wire[2].IN0 +dataa[2] => data_wire[3].IN0 +dataa[3] => data_wire[3].IN0 +dataa[4] => data_wire[4].IN0 +dataa[5] => data_wire[4].IN0 +dataa[6] => data_wire[5].IN0 +dataa[7] => data_wire[5].IN0 +dataa[8] => data_wire[6].IN0 +dataa[9] => data_wire[6].IN0 +datab[0] => data_wire[2].IN1 +datab[1] => data_wire[2].IN1 +datab[2] => data_wire[3].IN1 +datab[3] => data_wire[3].IN1 +datab[4] => data_wire[4].IN1 +datab[5] => data_wire[4].IN1 +datab[6] => data_wire[5].IN1 +datab[7] => data_wire[5].IN1 +datab[8] => data_wire[6].IN1 +datab[9] => data_wire[6].IN1 + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8 +iCLK => mI2C_CLK_DIV[0].CLK +iCLK => mI2C_CLK_DIV[1].CLK +iCLK => mI2C_CLK_DIV[2].CLK +iCLK => mI2C_CLK_DIV[3].CLK +iCLK => mI2C_CLK_DIV[4].CLK +iCLK => mI2C_CLK_DIV[5].CLK +iCLK => mI2C_CLK_DIV[6].CLK +iCLK => mI2C_CLK_DIV[7].CLK +iCLK => mI2C_CLK_DIV[8].CLK +iCLK => mI2C_CLK_DIV[9].CLK +iCLK => mI2C_CLK_DIV[10].CLK +iCLK => mI2C_CLK_DIV[11].CLK +iCLK => mI2C_CLK_DIV[12].CLK +iCLK => mI2C_CLK_DIV[13].CLK +iCLK => mI2C_CLK_DIV[14].CLK +iCLK => mI2C_CLK_DIV[15].CLK +iCLK => mI2C_CTRL_CLK.CLK +iCLK => combo_cnt[0].CLK +iCLK => combo_cnt[1].CLK +iCLK => combo_cnt[2].CLK +iCLK => combo_cnt[3].CLK +iCLK => combo_cnt[4].CLK +iCLK => combo_cnt[5].CLK +iCLK => combo_cnt[6].CLK +iCLK => combo_cnt[7].CLK +iCLK => combo_cnt[8].CLK +iCLK => combo_cnt[9].CLK +iCLK => combo_cnt[10].CLK +iCLK => combo_cnt[11].CLK +iCLK => combo_cnt[12].CLK +iCLK => combo_cnt[13].CLK +iCLK => combo_cnt[14].CLK +iCLK => combo_cnt[15].CLK +iCLK => combo_cnt[16].CLK +iCLK => combo_cnt[17].CLK +iCLK => combo_cnt[18].CLK +iCLK => combo_cnt[19].CLK +iCLK => combo_cnt[20].CLK +iCLK => combo_cnt[21].CLK +iCLK => combo_cnt[22].CLK +iCLK => combo_cnt[23].CLK +iCLK => combo_cnt[24].CLK +iCLK => sensor_exposure[0].CLK +iCLK => sensor_exposure[1].CLK +iCLK => sensor_exposure[2].CLK +iCLK => sensor_exposure[3].CLK +iCLK => sensor_exposure[4].CLK +iCLK => sensor_exposure[5].CLK +iCLK => sensor_exposure[6].CLK +iCLK => sensor_exposure[7].CLK +iCLK => sensor_exposure[8].CLK +iCLK => sensor_exposure[9].CLK +iCLK => sensor_exposure[10].CLK +iCLK => sensor_exposure[11].CLK +iCLK => sensor_exposure[12].CLK +iCLK => sensor_exposure[13].CLK +iCLK => sensor_exposure[14].CLK +iCLK => sensor_exposure[15].CLK +iCLK => iexposure_adj_delay[0].CLK +iCLK => iexposure_adj_delay[1].CLK +iCLK => iexposure_adj_delay[2].CLK +iCLK => iexposure_adj_delay[3].CLK +iRST_N => i2c_reset.IN1 +iRST_N => combo_cnt[0].ACLR +iRST_N => combo_cnt[1].ACLR +iRST_N => combo_cnt[2].ACLR +iRST_N => combo_cnt[3].ACLR +iRST_N => combo_cnt[4].ACLR +iRST_N => combo_cnt[5].ACLR +iRST_N => combo_cnt[6].ACLR +iRST_N => combo_cnt[7].ACLR +iRST_N => combo_cnt[8].ACLR +iRST_N => combo_cnt[9].ACLR +iRST_N => combo_cnt[10].ACLR +iRST_N => combo_cnt[11].ACLR +iRST_N => combo_cnt[12].ACLR +iRST_N => combo_cnt[13].ACLR +iRST_N => combo_cnt[14].ACLR +iRST_N => combo_cnt[15].ACLR +iRST_N => combo_cnt[16].ACLR +iRST_N => combo_cnt[17].ACLR +iRST_N => combo_cnt[18].ACLR +iRST_N => combo_cnt[19].ACLR +iRST_N => combo_cnt[20].ACLR +iRST_N => combo_cnt[21].ACLR +iRST_N => combo_cnt[22].ACLR +iRST_N => combo_cnt[23].ACLR +iRST_N => combo_cnt[24].ACLR +iRST_N => sensor_exposure[0].ACLR +iRST_N => sensor_exposure[1].ACLR +iRST_N => sensor_exposure[2].ACLR +iRST_N => sensor_exposure[3].ACLR +iRST_N => sensor_exposure[4].ACLR +iRST_N => sensor_exposure[5].ACLR +iRST_N => sensor_exposure[6].PRESET +iRST_N => sensor_exposure[7].PRESET +iRST_N => sensor_exposure[8].PRESET +iRST_N => sensor_exposure[9].PRESET +iRST_N => sensor_exposure[10].PRESET +iRST_N => sensor_exposure[11].ACLR +iRST_N => sensor_exposure[12].ACLR +iRST_N => sensor_exposure[13].ACLR +iRST_N => sensor_exposure[14].ACLR +iRST_N => sensor_exposure[15].ACLR +iRST_N => iexposure_adj_delay[0].ACLR +iRST_N => iexposure_adj_delay[1].ACLR +iRST_N => iexposure_adj_delay[2].ACLR +iRST_N => iexposure_adj_delay[3].ACLR +iUART_CTRL => ~NO_FANOUT~ +iZOOM_MODE_SW => Mux18.IN69 +iZOOM_MODE_SW => Mux19.IN66 +iZOOM_MODE_SW => Mux21.IN69 +iZOOM_MODE_SW => Mux22.IN69 +iZOOM_MODE_SW => Mux19.IN67 +iZOOM_MODE_SW => Mux13.IN68 +iZOOM_MODE_SW => Mux16.IN69 +iZOOM_MODE_SW => Mux17.IN69 +iZOOM_MODE_SW => Mux12.IN69 +iZOOM_MODE_SW => Mux13.IN69 +iZOOM_MODE_SW => Mux15.IN69 +iZOOM_MODE_SW => Mux19.IN68 +iZOOM_MODE_SW => Mux23.IN68 +iZOOM_MODE_SW => Mux19.IN69 +iZOOM_MODE_SW => Mux23.IN69 +iEXPOSURE_ADJ => iexposure_adj_delay[0].DATAIN +iEXPOSURE_ADJ => Equal0.IN0 +iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT +iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT +iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT +iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT +iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT +iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT +iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT +iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT +iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT +iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT +iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT +iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT +iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT +iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT +iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT +iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT +I2C_SCLK <= I2C_Controller:u0.I2C_SCLK +I2C_SDAT <> I2C_Controller:u0.I2C_SDAT + + +|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0 +CLOCK => SD[0].CLK +CLOCK => SD[1].CLK +CLOCK => SD[2].CLK +CLOCK => SD[3].CLK +CLOCK => SD[4].CLK +CLOCK => SD[5].CLK +CLOCK => SD[6].CLK +CLOCK => SD[7].CLK +CLOCK => SD[8].CLK +CLOCK => SD[9].CLK +CLOCK => SD[10].CLK +CLOCK => SD[11].CLK +CLOCK => SD[12].CLK +CLOCK => SD[13].CLK +CLOCK => SD[14].CLK +CLOCK => SD[15].CLK +CLOCK => SD[16].CLK +CLOCK => SD[17].CLK +CLOCK => SD[18].CLK +CLOCK => SD[19].CLK +CLOCK => SD[20].CLK +CLOCK => SD[21].CLK +CLOCK => SD[22].CLK +CLOCK => SD[23].CLK +CLOCK => SD[24].CLK +CLOCK => SD[25].CLK +CLOCK => SD[26].CLK +CLOCK => SD[27].CLK +CLOCK => SD[28].CLK +CLOCK => SD[29].CLK +CLOCK => SD[30].CLK +CLOCK => SD[31].CLK +CLOCK => END~reg0.CLK +CLOCK => ACK4.CLK +CLOCK => ACK3.CLK +CLOCK => ACK2.CLK +CLOCK => ACK1.CLK +CLOCK => SDO.CLK +CLOCK => SCLK.CLK +CLOCK => SD_COUNTER[0].CLK +CLOCK => SD_COUNTER[1].CLK +CLOCK => SD_COUNTER[2].CLK +CLOCK => SD_COUNTER[3].CLK +CLOCK => SD_COUNTER[4].CLK +CLOCK => SD_COUNTER[5].CLK +CLOCK => SD_COUNTER[6].CLK +CLOCK => comb.DATAB +I2C_SCLK <= comb.DB_MAX_OUTPUT_PORT_TYPE +I2C_SDAT <> I2C_SDAT +I2C_DATA[0] => SD.DATAB +I2C_DATA[1] => SD.DATAB +I2C_DATA[2] => SD.DATAB +I2C_DATA[3] => SD.DATAB +I2C_DATA[4] => SD.DATAB +I2C_DATA[5] => SD.DATAB +I2C_DATA[6] => SD.DATAB +I2C_DATA[7] => SD.DATAB +I2C_DATA[8] => SD.DATAB +I2C_DATA[9] => SD.DATAB +I2C_DATA[10] => SD.DATAB +I2C_DATA[11] => SD.DATAB +I2C_DATA[12] => SD.DATAB +I2C_DATA[13] => SD.DATAB +I2C_DATA[14] => SD.DATAB +I2C_DATA[15] => SD.DATAB +I2C_DATA[16] => SD.DATAB +I2C_DATA[17] => SD.DATAB +I2C_DATA[18] => SD.DATAB +I2C_DATA[19] => SD.DATAB +I2C_DATA[20] => SD.DATAB +I2C_DATA[21] => SD.DATAB +I2C_DATA[22] => SD.DATAB +I2C_DATA[23] => SD.DATAB +I2C_DATA[24] => SD.DATAB +I2C_DATA[25] => SD.DATAB +I2C_DATA[26] => SD.DATAB +I2C_DATA[27] => SD.DATAB +I2C_DATA[28] => SD.DATAB +I2C_DATA[29] => SD.DATAB +I2C_DATA[30] => SD.DATAB +I2C_DATA[31] => SD.DATAB +GO => SD_COUNTER.OUTPUTSELECT +GO => SD_COUNTER.OUTPUTSELECT +GO => SD_COUNTER.OUTPUTSELECT +GO => SD_COUNTER.OUTPUTSELECT +GO => SD_COUNTER.OUTPUTSELECT +GO => SD_COUNTER.OUTPUTSELECT +GO => SD_COUNTER.OUTPUTSELECT +END <= END~reg0.DB_MAX_OUTPUT_PORT_TYPE +ACK <= comb.DB_MAX_OUTPUT_PORT_TYPE +RESET => END~reg0.PRESET +RESET => ACK4.ACLR +RESET => ACK3.ACLR +RESET => ACK2.ACLR +RESET => ACK1.ACLR +RESET => SDO.PRESET +RESET => SCLK.PRESET +RESET => SD_COUNTER[0].PRESET +RESET => SD_COUNTER[1].PRESET +RESET => SD_COUNTER[2].PRESET +RESET => SD_COUNTER[3].PRESET +RESET => SD_COUNTER[4].PRESET +RESET => SD_COUNTER[5].PRESET +RESET => SD_COUNTER[6].ACLR +RESET => SD[0].ENA +RESET => SD[31].ENA +RESET => SD[30].ENA +RESET => SD[29].ENA +RESET => SD[28].ENA +RESET => SD[27].ENA +RESET => SD[26].ENA +RESET => SD[25].ENA +RESET => SD[24].ENA +RESET => SD[23].ENA +RESET => SD[22].ENA +RESET => SD[21].ENA +RESET => SD[20].ENA +RESET => SD[19].ENA +RESET => SD[18].ENA +RESET => SD[17].ENA +RESET => SD[16].ENA +RESET => SD[15].ENA +RESET => SD[14].ENA +RESET => SD[13].ENA +RESET => SD[12].ENA +RESET => SD[11].ENA +RESET => SD[10].ENA +RESET => SD[9].ENA +RESET => SD[8].ENA +RESET => SD[7].ENA +RESET => SD[6].ENA +RESET => SD[5].ENA +RESET => SD[4].ENA +RESET => SD[3].ENA +RESET => SD[2].ENA +RESET => SD[1].ENA + + +|TOP_DE0_CAMERA_MOUSE|ps2:inst6 +iSTART => always2.IN1 +iRST_n => y_latch[0].ACLR +iRST_n => y_latch[1].ACLR +iRST_n => y_latch[2].ACLR +iRST_n => y_latch[3].ACLR +iRST_n => y_latch[4].ACLR +iRST_n => y_latch[5].ACLR +iRST_n => y_latch[6].ACLR +iRST_n => y_latch[7].ACLR +iRST_n => x_latch[0].ACLR +iRST_n => x_latch[1].ACLR +iRST_n => x_latch[2].ACLR +iRST_n => x_latch[3].ACLR +iRST_n => x_latch[4].ACLR +iRST_n => x_latch[5].ACLR +iRST_n => x_latch[6].ACLR +iRST_n => x_latch[7].ACLR +iRST_n => midlatch.ACLR +iRST_n => riglatch.ACLR +iRST_n => leflatch.ACLR +iRST_n => cur_state~3.DATAIN +iCLK_50 => clk_div[0].CLK +iCLK_50 => clk_div[1].CLK +iCLK_50 => clk_div[2].CLK +iCLK_50 => clk_div[3].CLK +iCLK_50 => clk_div[4].CLK +iCLK_50 => clk_div[5].CLK +iCLK_50 => clk_div[6].CLK +iCLK_50 => clk_div[7].CLK +iCLK_50 => clk_div[8].CLK +PS2_CLK <> PS2_CLK +PS2_DAT <> PS2_DAT +oLEFBUT <= leflatch.DB_MAX_OUTPUT_PORT_TYPE +oRIGBUT <= riglatch.DB_MAX_OUTPUT_PORT_TYPE +oMIDBUT <= midlatch.DB_MAX_OUTPUT_PORT_TYPE +oX[0] <= x_latch[0].DB_MAX_OUTPUT_PORT_TYPE +oX[1] <= x_latch[1].DB_MAX_OUTPUT_PORT_TYPE +oX[2] <= x_latch[2].DB_MAX_OUTPUT_PORT_TYPE +oX[3] <= x_latch[3].DB_MAX_OUTPUT_PORT_TYPE +oX[4] <= x_latch[4].DB_MAX_OUTPUT_PORT_TYPE +oX[5] <= x_latch[5].DB_MAX_OUTPUT_PORT_TYPE +oX[6] <= x_latch[6].DB_MAX_OUTPUT_PORT_TYPE +oX[7] <= x_latch[7].DB_MAX_OUTPUT_PORT_TYPE +oY[0] <= y_latch[0].DB_MAX_OUTPUT_PORT_TYPE +oY[1] <= y_latch[1].DB_MAX_OUTPUT_PORT_TYPE +oY[2] <= y_latch[2].DB_MAX_OUTPUT_PORT_TYPE +oY[3] <= y_latch[3].DB_MAX_OUTPUT_PORT_TYPE +oY[4] <= y_latch[4].DB_MAX_OUTPUT_PORT_TYPE +oY[5] <= y_latch[5].DB_MAX_OUTPUT_PORT_TYPE +oY[6] <= y_latch[6].DB_MAX_OUTPUT_PORT_TYPE +oY[7] <= y_latch[7].DB_MAX_OUTPUT_PORT_TYPE +oX_MOV1[0] <= SEG7_LUT:U1.oSEG +oX_MOV1[1] <= SEG7_LUT:U1.oSEG +oX_MOV1[2] <= SEG7_LUT:U1.oSEG +oX_MOV1[3] <= SEG7_LUT:U1.oSEG +oX_MOV1[4] <= SEG7_LUT:U1.oSEG +oX_MOV1[5] <= SEG7_LUT:U1.oSEG +oX_MOV1[6] <= SEG7_LUT:U1.oSEG +oX_MOV2[0] <= SEG7_LUT:U2.oSEG +oX_MOV2[1] <= SEG7_LUT:U2.oSEG +oX_MOV2[2] <= SEG7_LUT:U2.oSEG +oX_MOV2[3] <= SEG7_LUT:U2.oSEG +oX_MOV2[4] <= SEG7_LUT:U2.oSEG +oX_MOV2[5] <= SEG7_LUT:U2.oSEG +oX_MOV2[6] <= SEG7_LUT:U2.oSEG +oY_MOV1[0] <= SEG7_LUT:U3.oSEG +oY_MOV1[1] <= SEG7_LUT:U3.oSEG +oY_MOV1[2] <= SEG7_LUT:U3.oSEG +oY_MOV1[3] <= SEG7_LUT:U3.oSEG +oY_MOV1[4] <= SEG7_LUT:U3.oSEG +oY_MOV1[5] <= SEG7_LUT:U3.oSEG +oY_MOV1[6] <= SEG7_LUT:U3.oSEG +oY_MOV2[0] <= SEG7_LUT:U4.oSEG +oY_MOV2[1] <= SEG7_LUT:U4.oSEG +oY_MOV2[2] <= SEG7_LUT:U4.oSEG +oY_MOV2[3] <= SEG7_LUT:U4.oSEG +oY_MOV2[4] <= SEG7_LUT:U4.oSEG +oY_MOV2[5] <= SEG7_LUT:U4.oSEG +oY_MOV2[6] <= SEG7_LUT:U4.oSEG + + +|TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U1 +oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE +oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE +oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE +oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE +oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE +oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE +oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +iDIG[0] => Decoder0.IN3 +iDIG[1] => Decoder0.IN2 +iDIG[2] => Decoder0.IN1 +iDIG[3] => Decoder0.IN0 + + +|TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U2 +oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE +oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE +oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE +oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE +oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE +oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE +oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +iDIG[0] => Decoder0.IN3 +iDIG[1] => Decoder0.IN2 +iDIG[2] => Decoder0.IN1 +iDIG[3] => Decoder0.IN0 + + +|TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U3 +oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE +oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE +oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE +oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE +oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE +oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE +oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +iDIG[0] => Decoder0.IN3 +iDIG[1] => Decoder0.IN2 +iDIG[2] => Decoder0.IN1 +iDIG[3] => Decoder0.IN0 + + +|TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U4 +oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE +oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE +oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE +oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE +oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE +oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE +oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +iDIG[0] => Decoder0.IN3 +iDIG[1] => Decoder0.IN2 +iDIG[2] => Decoder0.IN1 +iDIG[3] => Decoder0.IN0 + + +|TOP_DE0_CAMERA_MOUSE|vga_mux:inst10 +data0x[0] => LPM_MUX:LPM_MUX_component.DATA[0][0] +data0x[1] => LPM_MUX:LPM_MUX_component.DATA[0][1] +data0x[2] => LPM_MUX:LPM_MUX_component.DATA[0][2] +data0x[3] => LPM_MUX:LPM_MUX_component.DATA[0][3] +data0x[4] => LPM_MUX:LPM_MUX_component.DATA[0][4] +data0x[5] => LPM_MUX:LPM_MUX_component.DATA[0][5] +data0x[6] => LPM_MUX:LPM_MUX_component.DATA[0][6] +data0x[7] => LPM_MUX:LPM_MUX_component.DATA[0][7] +data0x[8] => LPM_MUX:LPM_MUX_component.DATA[0][8] +data0x[9] => LPM_MUX:LPM_MUX_component.DATA[0][9] +data0x[10] => LPM_MUX:LPM_MUX_component.DATA[0][10] +data0x[11] => LPM_MUX:LPM_MUX_component.DATA[0][11] +data0x[12] => LPM_MUX:LPM_MUX_component.DATA[0][12] +data0x[13] => LPM_MUX:LPM_MUX_component.DATA[0][13] +data0x[14] => LPM_MUX:LPM_MUX_component.DATA[0][14] +data0x[15] => LPM_MUX:LPM_MUX_component.DATA[0][15] +data0x[16] => LPM_MUX:LPM_MUX_component.DATA[0][16] +data0x[17] => LPM_MUX:LPM_MUX_component.DATA[0][17] +data0x[18] => LPM_MUX:LPM_MUX_component.DATA[0][18] +data0x[19] => LPM_MUX:LPM_MUX_component.DATA[0][19] +data0x[20] => LPM_MUX:LPM_MUX_component.DATA[0][20] +data0x[21] => LPM_MUX:LPM_MUX_component.DATA[0][21] +data0x[22] => LPM_MUX:LPM_MUX_component.DATA[0][22] +data0x[23] => LPM_MUX:LPM_MUX_component.DATA[0][23] +data0x[24] => LPM_MUX:LPM_MUX_component.DATA[0][24] +data0x[25] => LPM_MUX:LPM_MUX_component.DATA[0][25] +data0x[26] => LPM_MUX:LPM_MUX_component.DATA[0][26] +data0x[27] => LPM_MUX:LPM_MUX_component.DATA[0][27] +data0x[28] => LPM_MUX:LPM_MUX_component.DATA[0][28] +data0x[29] => LPM_MUX:LPM_MUX_component.DATA[0][29] +data1x[0] => LPM_MUX:LPM_MUX_component.DATA[1][0] +data1x[1] => LPM_MUX:LPM_MUX_component.DATA[1][1] +data1x[2] => LPM_MUX:LPM_MUX_component.DATA[1][2] +data1x[3] => LPM_MUX:LPM_MUX_component.DATA[1][3] +data1x[4] => LPM_MUX:LPM_MUX_component.DATA[1][4] +data1x[5] => LPM_MUX:LPM_MUX_component.DATA[1][5] +data1x[6] => LPM_MUX:LPM_MUX_component.DATA[1][6] +data1x[7] => LPM_MUX:LPM_MUX_component.DATA[1][7] +data1x[8] => LPM_MUX:LPM_MUX_component.DATA[1][8] +data1x[9] => LPM_MUX:LPM_MUX_component.DATA[1][9] +data1x[10] => LPM_MUX:LPM_MUX_component.DATA[1][10] +data1x[11] => LPM_MUX:LPM_MUX_component.DATA[1][11] +data1x[12] => LPM_MUX:LPM_MUX_component.DATA[1][12] +data1x[13] => LPM_MUX:LPM_MUX_component.DATA[1][13] +data1x[14] => LPM_MUX:LPM_MUX_component.DATA[1][14] +data1x[15] => LPM_MUX:LPM_MUX_component.DATA[1][15] +data1x[16] => LPM_MUX:LPM_MUX_component.DATA[1][16] +data1x[17] => LPM_MUX:LPM_MUX_component.DATA[1][17] +data1x[18] => LPM_MUX:LPM_MUX_component.DATA[1][18] +data1x[19] => LPM_MUX:LPM_MUX_component.DATA[1][19] +data1x[20] => LPM_MUX:LPM_MUX_component.DATA[1][20] +data1x[21] => LPM_MUX:LPM_MUX_component.DATA[1][21] +data1x[22] => LPM_MUX:LPM_MUX_component.DATA[1][22] +data1x[23] => LPM_MUX:LPM_MUX_component.DATA[1][23] +data1x[24] => LPM_MUX:LPM_MUX_component.DATA[1][24] +data1x[25] => LPM_MUX:LPM_MUX_component.DATA[1][25] +data1x[26] => LPM_MUX:LPM_MUX_component.DATA[1][26] +data1x[27] => LPM_MUX:LPM_MUX_component.DATA[1][27] +data1x[28] => LPM_MUX:LPM_MUX_component.DATA[1][28] +data1x[29] => LPM_MUX:LPM_MUX_component.DATA[1][29] +data2x[0] => LPM_MUX:LPM_MUX_component.DATA[2][0] +data2x[1] => LPM_MUX:LPM_MUX_component.DATA[2][1] +data2x[2] => LPM_MUX:LPM_MUX_component.DATA[2][2] +data2x[3] => LPM_MUX:LPM_MUX_component.DATA[2][3] +data2x[4] => LPM_MUX:LPM_MUX_component.DATA[2][4] +data2x[5] => LPM_MUX:LPM_MUX_component.DATA[2][5] +data2x[6] => LPM_MUX:LPM_MUX_component.DATA[2][6] +data2x[7] => LPM_MUX:LPM_MUX_component.DATA[2][7] +data2x[8] => LPM_MUX:LPM_MUX_component.DATA[2][8] +data2x[9] => LPM_MUX:LPM_MUX_component.DATA[2][9] +data2x[10] => LPM_MUX:LPM_MUX_component.DATA[2][10] +data2x[11] => LPM_MUX:LPM_MUX_component.DATA[2][11] +data2x[12] => LPM_MUX:LPM_MUX_component.DATA[2][12] +data2x[13] => LPM_MUX:LPM_MUX_component.DATA[2][13] +data2x[14] => LPM_MUX:LPM_MUX_component.DATA[2][14] +data2x[15] => LPM_MUX:LPM_MUX_component.DATA[2][15] +data2x[16] => LPM_MUX:LPM_MUX_component.DATA[2][16] +data2x[17] => LPM_MUX:LPM_MUX_component.DATA[2][17] +data2x[18] => LPM_MUX:LPM_MUX_component.DATA[2][18] +data2x[19] => LPM_MUX:LPM_MUX_component.DATA[2][19] +data2x[20] => LPM_MUX:LPM_MUX_component.DATA[2][20] +data2x[21] => LPM_MUX:LPM_MUX_component.DATA[2][21] +data2x[22] => LPM_MUX:LPM_MUX_component.DATA[2][22] +data2x[23] => LPM_MUX:LPM_MUX_component.DATA[2][23] +data2x[24] => LPM_MUX:LPM_MUX_component.DATA[2][24] +data2x[25] => LPM_MUX:LPM_MUX_component.DATA[2][25] +data2x[26] => LPM_MUX:LPM_MUX_component.DATA[2][26] +data2x[27] => LPM_MUX:LPM_MUX_component.DATA[2][27] +data2x[28] => LPM_MUX:LPM_MUX_component.DATA[2][28] +data2x[29] => LPM_MUX:LPM_MUX_component.DATA[2][29] +data3x[0] => LPM_MUX:LPM_MUX_component.DATA[3][0] +data3x[1] => LPM_MUX:LPM_MUX_component.DATA[3][1] +data3x[2] => LPM_MUX:LPM_MUX_component.DATA[3][2] +data3x[3] => LPM_MUX:LPM_MUX_component.DATA[3][3] +data3x[4] => LPM_MUX:LPM_MUX_component.DATA[3][4] +data3x[5] => LPM_MUX:LPM_MUX_component.DATA[3][5] +data3x[6] => LPM_MUX:LPM_MUX_component.DATA[3][6] +data3x[7] => LPM_MUX:LPM_MUX_component.DATA[3][7] +data3x[8] => LPM_MUX:LPM_MUX_component.DATA[3][8] +data3x[9] => LPM_MUX:LPM_MUX_component.DATA[3][9] +data3x[10] => LPM_MUX:LPM_MUX_component.DATA[3][10] +data3x[11] => LPM_MUX:LPM_MUX_component.DATA[3][11] +data3x[12] => LPM_MUX:LPM_MUX_component.DATA[3][12] +data3x[13] => LPM_MUX:LPM_MUX_component.DATA[3][13] +data3x[14] => LPM_MUX:LPM_MUX_component.DATA[3][14] +data3x[15] => LPM_MUX:LPM_MUX_component.DATA[3][15] +data3x[16] => LPM_MUX:LPM_MUX_component.DATA[3][16] +data3x[17] => LPM_MUX:LPM_MUX_component.DATA[3][17] +data3x[18] => LPM_MUX:LPM_MUX_component.DATA[3][18] +data3x[19] => LPM_MUX:LPM_MUX_component.DATA[3][19] +data3x[20] => LPM_MUX:LPM_MUX_component.DATA[3][20] +data3x[21] => LPM_MUX:LPM_MUX_component.DATA[3][21] +data3x[22] => LPM_MUX:LPM_MUX_component.DATA[3][22] +data3x[23] => LPM_MUX:LPM_MUX_component.DATA[3][23] +data3x[24] => LPM_MUX:LPM_MUX_component.DATA[3][24] +data3x[25] => LPM_MUX:LPM_MUX_component.DATA[3][25] +data3x[26] => LPM_MUX:LPM_MUX_component.DATA[3][26] +data3x[27] => LPM_MUX:LPM_MUX_component.DATA[3][27] +data3x[28] => LPM_MUX:LPM_MUX_component.DATA[3][28] +data3x[29] => LPM_MUX:LPM_MUX_component.DATA[3][29] +sel[0] => LPM_MUX:LPM_MUX_component.SEL[0] +sel[1] => LPM_MUX:LPM_MUX_component.SEL[1] +result[0] <= LPM_MUX:LPM_MUX_component.RESULT[0] +result[1] <= LPM_MUX:LPM_MUX_component.RESULT[1] +result[2] <= LPM_MUX:LPM_MUX_component.RESULT[2] +result[3] <= LPM_MUX:LPM_MUX_component.RESULT[3] +result[4] <= LPM_MUX:LPM_MUX_component.RESULT[4] +result[5] <= LPM_MUX:LPM_MUX_component.RESULT[5] +result[6] <= LPM_MUX:LPM_MUX_component.RESULT[6] +result[7] <= LPM_MUX:LPM_MUX_component.RESULT[7] +result[8] <= LPM_MUX:LPM_MUX_component.RESULT[8] +result[9] <= LPM_MUX:LPM_MUX_component.RESULT[9] +result[10] <= LPM_MUX:LPM_MUX_component.RESULT[10] +result[11] <= LPM_MUX:LPM_MUX_component.RESULT[11] +result[12] <= LPM_MUX:LPM_MUX_component.RESULT[12] +result[13] <= LPM_MUX:LPM_MUX_component.RESULT[13] +result[14] <= LPM_MUX:LPM_MUX_component.RESULT[14] +result[15] <= LPM_MUX:LPM_MUX_component.RESULT[15] +result[16] <= LPM_MUX:LPM_MUX_component.RESULT[16] +result[17] <= LPM_MUX:LPM_MUX_component.RESULT[17] +result[18] <= LPM_MUX:LPM_MUX_component.RESULT[18] +result[19] <= LPM_MUX:LPM_MUX_component.RESULT[19] +result[20] <= LPM_MUX:LPM_MUX_component.RESULT[20] +result[21] <= LPM_MUX:LPM_MUX_component.RESULT[21] +result[22] <= LPM_MUX:LPM_MUX_component.RESULT[22] +result[23] <= LPM_MUX:LPM_MUX_component.RESULT[23] +result[24] <= LPM_MUX:LPM_MUX_component.RESULT[24] +result[25] <= LPM_MUX:LPM_MUX_component.RESULT[25] +result[26] <= LPM_MUX:LPM_MUX_component.RESULT[26] +result[27] <= LPM_MUX:LPM_MUX_component.RESULT[27] +result[28] <= LPM_MUX:LPM_MUX_component.RESULT[28] +result[29] <= LPM_MUX:LPM_MUX_component.RESULT[29] + + +|TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|LPM_MUX:LPM_MUX_component +data[0][0] => mux_u7e:auto_generated.data[0] +data[0][1] => mux_u7e:auto_generated.data[1] +data[0][2] => mux_u7e:auto_generated.data[2] +data[0][3] => mux_u7e:auto_generated.data[3] +data[0][4] => mux_u7e:auto_generated.data[4] +data[0][5] => mux_u7e:auto_generated.data[5] +data[0][6] => mux_u7e:auto_generated.data[6] +data[0][7] => mux_u7e:auto_generated.data[7] +data[0][8] => mux_u7e:auto_generated.data[8] +data[0][9] => mux_u7e:auto_generated.data[9] +data[0][10] => mux_u7e:auto_generated.data[10] +data[0][11] => mux_u7e:auto_generated.data[11] +data[0][12] => mux_u7e:auto_generated.data[12] +data[0][13] => mux_u7e:auto_generated.data[13] +data[0][14] => mux_u7e:auto_generated.data[14] +data[0][15] => mux_u7e:auto_generated.data[15] +data[0][16] => mux_u7e:auto_generated.data[16] +data[0][17] => mux_u7e:auto_generated.data[17] +data[0][18] => mux_u7e:auto_generated.data[18] +data[0][19] => mux_u7e:auto_generated.data[19] +data[0][20] => mux_u7e:auto_generated.data[20] +data[0][21] => mux_u7e:auto_generated.data[21] +data[0][22] => mux_u7e:auto_generated.data[22] +data[0][23] => mux_u7e:auto_generated.data[23] +data[0][24] => mux_u7e:auto_generated.data[24] +data[0][25] => mux_u7e:auto_generated.data[25] +data[0][26] => mux_u7e:auto_generated.data[26] +data[0][27] => mux_u7e:auto_generated.data[27] +data[0][28] => mux_u7e:auto_generated.data[28] +data[0][29] => mux_u7e:auto_generated.data[29] +data[1][0] => mux_u7e:auto_generated.data[30] +data[1][1] => mux_u7e:auto_generated.data[31] +data[1][2] => mux_u7e:auto_generated.data[32] +data[1][3] => mux_u7e:auto_generated.data[33] +data[1][4] => mux_u7e:auto_generated.data[34] +data[1][5] => mux_u7e:auto_generated.data[35] +data[1][6] => mux_u7e:auto_generated.data[36] +data[1][7] => mux_u7e:auto_generated.data[37] +data[1][8] => mux_u7e:auto_generated.data[38] +data[1][9] => mux_u7e:auto_generated.data[39] +data[1][10] => mux_u7e:auto_generated.data[40] +data[1][11] => mux_u7e:auto_generated.data[41] +data[1][12] => mux_u7e:auto_generated.data[42] +data[1][13] => mux_u7e:auto_generated.data[43] +data[1][14] => mux_u7e:auto_generated.data[44] +data[1][15] => mux_u7e:auto_generated.data[45] +data[1][16] => mux_u7e:auto_generated.data[46] +data[1][17] => mux_u7e:auto_generated.data[47] +data[1][18] => mux_u7e:auto_generated.data[48] +data[1][19] => mux_u7e:auto_generated.data[49] +data[1][20] => mux_u7e:auto_generated.data[50] +data[1][21] => mux_u7e:auto_generated.data[51] +data[1][22] => mux_u7e:auto_generated.data[52] +data[1][23] => mux_u7e:auto_generated.data[53] +data[1][24] => mux_u7e:auto_generated.data[54] +data[1][25] => mux_u7e:auto_generated.data[55] +data[1][26] => mux_u7e:auto_generated.data[56] +data[1][27] => mux_u7e:auto_generated.data[57] +data[1][28] => mux_u7e:auto_generated.data[58] +data[1][29] => mux_u7e:auto_generated.data[59] +data[2][0] => mux_u7e:auto_generated.data[60] +data[2][1] => mux_u7e:auto_generated.data[61] +data[2][2] => mux_u7e:auto_generated.data[62] +data[2][3] => mux_u7e:auto_generated.data[63] +data[2][4] => mux_u7e:auto_generated.data[64] +data[2][5] => mux_u7e:auto_generated.data[65] +data[2][6] => mux_u7e:auto_generated.data[66] +data[2][7] => mux_u7e:auto_generated.data[67] +data[2][8] => mux_u7e:auto_generated.data[68] +data[2][9] => mux_u7e:auto_generated.data[69] +data[2][10] => mux_u7e:auto_generated.data[70] +data[2][11] => mux_u7e:auto_generated.data[71] +data[2][12] => mux_u7e:auto_generated.data[72] +data[2][13] => mux_u7e:auto_generated.data[73] +data[2][14] => mux_u7e:auto_generated.data[74] +data[2][15] => mux_u7e:auto_generated.data[75] +data[2][16] => mux_u7e:auto_generated.data[76] +data[2][17] => mux_u7e:auto_generated.data[77] +data[2][18] => mux_u7e:auto_generated.data[78] +data[2][19] => mux_u7e:auto_generated.data[79] +data[2][20] => mux_u7e:auto_generated.data[80] +data[2][21] => mux_u7e:auto_generated.data[81] +data[2][22] => mux_u7e:auto_generated.data[82] +data[2][23] => mux_u7e:auto_generated.data[83] +data[2][24] => mux_u7e:auto_generated.data[84] +data[2][25] => mux_u7e:auto_generated.data[85] +data[2][26] => mux_u7e:auto_generated.data[86] +data[2][27] => mux_u7e:auto_generated.data[87] +data[2][28] => mux_u7e:auto_generated.data[88] +data[2][29] => mux_u7e:auto_generated.data[89] +data[3][0] => mux_u7e:auto_generated.data[90] +data[3][1] => mux_u7e:auto_generated.data[91] +data[3][2] => mux_u7e:auto_generated.data[92] +data[3][3] => mux_u7e:auto_generated.data[93] +data[3][4] => mux_u7e:auto_generated.data[94] +data[3][5] => mux_u7e:auto_generated.data[95] +data[3][6] => mux_u7e:auto_generated.data[96] +data[3][7] => mux_u7e:auto_generated.data[97] +data[3][8] => mux_u7e:auto_generated.data[98] +data[3][9] => mux_u7e:auto_generated.data[99] +data[3][10] => mux_u7e:auto_generated.data[100] +data[3][11] => mux_u7e:auto_generated.data[101] +data[3][12] => mux_u7e:auto_generated.data[102] +data[3][13] => mux_u7e:auto_generated.data[103] +data[3][14] => mux_u7e:auto_generated.data[104] +data[3][15] => mux_u7e:auto_generated.data[105] +data[3][16] => mux_u7e:auto_generated.data[106] +data[3][17] => mux_u7e:auto_generated.data[107] +data[3][18] => mux_u7e:auto_generated.data[108] +data[3][19] => mux_u7e:auto_generated.data[109] +data[3][20] => mux_u7e:auto_generated.data[110] +data[3][21] => mux_u7e:auto_generated.data[111] +data[3][22] => mux_u7e:auto_generated.data[112] +data[3][23] => mux_u7e:auto_generated.data[113] +data[3][24] => mux_u7e:auto_generated.data[114] +data[3][25] => mux_u7e:auto_generated.data[115] +data[3][26] => mux_u7e:auto_generated.data[116] +data[3][27] => mux_u7e:auto_generated.data[117] +data[3][28] => mux_u7e:auto_generated.data[118] +data[3][29] => mux_u7e:auto_generated.data[119] +sel[0] => mux_u7e:auto_generated.sel[0] +sel[1] => mux_u7e:auto_generated.sel[1] +clock => ~NO_FANOUT~ +aclr => ~NO_FANOUT~ +clken => ~NO_FANOUT~ +result[0] <= mux_u7e:auto_generated.result[0] +result[1] <= mux_u7e:auto_generated.result[1] +result[2] <= mux_u7e:auto_generated.result[2] +result[3] <= mux_u7e:auto_generated.result[3] +result[4] <= mux_u7e:auto_generated.result[4] +result[5] <= mux_u7e:auto_generated.result[5] +result[6] <= mux_u7e:auto_generated.result[6] +result[7] <= mux_u7e:auto_generated.result[7] +result[8] <= mux_u7e:auto_generated.result[8] +result[9] <= mux_u7e:auto_generated.result[9] +result[10] <= mux_u7e:auto_generated.result[10] +result[11] <= mux_u7e:auto_generated.result[11] +result[12] <= mux_u7e:auto_generated.result[12] +result[13] <= mux_u7e:auto_generated.result[13] +result[14] <= mux_u7e:auto_generated.result[14] +result[15] <= mux_u7e:auto_generated.result[15] +result[16] <= mux_u7e:auto_generated.result[16] +result[17] <= mux_u7e:auto_generated.result[17] +result[18] <= mux_u7e:auto_generated.result[18] +result[19] <= mux_u7e:auto_generated.result[19] +result[20] <= mux_u7e:auto_generated.result[20] +result[21] <= mux_u7e:auto_generated.result[21] +result[22] <= mux_u7e:auto_generated.result[22] +result[23] <= mux_u7e:auto_generated.result[23] +result[24] <= mux_u7e:auto_generated.result[24] +result[25] <= mux_u7e:auto_generated.result[25] +result[26] <= mux_u7e:auto_generated.result[26] +result[27] <= mux_u7e:auto_generated.result[27] +result[28] <= mux_u7e:auto_generated.result[28] +result[29] <= mux_u7e:auto_generated.result[29] + + +|TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|LPM_MUX:LPM_MUX_component|mux_u7e:auto_generated +data[0] => _.IN0 +data[0] => _.IN0 +data[1] => _.IN0 +data[1] => _.IN0 +data[2] => _.IN0 +data[2] => _.IN0 +data[3] => _.IN0 +data[3] => _.IN0 +data[4] => _.IN0 +data[4] => _.IN0 +data[5] => _.IN0 +data[5] => _.IN0 +data[6] => _.IN0 +data[6] => _.IN0 +data[7] => _.IN0 +data[7] => _.IN0 +data[8] => _.IN0 +data[8] => _.IN0 +data[9] => _.IN0 +data[9] => _.IN0 +data[10] => _.IN0 +data[10] => _.IN0 +data[11] => _.IN0 +data[11] => _.IN0 +data[12] => _.IN0 +data[12] => _.IN0 +data[13] => _.IN0 +data[13] => _.IN0 +data[14] => _.IN0 +data[14] => _.IN0 +data[15] => _.IN0 +data[15] => _.IN0 +data[16] => _.IN0 +data[16] => _.IN0 +data[17] => _.IN0 +data[17] => _.IN0 +data[18] => _.IN0 +data[18] => _.IN0 +data[19] => _.IN0 +data[19] => _.IN0 +data[20] => _.IN0 +data[20] => _.IN0 +data[21] => _.IN0 +data[21] => _.IN0 +data[22] => _.IN0 +data[22] => _.IN0 +data[23] => _.IN0 +data[23] => _.IN0 +data[24] => _.IN0 +data[24] => _.IN0 +data[25] => _.IN0 +data[25] => _.IN0 +data[26] => _.IN0 +data[26] => _.IN0 +data[27] => _.IN0 +data[27] => _.IN0 +data[28] => _.IN0 +data[28] => _.IN0 +data[29] => _.IN0 +data[29] => _.IN0 +data[30] => _.IN0 +data[31] => _.IN0 +data[32] => _.IN0 +data[33] => _.IN0 +data[34] => _.IN0 +data[35] => _.IN0 +data[36] => _.IN0 +data[37] => _.IN0 +data[38] => _.IN0 +data[39] => _.IN0 +data[40] => _.IN0 +data[41] => _.IN0 +data[42] => _.IN0 +data[43] => _.IN0 +data[44] => _.IN0 +data[45] => _.IN0 +data[46] => _.IN0 +data[47] => _.IN0 +data[48] => _.IN0 +data[49] => _.IN0 +data[50] => _.IN0 +data[51] => _.IN0 +data[52] => _.IN0 +data[53] => _.IN0 +data[54] => _.IN0 +data[55] => _.IN0 +data[56] => _.IN0 +data[57] => _.IN0 +data[58] => _.IN0 +data[59] => _.IN0 +data[60] => _.IN1 +data[60] => _.IN1 +data[61] => _.IN1 +data[61] => _.IN1 +data[62] => _.IN1 +data[62] => _.IN1 +data[63] => _.IN1 +data[63] => _.IN1 +data[64] => _.IN1 +data[64] => _.IN1 +data[65] => _.IN1 +data[65] => _.IN1 +data[66] => _.IN1 +data[66] => _.IN1 +data[67] => _.IN1 +data[67] => _.IN1 +data[68] => _.IN1 +data[68] => _.IN1 +data[69] => _.IN1 +data[69] => _.IN1 +data[70] => _.IN1 +data[70] => _.IN1 +data[71] => _.IN1 +data[71] => _.IN1 +data[72] => _.IN1 +data[72] => _.IN1 +data[73] => _.IN1 +data[73] => _.IN1 +data[74] => _.IN1 +data[74] => _.IN1 +data[75] => _.IN1 +data[75] => _.IN1 +data[76] => _.IN1 +data[76] => _.IN1 +data[77] => _.IN1 +data[77] => _.IN1 +data[78] => _.IN1 +data[78] => _.IN1 +data[79] => _.IN1 +data[79] => _.IN1 +data[80] => _.IN1 +data[80] => _.IN1 +data[81] => _.IN1 +data[81] => _.IN1 +data[82] => _.IN1 +data[82] => _.IN1 +data[83] => _.IN1 +data[83] => _.IN1 +data[84] => _.IN1 +data[84] => _.IN1 +data[85] => _.IN1 +data[85] => _.IN1 +data[86] => _.IN1 +data[86] => _.IN1 +data[87] => _.IN1 +data[87] => _.IN1 +data[88] => _.IN1 +data[88] => _.IN1 +data[89] => _.IN1 +data[89] => _.IN1 +data[90] => _.IN0 +data[91] => _.IN0 +data[92] => _.IN0 +data[93] => _.IN0 +data[94] => _.IN0 +data[95] => _.IN0 +data[96] => _.IN0 +data[97] => _.IN0 +data[98] => _.IN0 +data[99] => _.IN0 +data[100] => _.IN0 +data[101] => _.IN0 +data[102] => _.IN0 +data[103] => _.IN0 +data[104] => _.IN0 +data[105] => _.IN0 +data[106] => _.IN0 +data[107] => _.IN0 +data[108] => _.IN0 +data[109] => _.IN0 +data[110] => _.IN0 +data[111] => _.IN0 +data[112] => _.IN0 +data[113] => _.IN0 +data[114] => _.IN0 +data[115] => _.IN0 +data[116] => _.IN0 +data[117] => _.IN0 +data[118] => _.IN0 +data[119] => _.IN0 +result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE +result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE +result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE +result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE +result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE +result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE +result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE +result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE +result[8] <= result_node[8].DB_MAX_OUTPUT_PORT_TYPE +result[9] <= result_node[9].DB_MAX_OUTPUT_PORT_TYPE +result[10] <= result_node[10].DB_MAX_OUTPUT_PORT_TYPE +result[11] <= result_node[11].DB_MAX_OUTPUT_PORT_TYPE +result[12] <= result_node[12].DB_MAX_OUTPUT_PORT_TYPE +result[13] <= result_node[13].DB_MAX_OUTPUT_PORT_TYPE +result[14] <= result_node[14].DB_MAX_OUTPUT_PORT_TYPE +result[15] <= result_node[15].DB_MAX_OUTPUT_PORT_TYPE +result[16] <= result_node[16].DB_MAX_OUTPUT_PORT_TYPE +result[17] <= result_node[17].DB_MAX_OUTPUT_PORT_TYPE +result[18] <= result_node[18].DB_MAX_OUTPUT_PORT_TYPE +result[19] <= result_node[19].DB_MAX_OUTPUT_PORT_TYPE +result[20] <= result_node[20].DB_MAX_OUTPUT_PORT_TYPE +result[21] <= result_node[21].DB_MAX_OUTPUT_PORT_TYPE +result[22] <= result_node[22].DB_MAX_OUTPUT_PORT_TYPE +result[23] <= result_node[23].DB_MAX_OUTPUT_PORT_TYPE +result[24] <= result_node[24].DB_MAX_OUTPUT_PORT_TYPE +result[25] <= result_node[25].DB_MAX_OUTPUT_PORT_TYPE +result[26] <= result_node[26].DB_MAX_OUTPUT_PORT_TYPE +result[27] <= result_node[27].DB_MAX_OUTPUT_PORT_TYPE +result[28] <= result_node[28].DB_MAX_OUTPUT_PORT_TYPE +result[29] <= result_node[29].DB_MAX_OUTPUT_PORT_TYPE +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 + + +|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst +vga_xy_rsc_z[0] => vga_xy_rsc_z[0].IN1 +vga_xy_rsc_z[1] => vga_xy_rsc_z[1].IN1 +vga_xy_rsc_z[2] => vga_xy_rsc_z[2].IN1 +vga_xy_rsc_z[3] => vga_xy_rsc_z[3].IN1 +vga_xy_rsc_z[4] => vga_xy_rsc_z[4].IN1 +vga_xy_rsc_z[5] => vga_xy_rsc_z[5].IN1 +vga_xy_rsc_z[6] => vga_xy_rsc_z[6].IN1 +vga_xy_rsc_z[7] => vga_xy_rsc_z[7].IN1 +vga_xy_rsc_z[8] => vga_xy_rsc_z[8].IN1 +vga_xy_rsc_z[9] => vga_xy_rsc_z[9].IN1 +vga_xy_rsc_z[10] => vga_xy_rsc_z[10].IN1 +vga_xy_rsc_z[11] => vga_xy_rsc_z[11].IN1 +vga_xy_rsc_z[12] => vga_xy_rsc_z[12].IN1 +vga_xy_rsc_z[13] => vga_xy_rsc_z[13].IN1 +vga_xy_rsc_z[14] => vga_xy_rsc_z[14].IN1 +vga_xy_rsc_z[15] => vga_xy_rsc_z[15].IN1 +vga_xy_rsc_z[16] => vga_xy_rsc_z[16].IN1 +vga_xy_rsc_z[17] => vga_xy_rsc_z[17].IN1 +vga_xy_rsc_z[18] => vga_xy_rsc_z[18].IN1 +vga_xy_rsc_z[19] => vga_xy_rsc_z[19].IN1 +mouse_xy_rsc_z[0] => mouse_xy_rsc_z[0].IN1 +mouse_xy_rsc_z[1] => mouse_xy_rsc_z[1].IN1 +mouse_xy_rsc_z[2] => mouse_xy_rsc_z[2].IN1 +mouse_xy_rsc_z[3] => mouse_xy_rsc_z[3].IN1 +mouse_xy_rsc_z[4] => mouse_xy_rsc_z[4].IN1 +mouse_xy_rsc_z[5] => mouse_xy_rsc_z[5].IN1 +mouse_xy_rsc_z[6] => mouse_xy_rsc_z[6].IN1 +mouse_xy_rsc_z[7] => mouse_xy_rsc_z[7].IN1 +mouse_xy_rsc_z[8] => mouse_xy_rsc_z[8].IN1 +mouse_xy_rsc_z[9] => mouse_xy_rsc_z[9].IN1 +mouse_xy_rsc_z[10] => mouse_xy_rsc_z[10].IN1 +mouse_xy_rsc_z[11] => mouse_xy_rsc_z[11].IN1 +mouse_xy_rsc_z[12] => mouse_xy_rsc_z[12].IN1 +mouse_xy_rsc_z[13] => mouse_xy_rsc_z[13].IN1 +mouse_xy_rsc_z[14] => mouse_xy_rsc_z[14].IN1 +mouse_xy_rsc_z[15] => mouse_xy_rsc_z[15].IN1 +mouse_xy_rsc_z[16] => mouse_xy_rsc_z[16].IN1 +mouse_xy_rsc_z[17] => mouse_xy_rsc_z[17].IN1 +mouse_xy_rsc_z[18] => mouse_xy_rsc_z[18].IN1 +mouse_xy_rsc_z[19] => mouse_xy_rsc_z[19].IN1 +cursor_size_rsc_z[0] => cursor_size_rsc_z[0].IN1 +cursor_size_rsc_z[1] => cursor_size_rsc_z[1].IN1 +cursor_size_rsc_z[2] => cursor_size_rsc_z[2].IN1 +cursor_size_rsc_z[3] => cursor_size_rsc_z[3].IN1 +cursor_size_rsc_z[4] => cursor_size_rsc_z[4].IN1 +cursor_size_rsc_z[5] => cursor_size_rsc_z[5].IN1 +cursor_size_rsc_z[6] => cursor_size_rsc_z[6].IN1 +cursor_size_rsc_z[7] => cursor_size_rsc_z[7].IN1 +video_in_rsc_z[0] => video_in_rsc_z[0].IN1 +video_in_rsc_z[1] => video_in_rsc_z[1].IN1 +video_in_rsc_z[2] => video_in_rsc_z[2].IN1 +video_in_rsc_z[3] => video_in_rsc_z[3].IN1 +video_in_rsc_z[4] => video_in_rsc_z[4].IN1 +video_in_rsc_z[5] => video_in_rsc_z[5].IN1 +video_in_rsc_z[6] => video_in_rsc_z[6].IN1 +video_in_rsc_z[7] => video_in_rsc_z[7].IN1 +video_in_rsc_z[8] => video_in_rsc_z[8].IN1 +video_in_rsc_z[9] => video_in_rsc_z[9].IN1 +video_in_rsc_z[10] => video_in_rsc_z[10].IN1 +video_in_rsc_z[11] => video_in_rsc_z[11].IN1 +video_in_rsc_z[12] => video_in_rsc_z[12].IN1 +video_in_rsc_z[13] => video_in_rsc_z[13].IN1 +video_in_rsc_z[14] => video_in_rsc_z[14].IN1 +video_in_rsc_z[15] => video_in_rsc_z[15].IN1 +video_in_rsc_z[16] => video_in_rsc_z[16].IN1 +video_in_rsc_z[17] => video_in_rsc_z[17].IN1 +video_in_rsc_z[18] => video_in_rsc_z[18].IN1 +video_in_rsc_z[19] => video_in_rsc_z[19].IN1 +video_in_rsc_z[20] => video_in_rsc_z[20].IN1 +video_in_rsc_z[21] => video_in_rsc_z[21].IN1 +video_in_rsc_z[22] => video_in_rsc_z[22].IN1 +video_in_rsc_z[23] => video_in_rsc_z[23].IN1 +video_in_rsc_z[24] => video_in_rsc_z[24].IN1 +video_in_rsc_z[25] => video_in_rsc_z[25].IN1 +video_in_rsc_z[26] => video_in_rsc_z[26].IN1 +video_in_rsc_z[27] => video_in_rsc_z[27].IN1 +video_in_rsc_z[28] => video_in_rsc_z[28].IN1 +video_in_rsc_z[29] => video_in_rsc_z[29].IN1 +video_out_rsc_z[0] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[1] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[2] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[3] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[4] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[5] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[6] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[7] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[8] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[9] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[10] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[11] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[12] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[13] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[14] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[15] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[16] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[17] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[18] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[19] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[20] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[21] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[22] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[23] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[24] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[25] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[26] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[27] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[28] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +video_out_rsc_z[29] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z +clk => clk.IN1 +en => en.IN1 +arst_n => arst_n.IN1 + + +|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:vga_xy_rsc_mgc_in_wire +d[0] <= z[0].DB_MAX_OUTPUT_PORT_TYPE +d[1] <= z[1].DB_MAX_OUTPUT_PORT_TYPE +d[2] <= z[2].DB_MAX_OUTPUT_PORT_TYPE +d[3] <= z[3].DB_MAX_OUTPUT_PORT_TYPE +d[4] <= z[4].DB_MAX_OUTPUT_PORT_TYPE +d[5] <= z[5].DB_MAX_OUTPUT_PORT_TYPE +d[6] <= z[6].DB_MAX_OUTPUT_PORT_TYPE +d[7] <= z[7].DB_MAX_OUTPUT_PORT_TYPE +d[8] <= z[8].DB_MAX_OUTPUT_PORT_TYPE +d[9] <= z[9].DB_MAX_OUTPUT_PORT_TYPE +d[10] <= z[10].DB_MAX_OUTPUT_PORT_TYPE +d[11] <= z[11].DB_MAX_OUTPUT_PORT_TYPE +d[12] <= z[12].DB_MAX_OUTPUT_PORT_TYPE +d[13] <= z[13].DB_MAX_OUTPUT_PORT_TYPE +d[14] <= z[14].DB_MAX_OUTPUT_PORT_TYPE +d[15] <= z[15].DB_MAX_OUTPUT_PORT_TYPE +d[16] <= z[16].DB_MAX_OUTPUT_PORT_TYPE +d[17] <= z[17].DB_MAX_OUTPUT_PORT_TYPE +d[18] <= z[18].DB_MAX_OUTPUT_PORT_TYPE +d[19] <= z[19].DB_MAX_OUTPUT_PORT_TYPE +z[0] => d[0].DATAIN +z[1] => d[1].DATAIN +z[2] => d[2].DATAIN +z[3] => d[3].DATAIN +z[4] => d[4].DATAIN +z[5] => d[5].DATAIN +z[6] => d[6].DATAIN +z[7] => d[7].DATAIN +z[8] => d[8].DATAIN +z[9] => d[9].DATAIN +z[10] => d[10].DATAIN +z[11] => d[11].DATAIN +z[12] => d[12].DATAIN +z[13] => d[13].DATAIN +z[14] => d[14].DATAIN +z[15] => d[15].DATAIN +z[16] => d[16].DATAIN +z[17] => d[17].DATAIN +z[18] => d[18].DATAIN +z[19] => d[19].DATAIN + + +|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:mouse_xy_rsc_mgc_in_wire +d[0] <= z[0].DB_MAX_OUTPUT_PORT_TYPE +d[1] <= z[1].DB_MAX_OUTPUT_PORT_TYPE +d[2] <= z[2].DB_MAX_OUTPUT_PORT_TYPE +d[3] <= z[3].DB_MAX_OUTPUT_PORT_TYPE +d[4] <= z[4].DB_MAX_OUTPUT_PORT_TYPE +d[5] <= z[5].DB_MAX_OUTPUT_PORT_TYPE +d[6] <= z[6].DB_MAX_OUTPUT_PORT_TYPE +d[7] <= z[7].DB_MAX_OUTPUT_PORT_TYPE +d[8] <= z[8].DB_MAX_OUTPUT_PORT_TYPE +d[9] <= z[9].DB_MAX_OUTPUT_PORT_TYPE +d[10] <= z[10].DB_MAX_OUTPUT_PORT_TYPE +d[11] <= z[11].DB_MAX_OUTPUT_PORT_TYPE +d[12] <= z[12].DB_MAX_OUTPUT_PORT_TYPE +d[13] <= z[13].DB_MAX_OUTPUT_PORT_TYPE +d[14] <= z[14].DB_MAX_OUTPUT_PORT_TYPE +d[15] <= z[15].DB_MAX_OUTPUT_PORT_TYPE +d[16] <= z[16].DB_MAX_OUTPUT_PORT_TYPE +d[17] <= z[17].DB_MAX_OUTPUT_PORT_TYPE +d[18] <= z[18].DB_MAX_OUTPUT_PORT_TYPE +d[19] <= z[19].DB_MAX_OUTPUT_PORT_TYPE +z[0] => d[0].DATAIN +z[1] => d[1].DATAIN +z[2] => d[2].DATAIN +z[3] => d[3].DATAIN +z[4] => d[4].DATAIN +z[5] => d[5].DATAIN +z[6] => d[6].DATAIN +z[7] => d[7].DATAIN +z[8] => d[8].DATAIN +z[9] => d[9].DATAIN +z[10] => d[10].DATAIN +z[11] => d[11].DATAIN +z[12] => d[12].DATAIN +z[13] => d[13].DATAIN +z[14] => d[14].DATAIN +z[15] => d[15].DATAIN +z[16] => d[16].DATAIN +z[17] => d[17].DATAIN +z[18] => d[18].DATAIN +z[19] => d[19].DATAIN + + +|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:cursor_size_rsc_mgc_in_wire +d[0] <= z[0].DB_MAX_OUTPUT_PORT_TYPE +d[1] <= z[1].DB_MAX_OUTPUT_PORT_TYPE +d[2] <= z[2].DB_MAX_OUTPUT_PORT_TYPE +d[3] <= z[3].DB_MAX_OUTPUT_PORT_TYPE +d[4] <= z[4].DB_MAX_OUTPUT_PORT_TYPE +d[5] <= z[5].DB_MAX_OUTPUT_PORT_TYPE +d[6] <= z[6].DB_MAX_OUTPUT_PORT_TYPE +d[7] <= z[7].DB_MAX_OUTPUT_PORT_TYPE +z[0] => d[0].DATAIN +z[1] => d[1].DATAIN +z[2] => d[2].DATAIN +z[3] => d[3].DATAIN +z[4] => d[4].DATAIN +z[5] => d[5].DATAIN +z[6] => d[6].DATAIN +z[7] => d[7].DATAIN + + +|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:video_in_rsc_mgc_in_wire +d[0] <= z[0].DB_MAX_OUTPUT_PORT_TYPE +d[1] <= z[1].DB_MAX_OUTPUT_PORT_TYPE +d[2] <= z[2].DB_MAX_OUTPUT_PORT_TYPE +d[3] <= z[3].DB_MAX_OUTPUT_PORT_TYPE +d[4] <= z[4].DB_MAX_OUTPUT_PORT_TYPE +d[5] <= z[5].DB_MAX_OUTPUT_PORT_TYPE +d[6] <= z[6].DB_MAX_OUTPUT_PORT_TYPE +d[7] <= z[7].DB_MAX_OUTPUT_PORT_TYPE +d[8] <= z[8].DB_MAX_OUTPUT_PORT_TYPE +d[9] <= z[9].DB_MAX_OUTPUT_PORT_TYPE +d[10] <= z[10].DB_MAX_OUTPUT_PORT_TYPE +d[11] <= z[11].DB_MAX_OUTPUT_PORT_TYPE +d[12] <= z[12].DB_MAX_OUTPUT_PORT_TYPE +d[13] <= z[13].DB_MAX_OUTPUT_PORT_TYPE +d[14] <= z[14].DB_MAX_OUTPUT_PORT_TYPE +d[15] <= z[15].DB_MAX_OUTPUT_PORT_TYPE +d[16] <= z[16].DB_MAX_OUTPUT_PORT_TYPE +d[17] <= z[17].DB_MAX_OUTPUT_PORT_TYPE +d[18] <= z[18].DB_MAX_OUTPUT_PORT_TYPE +d[19] <= z[19].DB_MAX_OUTPUT_PORT_TYPE +d[20] <= z[20].DB_MAX_OUTPUT_PORT_TYPE +d[21] <= z[21].DB_MAX_OUTPUT_PORT_TYPE +d[22] <= z[22].DB_MAX_OUTPUT_PORT_TYPE +d[23] <= z[23].DB_MAX_OUTPUT_PORT_TYPE +d[24] <= z[24].DB_MAX_OUTPUT_PORT_TYPE +d[25] <= z[25].DB_MAX_OUTPUT_PORT_TYPE +d[26] <= z[26].DB_MAX_OUTPUT_PORT_TYPE +d[27] <= z[27].DB_MAX_OUTPUT_PORT_TYPE +d[28] <= z[28].DB_MAX_OUTPUT_PORT_TYPE +d[29] <= z[29].DB_MAX_OUTPUT_PORT_TYPE +z[0] => d[0].DATAIN +z[1] => d[1].DATAIN +z[2] => d[2].DATAIN +z[3] => d[3].DATAIN +z[4] => d[4].DATAIN +z[5] => d[5].DATAIN +z[6] => d[6].DATAIN +z[7] => d[7].DATAIN +z[8] => d[8].DATAIN +z[9] => d[9].DATAIN +z[10] => d[10].DATAIN +z[11] => d[11].DATAIN +z[12] => d[12].DATAIN +z[13] => d[13].DATAIN +z[14] => d[14].DATAIN +z[15] => d[15].DATAIN +z[16] => d[16].DATAIN +z[17] => d[17].DATAIN +z[18] => d[18].DATAIN +z[19] => d[19].DATAIN +z[20] => d[20].DATAIN +z[21] => d[21].DATAIN +z[22] => d[22].DATAIN +z[23] => d[23].DATAIN +z[24] => d[24].DATAIN +z[25] => d[25].DATAIN +z[26] => d[26].DATAIN +z[27] => d[27].DATAIN +z[28] => d[28].DATAIN +z[29] => d[29].DATAIN + + +|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg +d[0] => z[0].DATAIN +d[1] => z[1].DATAIN +d[2] => z[2].DATAIN +d[3] => z[3].DATAIN +d[4] => z[4].DATAIN +d[5] => z[5].DATAIN +d[6] => z[6].DATAIN +d[7] => z[7].DATAIN +d[8] => z[8].DATAIN +d[9] => z[9].DATAIN +d[10] => z[10].DATAIN +d[11] => z[11].DATAIN +d[12] => z[12].DATAIN +d[13] => z[13].DATAIN +d[14] => z[14].DATAIN +d[15] => z[15].DATAIN +d[16] => z[16].DATAIN +d[17] => z[17].DATAIN +d[18] => z[18].DATAIN +d[19] => z[19].DATAIN +d[20] => z[20].DATAIN +d[21] => z[21].DATAIN +d[22] => z[22].DATAIN +d[23] => z[23].DATAIN +d[24] => z[24].DATAIN +d[25] => z[25].DATAIN +d[26] => z[26].DATAIN +d[27] => z[27].DATAIN +d[28] => z[28].DATAIN +d[29] => z[29].DATAIN +z[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE +z[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE +z[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE +z[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE +z[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE +z[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE +z[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE +z[7] <= d[7].DB_MAX_OUTPUT_PORT_TYPE +z[8] <= d[8].DB_MAX_OUTPUT_PORT_TYPE +z[9] <= d[9].DB_MAX_OUTPUT_PORT_TYPE +z[10] <= d[10].DB_MAX_OUTPUT_PORT_TYPE +z[11] <= d[11].DB_MAX_OUTPUT_PORT_TYPE +z[12] <= d[12].DB_MAX_OUTPUT_PORT_TYPE +z[13] <= d[13].DB_MAX_OUTPUT_PORT_TYPE +z[14] <= d[14].DB_MAX_OUTPUT_PORT_TYPE +z[15] <= d[15].DB_MAX_OUTPUT_PORT_TYPE +z[16] <= d[16].DB_MAX_OUTPUT_PORT_TYPE +z[17] <= d[17].DB_MAX_OUTPUT_PORT_TYPE +z[18] <= d[18].DB_MAX_OUTPUT_PORT_TYPE +z[19] <= d[19].DB_MAX_OUTPUT_PORT_TYPE +z[20] <= d[20].DB_MAX_OUTPUT_PORT_TYPE +z[21] <= d[21].DB_MAX_OUTPUT_PORT_TYPE +z[22] <= d[22].DB_MAX_OUTPUT_PORT_TYPE +z[23] <= d[23].DB_MAX_OUTPUT_PORT_TYPE +z[24] <= d[24].DB_MAX_OUTPUT_PORT_TYPE +z[25] <= d[25].DB_MAX_OUTPUT_PORT_TYPE +z[26] <= d[26].DB_MAX_OUTPUT_PORT_TYPE +z[27] <= d[27].DB_MAX_OUTPUT_PORT_TYPE +z[28] <= d[28].DB_MAX_OUTPUT_PORT_TYPE +z[29] <= d[29].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[0].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[1].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[2].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[3].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[4].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[5].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[6].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[7].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[8].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[9].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[0].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[1].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[2].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[3].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[4].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[5].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[0].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[1].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[2].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[3].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[4].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[5].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[6].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[7].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[8].CLK +clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[9].CLK +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[0].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[9].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[8].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[7].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[6].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[5].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[4].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[3].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[2].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[1].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[0].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[5].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[4].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[3].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[2].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[1].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[0].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[9].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[8].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[7].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[6].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[5].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[4].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[3].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[2].ENA +en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[1].ENA +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[0].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[1].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[2].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[3].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[4].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[5].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[6].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[7].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[8].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[9].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[0].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[1].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[2].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[3].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[4].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[5].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[0].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[1].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[2].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[3].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[4].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[5].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[6].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[7].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[8].ACLR +arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[9].ACLR +vga_xy_rsc_mgc_in_wire_d[0] => Add6.IN20 +vga_xy_rsc_mgc_in_wire_d[0] => Add4.IN10 +vga_xy_rsc_mgc_in_wire_d[1] => Add6.IN19 +vga_xy_rsc_mgc_in_wire_d[1] => Add4.IN9 +vga_xy_rsc_mgc_in_wire_d[2] => Add6.IN18 +vga_xy_rsc_mgc_in_wire_d[2] => Add4.IN8 +vga_xy_rsc_mgc_in_wire_d[3] => Add6.IN17 +vga_xy_rsc_mgc_in_wire_d[3] => Add4.IN7 +vga_xy_rsc_mgc_in_wire_d[4] => Add6.IN16 +vga_xy_rsc_mgc_in_wire_d[4] => Add4.IN6 +vga_xy_rsc_mgc_in_wire_d[5] => Add6.IN15 +vga_xy_rsc_mgc_in_wire_d[5] => Add4.IN5 +vga_xy_rsc_mgc_in_wire_d[6] => Add6.IN14 +vga_xy_rsc_mgc_in_wire_d[6] => Add4.IN4 +vga_xy_rsc_mgc_in_wire_d[7] => Add6.IN13 +vga_xy_rsc_mgc_in_wire_d[7] => Add4.IN3 +vga_xy_rsc_mgc_in_wire_d[8] => Add6.IN12 +vga_xy_rsc_mgc_in_wire_d[8] => Add4.IN2 +vga_xy_rsc_mgc_in_wire_d[9] => Add6.IN11 +vga_xy_rsc_mgc_in_wire_d[9] => Add4.IN1 +vga_xy_rsc_mgc_in_wire_d[10] => Add2.IN20 +vga_xy_rsc_mgc_in_wire_d[10] => Add0.IN10 +vga_xy_rsc_mgc_in_wire_d[11] => Add2.IN19 +vga_xy_rsc_mgc_in_wire_d[11] => Add0.IN9 +vga_xy_rsc_mgc_in_wire_d[12] => Add2.IN18 +vga_xy_rsc_mgc_in_wire_d[12] => Add0.IN8 +vga_xy_rsc_mgc_in_wire_d[13] => Add2.IN17 +vga_xy_rsc_mgc_in_wire_d[13] => Add0.IN7 +vga_xy_rsc_mgc_in_wire_d[14] => Add2.IN16 +vga_xy_rsc_mgc_in_wire_d[14] => Add0.IN6 +vga_xy_rsc_mgc_in_wire_d[15] => Add2.IN15 +vga_xy_rsc_mgc_in_wire_d[15] => Add0.IN5 +vga_xy_rsc_mgc_in_wire_d[16] => Add2.IN14 +vga_xy_rsc_mgc_in_wire_d[16] => Add0.IN4 +vga_xy_rsc_mgc_in_wire_d[17] => Add2.IN13 +vga_xy_rsc_mgc_in_wire_d[17] => Add0.IN3 +vga_xy_rsc_mgc_in_wire_d[18] => Add2.IN12 +vga_xy_rsc_mgc_in_wire_d[18] => Add0.IN2 +vga_xy_rsc_mgc_in_wire_d[19] => Add2.IN11 +vga_xy_rsc_mgc_in_wire_d[19] => Add0.IN1 +mouse_xy_rsc_mgc_in_wire_d[0] => Add4.IN20 +mouse_xy_rsc_mgc_in_wire_d[0] => Add6.IN10 +mouse_xy_rsc_mgc_in_wire_d[1] => Add4.IN19 +mouse_xy_rsc_mgc_in_wire_d[1] => Add6.IN9 +mouse_xy_rsc_mgc_in_wire_d[2] => Add4.IN18 +mouse_xy_rsc_mgc_in_wire_d[2] => Add6.IN8 +mouse_xy_rsc_mgc_in_wire_d[3] => Add4.IN17 +mouse_xy_rsc_mgc_in_wire_d[3] => Add6.IN7 +mouse_xy_rsc_mgc_in_wire_d[4] => Add4.IN16 +mouse_xy_rsc_mgc_in_wire_d[4] => Add6.IN6 +mouse_xy_rsc_mgc_in_wire_d[5] => Add4.IN15 +mouse_xy_rsc_mgc_in_wire_d[5] => Add6.IN5 +mouse_xy_rsc_mgc_in_wire_d[6] => Add4.IN14 +mouse_xy_rsc_mgc_in_wire_d[6] => Add6.IN4 +mouse_xy_rsc_mgc_in_wire_d[7] => Add4.IN13 +mouse_xy_rsc_mgc_in_wire_d[7] => Add6.IN3 +mouse_xy_rsc_mgc_in_wire_d[8] => Add4.IN12 +mouse_xy_rsc_mgc_in_wire_d[8] => Add6.IN2 +mouse_xy_rsc_mgc_in_wire_d[9] => Add4.IN11 +mouse_xy_rsc_mgc_in_wire_d[9] => Add6.IN1 +mouse_xy_rsc_mgc_in_wire_d[10] => Add0.IN20 +mouse_xy_rsc_mgc_in_wire_d[10] => Add2.IN10 +mouse_xy_rsc_mgc_in_wire_d[11] => Add0.IN19 +mouse_xy_rsc_mgc_in_wire_d[11] => Add2.IN9 +mouse_xy_rsc_mgc_in_wire_d[12] => Add0.IN18 +mouse_xy_rsc_mgc_in_wire_d[12] => Add2.IN8 +mouse_xy_rsc_mgc_in_wire_d[13] => Add0.IN17 +mouse_xy_rsc_mgc_in_wire_d[13] => Add2.IN7 +mouse_xy_rsc_mgc_in_wire_d[14] => Add0.IN16 +mouse_xy_rsc_mgc_in_wire_d[14] => Add2.IN6 +mouse_xy_rsc_mgc_in_wire_d[15] => Add0.IN15 +mouse_xy_rsc_mgc_in_wire_d[15] => Add2.IN5 +mouse_xy_rsc_mgc_in_wire_d[16] => Add0.IN14 +mouse_xy_rsc_mgc_in_wire_d[16] => Add2.IN4 +mouse_xy_rsc_mgc_in_wire_d[17] => Add0.IN13 +mouse_xy_rsc_mgc_in_wire_d[17] => Add2.IN3 +mouse_xy_rsc_mgc_in_wire_d[18] => Add0.IN12 +mouse_xy_rsc_mgc_in_wire_d[18] => Add2.IN2 +mouse_xy_rsc_mgc_in_wire_d[19] => Add0.IN11 +mouse_xy_rsc_mgc_in_wire_d[19] => Add2.IN1 +cursor_size_rsc_mgc_in_wire_d[0] => Add1.IN22 +cursor_size_rsc_mgc_in_wire_d[0] => Add3.IN22 +cursor_size_rsc_mgc_in_wire_d[0] => Add5.IN22 +cursor_size_rsc_mgc_in_wire_d[0] => Add7.IN22 +cursor_size_rsc_mgc_in_wire_d[1] => Add1.IN21 +cursor_size_rsc_mgc_in_wire_d[1] => Add3.IN21 +cursor_size_rsc_mgc_in_wire_d[1] => Add5.IN21 +cursor_size_rsc_mgc_in_wire_d[1] => Add7.IN21 +cursor_size_rsc_mgc_in_wire_d[2] => Add1.IN20 +cursor_size_rsc_mgc_in_wire_d[2] => Add3.IN20 +cursor_size_rsc_mgc_in_wire_d[2] => Add5.IN20 +cursor_size_rsc_mgc_in_wire_d[2] => Add7.IN20 +cursor_size_rsc_mgc_in_wire_d[3] => Add1.IN19 +cursor_size_rsc_mgc_in_wire_d[3] => Add3.IN19 +cursor_size_rsc_mgc_in_wire_d[3] => Add5.IN19 +cursor_size_rsc_mgc_in_wire_d[3] => Add7.IN19 +cursor_size_rsc_mgc_in_wire_d[4] => Add1.IN18 +cursor_size_rsc_mgc_in_wire_d[4] => Add3.IN18 +cursor_size_rsc_mgc_in_wire_d[4] => Add5.IN18 +cursor_size_rsc_mgc_in_wire_d[4] => Add7.IN18 +cursor_size_rsc_mgc_in_wire_d[5] => Add1.IN17 +cursor_size_rsc_mgc_in_wire_d[5] => Add3.IN17 +cursor_size_rsc_mgc_in_wire_d[5] => Add5.IN17 +cursor_size_rsc_mgc_in_wire_d[5] => Add7.IN17 +cursor_size_rsc_mgc_in_wire_d[6] => Add1.IN16 +cursor_size_rsc_mgc_in_wire_d[6] => Add3.IN16 +cursor_size_rsc_mgc_in_wire_d[6] => Add5.IN16 +cursor_size_rsc_mgc_in_wire_d[6] => Add7.IN16 +cursor_size_rsc_mgc_in_wire_d[7] => Add1.IN15 +cursor_size_rsc_mgc_in_wire_d[7] => Add3.IN15 +cursor_size_rsc_mgc_in_wire_d[7] => Add5.IN15 +cursor_size_rsc_mgc_in_wire_d[7] => Add7.IN15 +video_in_rsc_mgc_in_wire_d[0] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1 +video_in_rsc_mgc_in_wire_d[1] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1 +video_in_rsc_mgc_in_wire_d[2] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1 +video_in_rsc_mgc_in_wire_d[3] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1 +video_in_rsc_mgc_in_wire_d[4] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1 +video_in_rsc_mgc_in_wire_d[5] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1 +video_in_rsc_mgc_in_wire_d[6] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1 +video_in_rsc_mgc_in_wire_d[7] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1 +video_in_rsc_mgc_in_wire_d[8] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1 +video_in_rsc_mgc_in_wire_d[9] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1 +video_in_rsc_mgc_in_wire_d[10] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[0].DATAIN +video_in_rsc_mgc_in_wire_d[11] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[1].DATAIN +video_in_rsc_mgc_in_wire_d[12] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[2].DATAIN +video_in_rsc_mgc_in_wire_d[13] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[3].DATAIN +video_in_rsc_mgc_in_wire_d[14] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[4].DATAIN +video_in_rsc_mgc_in_wire_d[15] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[5].DATAIN +video_in_rsc_mgc_in_wire_d[16] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6].DATAIN +video_in_rsc_mgc_in_wire_d[17] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7].DATAIN +video_in_rsc_mgc_in_wire_d[18] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8].DATAIN +video_in_rsc_mgc_in_wire_d[19] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9].DATAIN +video_in_rsc_mgc_in_wire_d[20] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1 +video_in_rsc_mgc_in_wire_d[21] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1 +video_in_rsc_mgc_in_wire_d[22] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1 +video_in_rsc_mgc_in_wire_d[23] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1 +video_in_rsc_mgc_in_wire_d[24] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1 +video_in_rsc_mgc_in_wire_d[25] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1 +video_in_rsc_mgc_in_wire_d[26] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1 +video_in_rsc_mgc_in_wire_d[27] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1 +video_in_rsc_mgc_in_wire_d[28] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1 +video_in_rsc_mgc_in_wire_d[29] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1 +video_out_rsc_mgc_out_stdreg_d[0] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[0].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[1] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[1].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[2] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[2].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[3] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[3].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[4] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[4].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[5] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[5].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[6] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[6].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[7] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[7].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[8] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[8].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[9] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[9].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[10] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[0].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[11] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[1].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[12] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[2].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[13] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[3].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[14] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[4].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[15] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[5].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[16] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[17] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[18] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[19] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[20] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[0].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[21] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[1].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[22] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[2].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[23] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[3].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[24] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[4].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[25] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[5].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[26] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[6].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[27] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[7].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[28] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[8].DB_MAX_OUTPUT_PORT_TYPE +video_out_rsc_mgc_out_stdreg_d[29] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|sobel:inst1 +vin_rsc_z[0] => vin_rsc_z[0].IN1 +vin_rsc_z[1] => vin_rsc_z[1].IN1 +vin_rsc_z[2] => vin_rsc_z[2].IN1 +vin_rsc_z[3] => vin_rsc_z[3].IN1 +vin_rsc_z[4] => vin_rsc_z[4].IN1 +vin_rsc_z[5] => vin_rsc_z[5].IN1 +vin_rsc_z[6] => vin_rsc_z[6].IN1 +vin_rsc_z[7] => vin_rsc_z[7].IN1 +vin_rsc_z[8] => vin_rsc_z[8].IN1 +vin_rsc_z[9] => vin_rsc_z[9].IN1 +vin_rsc_z[10] => vin_rsc_z[10].IN1 +vin_rsc_z[11] => vin_rsc_z[11].IN1 +vin_rsc_z[12] => vin_rsc_z[12].IN1 +vin_rsc_z[13] => vin_rsc_z[13].IN1 +vin_rsc_z[14] => vin_rsc_z[14].IN1 +vin_rsc_z[15] => vin_rsc_z[15].IN1 +vin_rsc_z[16] => vin_rsc_z[16].IN1 +vin_rsc_z[17] => vin_rsc_z[17].IN1 +vin_rsc_z[18] => vin_rsc_z[18].IN1 +vin_rsc_z[19] => vin_rsc_z[19].IN1 +vin_rsc_z[20] => vin_rsc_z[20].IN1 +vin_rsc_z[21] => vin_rsc_z[21].IN1 +vin_rsc_z[22] => vin_rsc_z[22].IN1 +vin_rsc_z[23] => vin_rsc_z[23].IN1 +vin_rsc_z[24] => vin_rsc_z[24].IN1 +vin_rsc_z[25] => vin_rsc_z[25].IN1 +vin_rsc_z[26] => vin_rsc_z[26].IN1 +vin_rsc_z[27] => vin_rsc_z[27].IN1 +vin_rsc_z[28] => vin_rsc_z[28].IN1 +vin_rsc_z[29] => vin_rsc_z[29].IN1 +vin_rsc_z[30] => vin_rsc_z[30].IN1 +vin_rsc_z[31] => vin_rsc_z[31].IN1 +vin_rsc_z[32] => vin_rsc_z[32].IN1 +vin_rsc_z[33] => vin_rsc_z[33].IN1 +vin_rsc_z[34] => vin_rsc_z[34].IN1 +vin_rsc_z[35] => vin_rsc_z[35].IN1 +vin_rsc_z[36] => vin_rsc_z[36].IN1 +vin_rsc_z[37] => vin_rsc_z[37].IN1 +vin_rsc_z[38] => vin_rsc_z[38].IN1 +vin_rsc_z[39] => vin_rsc_z[39].IN1 +vin_rsc_z[40] => vin_rsc_z[40].IN1 +vin_rsc_z[41] => vin_rsc_z[41].IN1 +vin_rsc_z[42] => vin_rsc_z[42].IN1 +vin_rsc_z[43] => vin_rsc_z[43].IN1 +vin_rsc_z[44] => vin_rsc_z[44].IN1 +vin_rsc_z[45] => vin_rsc_z[45].IN1 +vin_rsc_z[46] => vin_rsc_z[46].IN1 +vin_rsc_z[47] => vin_rsc_z[47].IN1 +vin_rsc_z[48] => vin_rsc_z[48].IN1 +vin_rsc_z[49] => vin_rsc_z[49].IN1 +vin_rsc_z[50] => vin_rsc_z[50].IN1 +vin_rsc_z[51] => vin_rsc_z[51].IN1 +vin_rsc_z[52] => vin_rsc_z[52].IN1 +vin_rsc_z[53] => vin_rsc_z[53].IN1 +vin_rsc_z[54] => vin_rsc_z[54].IN1 +vin_rsc_z[55] => vin_rsc_z[55].IN1 +vin_rsc_z[56] => vin_rsc_z[56].IN1 +vin_rsc_z[57] => vin_rsc_z[57].IN1 +vin_rsc_z[58] => vin_rsc_z[58].IN1 +vin_rsc_z[59] => vin_rsc_z[59].IN1 +vin_rsc_z[60] => vin_rsc_z[60].IN1 +vin_rsc_z[61] => vin_rsc_z[61].IN1 +vin_rsc_z[62] => vin_rsc_z[62].IN1 +vin_rsc_z[63] => vin_rsc_z[63].IN1 +vin_rsc_z[64] => vin_rsc_z[64].IN1 +vin_rsc_z[65] => vin_rsc_z[65].IN1 +vin_rsc_z[66] => vin_rsc_z[66].IN1 +vin_rsc_z[67] => vin_rsc_z[67].IN1 +vin_rsc_z[68] => vin_rsc_z[68].IN1 +vin_rsc_z[69] => vin_rsc_z[69].IN1 +vin_rsc_z[70] => vin_rsc_z[70].IN1 +vin_rsc_z[71] => vin_rsc_z[71].IN1 +vin_rsc_z[72] => vin_rsc_z[72].IN1 +vin_rsc_z[73] => vin_rsc_z[73].IN1 +vin_rsc_z[74] => vin_rsc_z[74].IN1 +vin_rsc_z[75] => vin_rsc_z[75].IN1 +vin_rsc_z[76] => vin_rsc_z[76].IN1 +vin_rsc_z[77] => vin_rsc_z[77].IN1 +vin_rsc_z[78] => vin_rsc_z[78].IN1 +vin_rsc_z[79] => vin_rsc_z[79].IN1 +vin_rsc_z[80] => vin_rsc_z[80].IN1 +vin_rsc_z[81] => vin_rsc_z[81].IN1 +vin_rsc_z[82] => vin_rsc_z[82].IN1 +vin_rsc_z[83] => vin_rsc_z[83].IN1 +vin_rsc_z[84] => vin_rsc_z[84].IN1 +vin_rsc_z[85] => vin_rsc_z[85].IN1 +vin_rsc_z[86] => vin_rsc_z[86].IN1 +vin_rsc_z[87] => vin_rsc_z[87].IN1 +vin_rsc_z[88] => vin_rsc_z[88].IN1 +vin_rsc_z[89] => vin_rsc_z[89].IN1 +vout_rsc_z[0] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[1] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[2] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[3] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[4] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[5] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[6] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[7] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[8] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[9] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[10] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[11] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[12] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[13] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[14] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[15] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[16] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[17] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[18] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[19] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[20] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[21] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[22] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[23] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[24] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[25] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[26] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[27] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[28] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +vout_rsc_z[29] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z +clk => clk.IN1 +en => en.IN1 +arst_n => arst_n.IN1 + + +|TOP_DE0_CAMERA_MOUSE|sobel:inst1|mgc_in_wire:vin_rsc_mgc_in_wire +d[0] <= z[0].DB_MAX_OUTPUT_PORT_TYPE +d[1] <= z[1].DB_MAX_OUTPUT_PORT_TYPE +d[2] <= z[2].DB_MAX_OUTPUT_PORT_TYPE +d[3] <= z[3].DB_MAX_OUTPUT_PORT_TYPE +d[4] <= z[4].DB_MAX_OUTPUT_PORT_TYPE +d[5] <= z[5].DB_MAX_OUTPUT_PORT_TYPE +d[6] <= z[6].DB_MAX_OUTPUT_PORT_TYPE +d[7] <= z[7].DB_MAX_OUTPUT_PORT_TYPE +d[8] <= z[8].DB_MAX_OUTPUT_PORT_TYPE +d[9] <= z[9].DB_MAX_OUTPUT_PORT_TYPE +d[10] <= z[10].DB_MAX_OUTPUT_PORT_TYPE +d[11] <= z[11].DB_MAX_OUTPUT_PORT_TYPE +d[12] <= z[12].DB_MAX_OUTPUT_PORT_TYPE +d[13] <= z[13].DB_MAX_OUTPUT_PORT_TYPE +d[14] <= z[14].DB_MAX_OUTPUT_PORT_TYPE +d[15] <= z[15].DB_MAX_OUTPUT_PORT_TYPE +d[16] <= z[16].DB_MAX_OUTPUT_PORT_TYPE +d[17] <= z[17].DB_MAX_OUTPUT_PORT_TYPE +d[18] <= z[18].DB_MAX_OUTPUT_PORT_TYPE +d[19] <= z[19].DB_MAX_OUTPUT_PORT_TYPE +d[20] <= z[20].DB_MAX_OUTPUT_PORT_TYPE +d[21] <= z[21].DB_MAX_OUTPUT_PORT_TYPE +d[22] <= z[22].DB_MAX_OUTPUT_PORT_TYPE +d[23] <= z[23].DB_MAX_OUTPUT_PORT_TYPE +d[24] <= z[24].DB_MAX_OUTPUT_PORT_TYPE +d[25] <= z[25].DB_MAX_OUTPUT_PORT_TYPE +d[26] <= z[26].DB_MAX_OUTPUT_PORT_TYPE +d[27] <= z[27].DB_MAX_OUTPUT_PORT_TYPE +d[28] <= z[28].DB_MAX_OUTPUT_PORT_TYPE +d[29] <= z[29].DB_MAX_OUTPUT_PORT_TYPE +d[30] <= z[30].DB_MAX_OUTPUT_PORT_TYPE +d[31] <= z[31].DB_MAX_OUTPUT_PORT_TYPE +d[32] <= z[32].DB_MAX_OUTPUT_PORT_TYPE +d[33] <= z[33].DB_MAX_OUTPUT_PORT_TYPE +d[34] <= z[34].DB_MAX_OUTPUT_PORT_TYPE +d[35] <= z[35].DB_MAX_OUTPUT_PORT_TYPE +d[36] <= z[36].DB_MAX_OUTPUT_PORT_TYPE +d[37] <= z[37].DB_MAX_OUTPUT_PORT_TYPE +d[38] <= z[38].DB_MAX_OUTPUT_PORT_TYPE +d[39] <= z[39].DB_MAX_OUTPUT_PORT_TYPE +d[40] <= z[40].DB_MAX_OUTPUT_PORT_TYPE +d[41] <= z[41].DB_MAX_OUTPUT_PORT_TYPE +d[42] <= z[42].DB_MAX_OUTPUT_PORT_TYPE +d[43] <= z[43].DB_MAX_OUTPUT_PORT_TYPE +d[44] <= z[44].DB_MAX_OUTPUT_PORT_TYPE +d[45] <= z[45].DB_MAX_OUTPUT_PORT_TYPE +d[46] <= z[46].DB_MAX_OUTPUT_PORT_TYPE +d[47] <= z[47].DB_MAX_OUTPUT_PORT_TYPE +d[48] <= z[48].DB_MAX_OUTPUT_PORT_TYPE +d[49] <= z[49].DB_MAX_OUTPUT_PORT_TYPE +d[50] <= z[50].DB_MAX_OUTPUT_PORT_TYPE +d[51] <= z[51].DB_MAX_OUTPUT_PORT_TYPE +d[52] <= z[52].DB_MAX_OUTPUT_PORT_TYPE +d[53] <= z[53].DB_MAX_OUTPUT_PORT_TYPE +d[54] <= z[54].DB_MAX_OUTPUT_PORT_TYPE +d[55] <= z[55].DB_MAX_OUTPUT_PORT_TYPE +d[56] <= z[56].DB_MAX_OUTPUT_PORT_TYPE +d[57] <= z[57].DB_MAX_OUTPUT_PORT_TYPE +d[58] <= z[58].DB_MAX_OUTPUT_PORT_TYPE +d[59] <= z[59].DB_MAX_OUTPUT_PORT_TYPE +d[60] <= z[60].DB_MAX_OUTPUT_PORT_TYPE +d[61] <= z[61].DB_MAX_OUTPUT_PORT_TYPE +d[62] <= z[62].DB_MAX_OUTPUT_PORT_TYPE +d[63] <= z[63].DB_MAX_OUTPUT_PORT_TYPE +d[64] <= z[64].DB_MAX_OUTPUT_PORT_TYPE +d[65] <= z[65].DB_MAX_OUTPUT_PORT_TYPE +d[66] <= z[66].DB_MAX_OUTPUT_PORT_TYPE +d[67] <= z[67].DB_MAX_OUTPUT_PORT_TYPE +d[68] <= z[68].DB_MAX_OUTPUT_PORT_TYPE +d[69] <= z[69].DB_MAX_OUTPUT_PORT_TYPE +d[70] <= z[70].DB_MAX_OUTPUT_PORT_TYPE +d[71] <= z[71].DB_MAX_OUTPUT_PORT_TYPE +d[72] <= z[72].DB_MAX_OUTPUT_PORT_TYPE +d[73] <= z[73].DB_MAX_OUTPUT_PORT_TYPE +d[74] <= z[74].DB_MAX_OUTPUT_PORT_TYPE +d[75] <= z[75].DB_MAX_OUTPUT_PORT_TYPE +d[76] <= z[76].DB_MAX_OUTPUT_PORT_TYPE +d[77] <= z[77].DB_MAX_OUTPUT_PORT_TYPE +d[78] <= z[78].DB_MAX_OUTPUT_PORT_TYPE +d[79] <= z[79].DB_MAX_OUTPUT_PORT_TYPE +d[80] <= z[80].DB_MAX_OUTPUT_PORT_TYPE +d[81] <= z[81].DB_MAX_OUTPUT_PORT_TYPE +d[82] <= z[82].DB_MAX_OUTPUT_PORT_TYPE +d[83] <= z[83].DB_MAX_OUTPUT_PORT_TYPE +d[84] <= z[84].DB_MAX_OUTPUT_PORT_TYPE +d[85] <= z[85].DB_MAX_OUTPUT_PORT_TYPE +d[86] <= z[86].DB_MAX_OUTPUT_PORT_TYPE +d[87] <= z[87].DB_MAX_OUTPUT_PORT_TYPE +d[88] <= z[88].DB_MAX_OUTPUT_PORT_TYPE +d[89] <= z[89].DB_MAX_OUTPUT_PORT_TYPE +z[0] => d[0].DATAIN +z[1] => d[1].DATAIN +z[2] => d[2].DATAIN +z[3] => d[3].DATAIN +z[4] => d[4].DATAIN +z[5] => d[5].DATAIN +z[6] => d[6].DATAIN +z[7] => d[7].DATAIN +z[8] => d[8].DATAIN +z[9] => d[9].DATAIN +z[10] => d[10].DATAIN +z[11] => d[11].DATAIN +z[12] => d[12].DATAIN +z[13] => d[13].DATAIN +z[14] => d[14].DATAIN +z[15] => d[15].DATAIN +z[16] => d[16].DATAIN +z[17] => d[17].DATAIN +z[18] => d[18].DATAIN +z[19] => d[19].DATAIN +z[20] => d[20].DATAIN +z[21] => d[21].DATAIN +z[22] => d[22].DATAIN +z[23] => d[23].DATAIN +z[24] => d[24].DATAIN +z[25] => d[25].DATAIN +z[26] => d[26].DATAIN +z[27] => d[27].DATAIN +z[28] => d[28].DATAIN +z[29] => d[29].DATAIN +z[30] => d[30].DATAIN +z[31] => d[31].DATAIN +z[32] => d[32].DATAIN +z[33] => d[33].DATAIN +z[34] => d[34].DATAIN +z[35] => d[35].DATAIN +z[36] => d[36].DATAIN +z[37] => d[37].DATAIN +z[38] => d[38].DATAIN +z[39] => d[39].DATAIN +z[40] => d[40].DATAIN +z[41] => d[41].DATAIN +z[42] => d[42].DATAIN +z[43] => d[43].DATAIN +z[44] => d[44].DATAIN +z[45] => d[45].DATAIN +z[46] => d[46].DATAIN +z[47] => d[47].DATAIN +z[48] => d[48].DATAIN +z[49] => d[49].DATAIN +z[50] => d[50].DATAIN +z[51] => d[51].DATAIN +z[52] => d[52].DATAIN +z[53] => d[53].DATAIN +z[54] => d[54].DATAIN +z[55] => d[55].DATAIN +z[56] => d[56].DATAIN +z[57] => d[57].DATAIN +z[58] => d[58].DATAIN +z[59] => d[59].DATAIN +z[60] => d[60].DATAIN +z[61] => d[61].DATAIN +z[62] => d[62].DATAIN +z[63] => d[63].DATAIN +z[64] => d[64].DATAIN +z[65] => d[65].DATAIN +z[66] => d[66].DATAIN +z[67] => d[67].DATAIN +z[68] => d[68].DATAIN +z[69] => d[69].DATAIN +z[70] => d[70].DATAIN +z[71] => d[71].DATAIN +z[72] => d[72].DATAIN +z[73] => d[73].DATAIN +z[74] => d[74].DATAIN +z[75] => d[75].DATAIN +z[76] => d[76].DATAIN +z[77] => d[77].DATAIN +z[78] => d[78].DATAIN +z[79] => d[79].DATAIN +z[80] => d[80].DATAIN +z[81] => d[81].DATAIN +z[82] => d[82].DATAIN +z[83] => d[83].DATAIN +z[84] => d[84].DATAIN +z[85] => d[85].DATAIN +z[86] => d[86].DATAIN +z[87] => d[87].DATAIN +z[88] => d[88].DATAIN +z[89] => d[89].DATAIN + + +|TOP_DE0_CAMERA_MOUSE|sobel:inst1|mgc_out_stdreg:vout_rsc_mgc_out_stdreg +d[0] => z[0].DATAIN +d[1] => z[1].DATAIN +d[2] => z[2].DATAIN +d[3] => z[3].DATAIN +d[4] => z[4].DATAIN +d[5] => z[5].DATAIN +d[6] => z[6].DATAIN +d[7] => z[7].DATAIN +d[8] => z[8].DATAIN +d[9] => z[9].DATAIN +d[10] => z[10].DATAIN +d[11] => z[11].DATAIN +d[12] => z[12].DATAIN +d[13] => z[13].DATAIN +d[14] => z[14].DATAIN +d[15] => z[15].DATAIN +d[16] => z[16].DATAIN +d[17] => z[17].DATAIN +d[18] => z[18].DATAIN +d[19] => z[19].DATAIN +d[20] => z[20].DATAIN +d[21] => z[21].DATAIN +d[22] => z[22].DATAIN +d[23] => z[23].DATAIN +d[24] => z[24].DATAIN +d[25] => z[25].DATAIN +d[26] => z[26].DATAIN +d[27] => z[27].DATAIN +d[28] => z[28].DATAIN +d[29] => z[29].DATAIN +z[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE +z[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE +z[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE +z[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE +z[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE +z[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE +z[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE +z[7] <= d[7].DB_MAX_OUTPUT_PORT_TYPE +z[8] <= d[8].DB_MAX_OUTPUT_PORT_TYPE +z[9] <= d[9].DB_MAX_OUTPUT_PORT_TYPE +z[10] <= d[10].DB_MAX_OUTPUT_PORT_TYPE +z[11] <= d[11].DB_MAX_OUTPUT_PORT_TYPE +z[12] <= d[12].DB_MAX_OUTPUT_PORT_TYPE +z[13] <= d[13].DB_MAX_OUTPUT_PORT_TYPE +z[14] <= d[14].DB_MAX_OUTPUT_PORT_TYPE +z[15] <= d[15].DB_MAX_OUTPUT_PORT_TYPE +z[16] <= d[16].DB_MAX_OUTPUT_PORT_TYPE +z[17] <= d[17].DB_MAX_OUTPUT_PORT_TYPE +z[18] <= d[18].DB_MAX_OUTPUT_PORT_TYPE +z[19] <= d[19].DB_MAX_OUTPUT_PORT_TYPE +z[20] <= d[20].DB_MAX_OUTPUT_PORT_TYPE +z[21] <= d[21].DB_MAX_OUTPUT_PORT_TYPE +z[22] <= d[22].DB_MAX_OUTPUT_PORT_TYPE +z[23] <= d[23].DB_MAX_OUTPUT_PORT_TYPE +z[24] <= d[24].DB_MAX_OUTPUT_PORT_TYPE +z[25] <= d[25].DB_MAX_OUTPUT_PORT_TYPE +z[26] <= d[26].DB_MAX_OUTPUT_PORT_TYPE +z[27] <= d[27].DB_MAX_OUTPUT_PORT_TYPE +z[28] <= d[28].DB_MAX_OUTPUT_PORT_TYPE +z[29] <= d[29].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst +clk => reg_regs_regs_0_sva_cse[0].CLK +clk => reg_regs_regs_0_sva_cse[1].CLK +clk => reg_regs_regs_0_sva_cse[2].CLK +clk => reg_regs_regs_0_sva_cse[3].CLK +clk => reg_regs_regs_0_sva_cse[4].CLK +clk => reg_regs_regs_0_sva_cse[5].CLK +clk => reg_regs_regs_0_sva_cse[6].CLK +clk => reg_regs_regs_0_sva_cse[7].CLK +clk => reg_regs_regs_0_sva_cse[8].CLK +clk => reg_regs_regs_0_sva_cse[9].CLK +clk => reg_regs_regs_0_sva_cse[10].CLK +clk => reg_regs_regs_0_sva_cse[11].CLK +clk => reg_regs_regs_0_sva_cse[12].CLK +clk => reg_regs_regs_0_sva_cse[13].CLK +clk => reg_regs_regs_0_sva_cse[14].CLK +clk => reg_regs_regs_0_sva_cse[15].CLK +clk => reg_regs_regs_0_sva_cse[16].CLK +clk => reg_regs_regs_0_sva_cse[17].CLK +clk => reg_regs_regs_0_sva_cse[18].CLK +clk => reg_regs_regs_0_sva_cse[19].CLK +clk => reg_regs_regs_0_sva_cse[20].CLK +clk => reg_regs_regs_0_sva_cse[21].CLK +clk => reg_regs_regs_0_sva_cse[22].CLK +clk => reg_regs_regs_0_sva_cse[23].CLK +clk => reg_regs_regs_0_sva_cse[24].CLK +clk => reg_regs_regs_0_sva_cse[25].CLK +clk => reg_regs_regs_0_sva_cse[26].CLK +clk => reg_regs_regs_0_sva_cse[27].CLK +clk => reg_regs_regs_0_sva_cse[28].CLK +clk => reg_regs_regs_0_sva_cse[29].CLK +clk => reg_regs_regs_0_sva_cse[30].CLK +clk => reg_regs_regs_0_sva_cse[31].CLK +clk => reg_regs_regs_0_sva_cse[32].CLK +clk => reg_regs_regs_0_sva_cse[33].CLK +clk => reg_regs_regs_0_sva_cse[34].CLK +clk => reg_regs_regs_0_sva_cse[35].CLK +clk => reg_regs_regs_0_sva_cse[36].CLK +clk => reg_regs_regs_0_sva_cse[37].CLK +clk => reg_regs_regs_0_sva_cse[38].CLK +clk => reg_regs_regs_0_sva_cse[39].CLK +clk => reg_regs_regs_0_sva_cse[40].CLK +clk => reg_regs_regs_0_sva_cse[41].CLK +clk => reg_regs_regs_0_sva_cse[42].CLK +clk => reg_regs_regs_0_sva_cse[43].CLK +clk => reg_regs_regs_0_sva_cse[44].CLK +clk => reg_regs_regs_0_sva_cse[45].CLK +clk => reg_regs_regs_0_sva_cse[46].CLK +clk => reg_regs_regs_0_sva_cse[47].CLK +clk => reg_regs_regs_0_sva_cse[48].CLK +clk => reg_regs_regs_0_sva_cse[49].CLK +clk => reg_regs_regs_0_sva_cse[50].CLK +clk => reg_regs_regs_0_sva_cse[51].CLK +clk => reg_regs_regs_0_sva_cse[52].CLK +clk => reg_regs_regs_0_sva_cse[53].CLK +clk => reg_regs_regs_0_sva_cse[54].CLK +clk => reg_regs_regs_0_sva_cse[55].CLK +clk => reg_regs_regs_0_sva_cse[56].CLK +clk => reg_regs_regs_0_sva_cse[57].CLK +clk => reg_regs_regs_0_sva_cse[58].CLK +clk => reg_regs_regs_0_sva_cse[59].CLK +clk => reg_regs_regs_0_sva_cse[60].CLK +clk => reg_regs_regs_0_sva_cse[61].CLK +clk => reg_regs_regs_0_sva_cse[62].CLK +clk => reg_regs_regs_0_sva_cse[63].CLK +clk => reg_regs_regs_0_sva_cse[64].CLK +clk => reg_regs_regs_0_sva_cse[65].CLK +clk => reg_regs_regs_0_sva_cse[66].CLK +clk => reg_regs_regs_0_sva_cse[67].CLK +clk => reg_regs_regs_0_sva_cse[68].CLK +clk => reg_regs_regs_0_sva_cse[69].CLK +clk => reg_regs_regs_0_sva_cse[70].CLK +clk => reg_regs_regs_0_sva_cse[71].CLK +clk => reg_regs_regs_0_sva_cse[72].CLK +clk => reg_regs_regs_0_sva_cse[73].CLK +clk => reg_regs_regs_0_sva_cse[74].CLK +clk => reg_regs_regs_0_sva_cse[75].CLK +clk => reg_regs_regs_0_sva_cse[76].CLK +clk => reg_regs_regs_0_sva_cse[77].CLK +clk => reg_regs_regs_0_sva_cse[78].CLK +clk => reg_regs_regs_0_sva_cse[79].CLK +clk => reg_regs_regs_0_sva_cse[80].CLK +clk => reg_regs_regs_0_sva_cse[81].CLK +clk => reg_regs_regs_0_sva_cse[82].CLK +clk => reg_regs_regs_0_sva_cse[83].CLK +clk => reg_regs_regs_0_sva_cse[84].CLK +clk => reg_regs_regs_0_sva_cse[85].CLK +clk => reg_regs_regs_0_sva_cse[86].CLK +clk => reg_regs_regs_0_sva_cse[87].CLK +clk => reg_regs_regs_0_sva_cse[88].CLK +clk => reg_regs_regs_0_sva_cse[89].CLK +clk => regs_regs_slc_regs_regs_2_2_itm[0].CLK +clk => regs_regs_slc_regs_regs_2_2_itm[1].CLK +clk => regs_regs_slc_regs_regs_2_2_itm[2].CLK +clk => regs_regs_slc_regs_regs_2_2_itm[3].CLK +clk => regs_regs_slc_regs_regs_2_2_itm[4].CLK +clk => regs_regs_slc_regs_regs_2_2_itm[5].CLK +clk => regs_regs_slc_regs_regs_2_2_itm[6].CLK +clk => regs_regs_slc_regs_regs_2_2_itm[7].CLK +clk => regs_regs_slc_regs_regs_2_2_itm[8].CLK +clk => regs_regs_slc_regs_regs_2_2_itm[9].CLK +clk => regs_regs_slc_regs_regs_2_1_itm[0].CLK +clk => regs_regs_slc_regs_regs_2_1_itm[1].CLK +clk => regs_regs_slc_regs_regs_2_1_itm[2].CLK +clk => regs_regs_slc_regs_regs_2_1_itm[3].CLK +clk => regs_regs_slc_regs_regs_2_1_itm[4].CLK +clk => regs_regs_slc_regs_regs_2_1_itm[5].CLK +clk => regs_regs_slc_regs_regs_2_1_itm[6].CLK +clk => regs_regs_slc_regs_regs_2_1_itm[7].CLK +clk => regs_regs_slc_regs_regs_2_1_itm[8].CLK +clk => regs_regs_slc_regs_regs_2_1_itm[9].CLK +clk => regs_regs_slc_regs_regs_2_itm[0].CLK +clk => regs_regs_slc_regs_regs_2_itm[1].CLK +clk => regs_regs_slc_regs_regs_2_itm[2].CLK +clk => regs_regs_slc_regs_regs_2_itm[3].CLK +clk => regs_regs_slc_regs_regs_2_itm[4].CLK +clk => regs_regs_slc_regs_regs_2_itm[5].CLK +clk => regs_regs_slc_regs_regs_2_itm[6].CLK +clk => regs_regs_slc_regs_regs_2_itm[7].CLK +clk => regs_regs_slc_regs_regs_2_itm[8].CLK +clk => regs_regs_slc_regs_regs_2_itm[9].CLK +clk => regs_regs_slc_regs_regs_2_3_itm[0].CLK +clk => regs_regs_slc_regs_regs_2_3_itm[1].CLK +clk => regs_regs_slc_regs_regs_2_3_itm[2].CLK +clk => regs_regs_slc_regs_regs_2_3_itm[3].CLK +clk => regs_regs_slc_regs_regs_2_3_itm[4].CLK +clk => regs_regs_slc_regs_regs_2_3_itm[5].CLK +clk => regs_regs_slc_regs_regs_2_3_itm[6].CLK +clk => regs_regs_slc_regs_regs_2_3_itm[7].CLK +clk => regs_regs_slc_regs_regs_2_3_itm[8].CLK +clk => regs_regs_slc_regs_regs_2_3_itm[9].CLK +clk => regs_regs_slc_regs_regs_2_5_itm[0].CLK +clk => regs_regs_slc_regs_regs_2_5_itm[1].CLK +clk => regs_regs_slc_regs_regs_2_5_itm[2].CLK +clk => regs_regs_slc_regs_regs_2_5_itm[3].CLK +clk => regs_regs_slc_regs_regs_2_5_itm[4].CLK +clk => regs_regs_slc_regs_regs_2_5_itm[5].CLK +clk => regs_regs_slc_regs_regs_2_5_itm[6].CLK +clk => regs_regs_slc_regs_regs_2_5_itm[7].CLK +clk => regs_regs_slc_regs_regs_2_5_itm[8].CLK +clk => regs_regs_slc_regs_regs_2_5_itm[9].CLK +clk => regs_regs_slc_regs_regs_2_4_itm[0].CLK +clk => regs_regs_slc_regs_regs_2_4_itm[1].CLK +clk => regs_regs_slc_regs_regs_2_4_itm[2].CLK +clk => regs_regs_slc_regs_regs_2_4_itm[3].CLK +clk => regs_regs_slc_regs_regs_2_4_itm[4].CLK +clk => regs_regs_slc_regs_regs_2_4_itm[5].CLK +clk => regs_regs_slc_regs_regs_2_4_itm[6].CLK +clk => regs_regs_slc_regs_regs_2_4_itm[7].CLK +clk => regs_regs_slc_regs_regs_2_4_itm[8].CLK +clk => regs_regs_slc_regs_regs_2_4_itm[9].CLK +clk => regs_regs_slc_regs_regs_2_9_itm[0].CLK +clk => regs_regs_slc_regs_regs_2_9_itm[1].CLK +clk => regs_regs_slc_regs_regs_2_9_itm[2].CLK +clk => regs_regs_slc_regs_regs_2_9_itm[3].CLK +clk => regs_regs_slc_regs_regs_2_9_itm[4].CLK +clk => regs_regs_slc_regs_regs_2_9_itm[5].CLK +clk => regs_regs_slc_regs_regs_2_9_itm[6].CLK +clk => regs_regs_slc_regs_regs_2_9_itm[7].CLK +clk => regs_regs_slc_regs_regs_2_9_itm[8].CLK +clk => regs_regs_slc_regs_regs_2_9_itm[9].CLK +clk => regs_regs_slc_regs_regs_2_11_itm[0].CLK +clk => regs_regs_slc_regs_regs_2_11_itm[1].CLK +clk => regs_regs_slc_regs_regs_2_11_itm[2].CLK +clk => regs_regs_slc_regs_regs_2_11_itm[3].CLK +clk => regs_regs_slc_regs_regs_2_11_itm[4].CLK +clk => regs_regs_slc_regs_regs_2_11_itm[5].CLK +clk => regs_regs_slc_regs_regs_2_11_itm[6].CLK +clk => regs_regs_slc_regs_regs_2_11_itm[7].CLK +clk => regs_regs_slc_regs_regs_2_11_itm[8].CLK +clk => regs_regs_slc_regs_regs_2_11_itm[9].CLK +clk => regs_regs_slc_regs_regs_2_10_itm[0].CLK +clk => regs_regs_slc_regs_regs_2_10_itm[1].CLK +clk => regs_regs_slc_regs_regs_2_10_itm[2].CLK +clk => regs_regs_slc_regs_regs_2_10_itm[3].CLK +clk => regs_regs_slc_regs_regs_2_10_itm[4].CLK +clk => regs_regs_slc_regs_regs_2_10_itm[5].CLK +clk => regs_regs_slc_regs_regs_2_10_itm[6].CLK +clk => regs_regs_slc_regs_regs_2_10_itm[7].CLK +clk => regs_regs_slc_regs_regs_2_10_itm[8].CLK +clk => regs_regs_slc_regs_regs_2_10_itm[9].CLK +clk => main_stage_0_2.CLK +clk => ACC1_acc_655_itm_1[0].CLK +clk => ACC1_acc_655_itm_1[1].CLK +clk => ACC1_acc_655_itm_1[2].CLK +clk => ACC1_acc_655_itm_1[3].CLK +clk => ACC1_acc_655_itm_1[4].CLK +clk => ACC1_acc_655_itm_1[5].CLK +clk => ACC1_acc_655_itm_1[6].CLK +clk => ACC1_acc_655_itm_1[7].CLK +clk => ACC1_acc_655_itm_1[8].CLK +clk => ACC1_acc_655_itm_1[9].CLK +clk => ACC1_acc_655_itm_1[10].CLK +clk => ACC1_acc_655_itm_1[11].CLK +clk => ACC1_acc_652_itm_1[0].CLK +clk => ACC1_acc_652_itm_1[1].CLK +clk => ACC1_acc_652_itm_1[2].CLK +clk => ACC1_acc_652_itm_1[3].CLK +clk => ACC1_acc_652_itm_1[4].CLK +clk => ACC1_acc_652_itm_1[5].CLK +clk => ACC1_acc_652_itm_1[6].CLK +clk => ACC1_acc_652_itm_1[7].CLK +clk => ACC1_acc_652_itm_1[8].CLK +clk => ACC1_acc_652_itm_1[9].CLK +clk => ACC1_acc_652_itm_1[10].CLK +clk => ACC1_3_slc_acc_10_psp_62_itm_1.CLK +clk => ACC1_slc_ACC1_acc_228_psp_55_itm_1.CLK +clk => slc_acc_20_psp_1_93_itm_1.CLK +clk => ACC1_mul_57_itm_2[0].CLK +clk => ACC1_mul_57_itm_2[1].CLK +clk => ACC1_mul_57_itm_1_sg2[0].CLK +clk => ACC1_mul_57_itm_1_sg2[1].CLK +clk => ACC1_mul_57_itm_1_sg2[2].CLK +clk => ACC1_mul_57_itm_1_sg2[3].CLK +clk => ACC1_mul_57_itm_1_sg2[4].CLK +clk => ACC1_acc_661_itm_1[0].CLK +clk => ACC1_acc_661_itm_1[1].CLK +clk => ACC1_acc_661_itm_1[2].CLK +clk => ACC1_acc_661_itm_1[3].CLK +clk => ACC1_acc_661_itm_1[4].CLK +clk => ACC1_acc_661_itm_1[5].CLK +clk => ACC1_acc_661_itm_1[6].CLK +clk => ACC1_acc_661_itm_1[7].CLK +clk => ACC1_acc_661_itm_1[8].CLK +clk => ACC1_acc_661_itm_1[9].CLK +clk => ACC1_acc_661_itm_1[10].CLK +clk => ACC1_acc_661_itm_1[11].CLK +clk => ACC1_acc_661_itm_1[12].CLK +clk => ACC1_acc_661_itm_1[13].CLK +clk => ACC1_acc_658_itm_1[0].CLK +clk => ACC1_acc_658_itm_1[1].CLK +clk => ACC1_acc_658_itm_1[2].CLK +clk => ACC1_acc_658_itm_1[3].CLK +clk => ACC1_acc_658_itm_1[4].CLK +clk => ACC1_acc_658_itm_1[5].CLK +clk => ACC1_acc_658_itm_1[6].CLK +clk => ACC1_acc_658_itm_1[7].CLK +clk => ACC1_acc_658_itm_1[8].CLK +clk => ACC1_acc_658_itm_1[9].CLK +clk => ACC1_acc_658_itm_1[10].CLK +clk => ACC1_acc_658_itm_1[11].CLK +clk => ACC1_acc_658_itm_1[12].CLK +clk => ACC1_acc_659_itm_1[0].CLK +clk => ACC1_acc_659_itm_1[1].CLK +clk => ACC1_acc_659_itm_1[2].CLK +clk => ACC1_acc_659_itm_1[3].CLK +clk => ACC1_acc_659_itm_1[4].CLK +clk => ACC1_acc_659_itm_1[5].CLK +clk => ACC1_acc_659_itm_1[6].CLK +clk => ACC1_acc_659_itm_1[7].CLK +clk => ACC1_acc_659_itm_1[8].CLK +clk => ACC1_acc_659_itm_1[9].CLK +clk => ACC1_acc_659_itm_1[10].CLK +clk => ACC1_acc_659_itm_1[11].CLK +clk => ACC1_acc_659_itm_1[12].CLK +clk => vout_rsc_mgc_out_stdreg_d[0]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[1]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[2]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[3]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[4]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[5]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[6]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[7]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[8]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[9]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[10]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[11]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[12]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[13]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[14]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[15]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[16]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[17]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[18]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[19]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[20]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[21]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[22]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[23]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[24]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[25]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[26]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[27]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[28]~reg0.CLK +clk => vout_rsc_mgc_out_stdreg_d[29]~reg0.CLK +en => reg_regs_regs_0_sva_cse[0].ENA +en => vout_rsc_mgc_out_stdreg_d[29]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[28]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[27]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[26]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[25]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[24]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[23]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[22]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[21]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[20]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[19]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[18]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[17]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[16]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[15]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[14]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[13]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[12]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[11]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[10]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[9]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[8]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[7]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[6]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[5]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[4]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[3]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[2]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[1]~reg0.ENA +en => vout_rsc_mgc_out_stdreg_d[0]~reg0.ENA +en => ACC1_acc_659_itm_1[12].ENA +en => ACC1_acc_659_itm_1[11].ENA +en => ACC1_acc_659_itm_1[10].ENA +en => ACC1_acc_659_itm_1[9].ENA +en => ACC1_acc_659_itm_1[8].ENA +en => ACC1_acc_659_itm_1[7].ENA +en => ACC1_acc_659_itm_1[6].ENA +en => ACC1_acc_659_itm_1[5].ENA +en => ACC1_acc_659_itm_1[4].ENA +en => ACC1_acc_659_itm_1[3].ENA +en => ACC1_acc_659_itm_1[2].ENA +en => ACC1_acc_659_itm_1[1].ENA +en => ACC1_acc_659_itm_1[0].ENA +en => ACC1_acc_658_itm_1[12].ENA +en => ACC1_acc_658_itm_1[11].ENA +en => ACC1_acc_658_itm_1[10].ENA +en => ACC1_acc_658_itm_1[9].ENA +en => ACC1_acc_658_itm_1[8].ENA +en => ACC1_acc_658_itm_1[7].ENA +en => ACC1_acc_658_itm_1[6].ENA +en => ACC1_acc_658_itm_1[5].ENA +en => ACC1_acc_658_itm_1[4].ENA +en => ACC1_acc_658_itm_1[3].ENA +en => ACC1_acc_658_itm_1[2].ENA +en => ACC1_acc_658_itm_1[1].ENA +en => ACC1_acc_658_itm_1[0].ENA +en => ACC1_acc_661_itm_1[13].ENA +en => ACC1_acc_661_itm_1[12].ENA +en => ACC1_acc_661_itm_1[11].ENA +en => ACC1_acc_661_itm_1[10].ENA +en => ACC1_acc_661_itm_1[9].ENA +en => ACC1_acc_661_itm_1[8].ENA +en => ACC1_acc_661_itm_1[7].ENA +en => ACC1_acc_661_itm_1[6].ENA +en => ACC1_acc_661_itm_1[5].ENA +en => ACC1_acc_661_itm_1[4].ENA +en => ACC1_acc_661_itm_1[3].ENA +en => ACC1_acc_661_itm_1[2].ENA +en => ACC1_acc_661_itm_1[1].ENA +en => ACC1_acc_661_itm_1[0].ENA +en => ACC1_mul_57_itm_1_sg2[4].ENA +en => ACC1_mul_57_itm_1_sg2[3].ENA +en => ACC1_mul_57_itm_1_sg2[2].ENA +en => ACC1_mul_57_itm_1_sg2[1].ENA +en => ACC1_mul_57_itm_1_sg2[0].ENA +en => ACC1_mul_57_itm_2[1].ENA +en => ACC1_mul_57_itm_2[0].ENA +en => slc_acc_20_psp_1_93_itm_1.ENA +en => ACC1_slc_ACC1_acc_228_psp_55_itm_1.ENA +en => ACC1_3_slc_acc_10_psp_62_itm_1.ENA +en => ACC1_acc_652_itm_1[10].ENA +en => ACC1_acc_652_itm_1[9].ENA +en => ACC1_acc_652_itm_1[8].ENA +en => ACC1_acc_652_itm_1[7].ENA +en => ACC1_acc_652_itm_1[6].ENA +en => ACC1_acc_652_itm_1[5].ENA +en => ACC1_acc_652_itm_1[4].ENA +en => ACC1_acc_652_itm_1[3].ENA +en => ACC1_acc_652_itm_1[2].ENA +en => ACC1_acc_652_itm_1[1].ENA +en => ACC1_acc_652_itm_1[0].ENA +en => ACC1_acc_655_itm_1[11].ENA +en => ACC1_acc_655_itm_1[10].ENA +en => ACC1_acc_655_itm_1[9].ENA +en => ACC1_acc_655_itm_1[8].ENA +en => ACC1_acc_655_itm_1[7].ENA +en => ACC1_acc_655_itm_1[6].ENA +en => ACC1_acc_655_itm_1[5].ENA +en => ACC1_acc_655_itm_1[4].ENA +en => ACC1_acc_655_itm_1[3].ENA +en => ACC1_acc_655_itm_1[2].ENA +en => ACC1_acc_655_itm_1[1].ENA +en => ACC1_acc_655_itm_1[0].ENA +en => main_stage_0_2.ENA +en => regs_regs_slc_regs_regs_2_10_itm[9].ENA +en => regs_regs_slc_regs_regs_2_10_itm[8].ENA +en => regs_regs_slc_regs_regs_2_10_itm[7].ENA +en => regs_regs_slc_regs_regs_2_10_itm[6].ENA +en => regs_regs_slc_regs_regs_2_10_itm[5].ENA +en => regs_regs_slc_regs_regs_2_10_itm[4].ENA +en => regs_regs_slc_regs_regs_2_10_itm[3].ENA +en => regs_regs_slc_regs_regs_2_10_itm[2].ENA +en => regs_regs_slc_regs_regs_2_10_itm[1].ENA +en => regs_regs_slc_regs_regs_2_10_itm[0].ENA +en => regs_regs_slc_regs_regs_2_11_itm[9].ENA +en => regs_regs_slc_regs_regs_2_11_itm[8].ENA +en => regs_regs_slc_regs_regs_2_11_itm[7].ENA +en => regs_regs_slc_regs_regs_2_11_itm[6].ENA +en => regs_regs_slc_regs_regs_2_11_itm[5].ENA +en => regs_regs_slc_regs_regs_2_11_itm[4].ENA +en => regs_regs_slc_regs_regs_2_11_itm[3].ENA +en => regs_regs_slc_regs_regs_2_11_itm[2].ENA +en => regs_regs_slc_regs_regs_2_11_itm[1].ENA +en => regs_regs_slc_regs_regs_2_11_itm[0].ENA +en => regs_regs_slc_regs_regs_2_9_itm[9].ENA +en => regs_regs_slc_regs_regs_2_9_itm[8].ENA +en => regs_regs_slc_regs_regs_2_9_itm[7].ENA +en => regs_regs_slc_regs_regs_2_9_itm[6].ENA +en => regs_regs_slc_regs_regs_2_9_itm[5].ENA +en => regs_regs_slc_regs_regs_2_9_itm[4].ENA +en => regs_regs_slc_regs_regs_2_9_itm[3].ENA +en => regs_regs_slc_regs_regs_2_9_itm[2].ENA +en => regs_regs_slc_regs_regs_2_9_itm[1].ENA +en => regs_regs_slc_regs_regs_2_9_itm[0].ENA +en => regs_regs_slc_regs_regs_2_4_itm[9].ENA +en => regs_regs_slc_regs_regs_2_4_itm[8].ENA +en => regs_regs_slc_regs_regs_2_4_itm[7].ENA +en => regs_regs_slc_regs_regs_2_4_itm[6].ENA +en => regs_regs_slc_regs_regs_2_4_itm[5].ENA +en => regs_regs_slc_regs_regs_2_4_itm[4].ENA +en => regs_regs_slc_regs_regs_2_4_itm[3].ENA +en => regs_regs_slc_regs_regs_2_4_itm[2].ENA +en => regs_regs_slc_regs_regs_2_4_itm[1].ENA +en => regs_regs_slc_regs_regs_2_4_itm[0].ENA +en => regs_regs_slc_regs_regs_2_5_itm[9].ENA +en => regs_regs_slc_regs_regs_2_5_itm[8].ENA +en => regs_regs_slc_regs_regs_2_5_itm[7].ENA +en => regs_regs_slc_regs_regs_2_5_itm[6].ENA +en => regs_regs_slc_regs_regs_2_5_itm[5].ENA +en => regs_regs_slc_regs_regs_2_5_itm[4].ENA +en => regs_regs_slc_regs_regs_2_5_itm[3].ENA +en => regs_regs_slc_regs_regs_2_5_itm[2].ENA +en => regs_regs_slc_regs_regs_2_5_itm[1].ENA +en => regs_regs_slc_regs_regs_2_5_itm[0].ENA +en => regs_regs_slc_regs_regs_2_3_itm[9].ENA +en => regs_regs_slc_regs_regs_2_3_itm[8].ENA +en => regs_regs_slc_regs_regs_2_3_itm[7].ENA +en => regs_regs_slc_regs_regs_2_3_itm[6].ENA +en => regs_regs_slc_regs_regs_2_3_itm[5].ENA +en => regs_regs_slc_regs_regs_2_3_itm[4].ENA +en => regs_regs_slc_regs_regs_2_3_itm[3].ENA +en => regs_regs_slc_regs_regs_2_3_itm[2].ENA +en => regs_regs_slc_regs_regs_2_3_itm[1].ENA +en => regs_regs_slc_regs_regs_2_3_itm[0].ENA +en => regs_regs_slc_regs_regs_2_itm[9].ENA +en => regs_regs_slc_regs_regs_2_itm[8].ENA +en => regs_regs_slc_regs_regs_2_itm[7].ENA +en => regs_regs_slc_regs_regs_2_itm[6].ENA +en => regs_regs_slc_regs_regs_2_itm[5].ENA +en => regs_regs_slc_regs_regs_2_itm[4].ENA +en => regs_regs_slc_regs_regs_2_itm[3].ENA +en => regs_regs_slc_regs_regs_2_itm[2].ENA +en => regs_regs_slc_regs_regs_2_itm[1].ENA +en => regs_regs_slc_regs_regs_2_itm[0].ENA +en => regs_regs_slc_regs_regs_2_1_itm[9].ENA +en => regs_regs_slc_regs_regs_2_1_itm[8].ENA +en => regs_regs_slc_regs_regs_2_1_itm[7].ENA +en => regs_regs_slc_regs_regs_2_1_itm[6].ENA +en => regs_regs_slc_regs_regs_2_1_itm[5].ENA +en => regs_regs_slc_regs_regs_2_1_itm[4].ENA +en => regs_regs_slc_regs_regs_2_1_itm[3].ENA +en => regs_regs_slc_regs_regs_2_1_itm[2].ENA +en => regs_regs_slc_regs_regs_2_1_itm[1].ENA +en => regs_regs_slc_regs_regs_2_1_itm[0].ENA +en => regs_regs_slc_regs_regs_2_2_itm[9].ENA +en => regs_regs_slc_regs_regs_2_2_itm[8].ENA +en => regs_regs_slc_regs_regs_2_2_itm[7].ENA +en => regs_regs_slc_regs_regs_2_2_itm[6].ENA +en => regs_regs_slc_regs_regs_2_2_itm[5].ENA +en => regs_regs_slc_regs_regs_2_2_itm[4].ENA +en => regs_regs_slc_regs_regs_2_2_itm[3].ENA +en => regs_regs_slc_regs_regs_2_2_itm[2].ENA +en => regs_regs_slc_regs_regs_2_2_itm[1].ENA +en => regs_regs_slc_regs_regs_2_2_itm[0].ENA +en => reg_regs_regs_0_sva_cse[89].ENA +en => reg_regs_regs_0_sva_cse[88].ENA +en => reg_regs_regs_0_sva_cse[87].ENA +en => reg_regs_regs_0_sva_cse[86].ENA +en => reg_regs_regs_0_sva_cse[85].ENA +en => reg_regs_regs_0_sva_cse[84].ENA +en => reg_regs_regs_0_sva_cse[83].ENA +en => reg_regs_regs_0_sva_cse[82].ENA +en => reg_regs_regs_0_sva_cse[81].ENA +en => reg_regs_regs_0_sva_cse[80].ENA +en => reg_regs_regs_0_sva_cse[79].ENA +en => reg_regs_regs_0_sva_cse[78].ENA +en => reg_regs_regs_0_sva_cse[77].ENA +en => reg_regs_regs_0_sva_cse[76].ENA +en => reg_regs_regs_0_sva_cse[75].ENA +en => reg_regs_regs_0_sva_cse[74].ENA +en => reg_regs_regs_0_sva_cse[73].ENA +en => reg_regs_regs_0_sva_cse[72].ENA +en => reg_regs_regs_0_sva_cse[71].ENA +en => reg_regs_regs_0_sva_cse[70].ENA +en => reg_regs_regs_0_sva_cse[69].ENA +en => reg_regs_regs_0_sva_cse[68].ENA +en => reg_regs_regs_0_sva_cse[67].ENA +en => reg_regs_regs_0_sva_cse[66].ENA +en => reg_regs_regs_0_sva_cse[65].ENA +en => reg_regs_regs_0_sva_cse[64].ENA +en => reg_regs_regs_0_sva_cse[63].ENA +en => reg_regs_regs_0_sva_cse[62].ENA +en => reg_regs_regs_0_sva_cse[61].ENA +en => reg_regs_regs_0_sva_cse[60].ENA +en => reg_regs_regs_0_sva_cse[59].ENA +en => reg_regs_regs_0_sva_cse[58].ENA +en => reg_regs_regs_0_sva_cse[57].ENA +en => reg_regs_regs_0_sva_cse[56].ENA +en => reg_regs_regs_0_sva_cse[55].ENA +en => reg_regs_regs_0_sva_cse[54].ENA +en => reg_regs_regs_0_sva_cse[53].ENA +en => reg_regs_regs_0_sva_cse[52].ENA +en => reg_regs_regs_0_sva_cse[51].ENA +en => reg_regs_regs_0_sva_cse[50].ENA +en => reg_regs_regs_0_sva_cse[49].ENA +en => reg_regs_regs_0_sva_cse[48].ENA +en => reg_regs_regs_0_sva_cse[47].ENA +en => reg_regs_regs_0_sva_cse[46].ENA +en => reg_regs_regs_0_sva_cse[45].ENA +en => reg_regs_regs_0_sva_cse[44].ENA +en => reg_regs_regs_0_sva_cse[43].ENA +en => reg_regs_regs_0_sva_cse[42].ENA +en => reg_regs_regs_0_sva_cse[41].ENA +en => reg_regs_regs_0_sva_cse[40].ENA +en => reg_regs_regs_0_sva_cse[39].ENA +en => reg_regs_regs_0_sva_cse[38].ENA +en => reg_regs_regs_0_sva_cse[37].ENA +en => reg_regs_regs_0_sva_cse[36].ENA +en => reg_regs_regs_0_sva_cse[35].ENA +en => reg_regs_regs_0_sva_cse[34].ENA +en => reg_regs_regs_0_sva_cse[33].ENA +en => reg_regs_regs_0_sva_cse[32].ENA +en => reg_regs_regs_0_sva_cse[31].ENA +en => reg_regs_regs_0_sva_cse[30].ENA +en => reg_regs_regs_0_sva_cse[29].ENA +en => reg_regs_regs_0_sva_cse[28].ENA +en => reg_regs_regs_0_sva_cse[27].ENA +en => reg_regs_regs_0_sva_cse[26].ENA +en => reg_regs_regs_0_sva_cse[25].ENA +en => reg_regs_regs_0_sva_cse[24].ENA +en => reg_regs_regs_0_sva_cse[23].ENA +en => reg_regs_regs_0_sva_cse[22].ENA +en => reg_regs_regs_0_sva_cse[21].ENA +en => reg_regs_regs_0_sva_cse[20].ENA +en => reg_regs_regs_0_sva_cse[19].ENA +en => reg_regs_regs_0_sva_cse[18].ENA +en => reg_regs_regs_0_sva_cse[17].ENA +en => reg_regs_regs_0_sva_cse[16].ENA +en => reg_regs_regs_0_sva_cse[15].ENA +en => reg_regs_regs_0_sva_cse[14].ENA +en => reg_regs_regs_0_sva_cse[13].ENA +en => reg_regs_regs_0_sva_cse[12].ENA +en => reg_regs_regs_0_sva_cse[11].ENA +en => reg_regs_regs_0_sva_cse[10].ENA +en => reg_regs_regs_0_sva_cse[9].ENA +en => reg_regs_regs_0_sva_cse[8].ENA +en => reg_regs_regs_0_sva_cse[7].ENA +en => reg_regs_regs_0_sva_cse[6].ENA +en => reg_regs_regs_0_sva_cse[5].ENA +en => reg_regs_regs_0_sva_cse[4].ENA +en => reg_regs_regs_0_sva_cse[3].ENA +en => reg_regs_regs_0_sva_cse[2].ENA +en => reg_regs_regs_0_sva_cse[1].ENA +arst_n => reg_regs_regs_0_sva_cse[0].ACLR +arst_n => reg_regs_regs_0_sva_cse[1].ACLR +arst_n => reg_regs_regs_0_sva_cse[2].ACLR +arst_n => reg_regs_regs_0_sva_cse[3].ACLR +arst_n => reg_regs_regs_0_sva_cse[4].ACLR +arst_n => reg_regs_regs_0_sva_cse[5].ACLR +arst_n => reg_regs_regs_0_sva_cse[6].ACLR +arst_n => reg_regs_regs_0_sva_cse[7].ACLR +arst_n => reg_regs_regs_0_sva_cse[8].ACLR +arst_n => reg_regs_regs_0_sva_cse[9].ACLR +arst_n => reg_regs_regs_0_sva_cse[10].ACLR +arst_n => reg_regs_regs_0_sva_cse[11].ACLR +arst_n => reg_regs_regs_0_sva_cse[12].ACLR +arst_n => reg_regs_regs_0_sva_cse[13].ACLR +arst_n => reg_regs_regs_0_sva_cse[14].ACLR +arst_n => reg_regs_regs_0_sva_cse[15].ACLR +arst_n => reg_regs_regs_0_sva_cse[16].ACLR +arst_n => reg_regs_regs_0_sva_cse[17].ACLR +arst_n => reg_regs_regs_0_sva_cse[18].ACLR +arst_n => reg_regs_regs_0_sva_cse[19].ACLR +arst_n => reg_regs_regs_0_sva_cse[20].ACLR +arst_n => reg_regs_regs_0_sva_cse[21].ACLR +arst_n => reg_regs_regs_0_sva_cse[22].ACLR +arst_n => reg_regs_regs_0_sva_cse[23].ACLR +arst_n => reg_regs_regs_0_sva_cse[24].ACLR +arst_n => reg_regs_regs_0_sva_cse[25].ACLR +arst_n => reg_regs_regs_0_sva_cse[26].ACLR +arst_n => reg_regs_regs_0_sva_cse[27].ACLR +arst_n => reg_regs_regs_0_sva_cse[28].ACLR +arst_n => reg_regs_regs_0_sva_cse[29].ACLR +arst_n => reg_regs_regs_0_sva_cse[30].ACLR +arst_n => reg_regs_regs_0_sva_cse[31].ACLR +arst_n => reg_regs_regs_0_sva_cse[32].ACLR +arst_n => reg_regs_regs_0_sva_cse[33].ACLR +arst_n => reg_regs_regs_0_sva_cse[34].ACLR +arst_n => reg_regs_regs_0_sva_cse[35].ACLR +arst_n => reg_regs_regs_0_sva_cse[36].ACLR +arst_n => reg_regs_regs_0_sva_cse[37].ACLR +arst_n => reg_regs_regs_0_sva_cse[38].ACLR +arst_n => reg_regs_regs_0_sva_cse[39].ACLR +arst_n => reg_regs_regs_0_sva_cse[40].ACLR +arst_n => reg_regs_regs_0_sva_cse[41].ACLR +arst_n => reg_regs_regs_0_sva_cse[42].ACLR +arst_n => reg_regs_regs_0_sva_cse[43].ACLR +arst_n => reg_regs_regs_0_sva_cse[44].ACLR +arst_n => reg_regs_regs_0_sva_cse[45].ACLR +arst_n => reg_regs_regs_0_sva_cse[46].ACLR +arst_n => reg_regs_regs_0_sva_cse[47].ACLR +arst_n => reg_regs_regs_0_sva_cse[48].ACLR +arst_n => reg_regs_regs_0_sva_cse[49].ACLR +arst_n => reg_regs_regs_0_sva_cse[50].ACLR +arst_n => reg_regs_regs_0_sva_cse[51].ACLR +arst_n => reg_regs_regs_0_sva_cse[52].ACLR +arst_n => reg_regs_regs_0_sva_cse[53].ACLR +arst_n => reg_regs_regs_0_sva_cse[54].ACLR +arst_n => reg_regs_regs_0_sva_cse[55].ACLR +arst_n => reg_regs_regs_0_sva_cse[56].ACLR +arst_n => reg_regs_regs_0_sva_cse[57].ACLR +arst_n => reg_regs_regs_0_sva_cse[58].ACLR +arst_n => reg_regs_regs_0_sva_cse[59].ACLR +arst_n => reg_regs_regs_0_sva_cse[60].ACLR +arst_n => reg_regs_regs_0_sva_cse[61].ACLR +arst_n => reg_regs_regs_0_sva_cse[62].ACLR +arst_n => reg_regs_regs_0_sva_cse[63].ACLR +arst_n => reg_regs_regs_0_sva_cse[64].ACLR +arst_n => reg_regs_regs_0_sva_cse[65].ACLR +arst_n => reg_regs_regs_0_sva_cse[66].ACLR +arst_n => reg_regs_regs_0_sva_cse[67].ACLR +arst_n => reg_regs_regs_0_sva_cse[68].ACLR +arst_n => reg_regs_regs_0_sva_cse[69].ACLR +arst_n => reg_regs_regs_0_sva_cse[70].ACLR +arst_n => reg_regs_regs_0_sva_cse[71].ACLR +arst_n => reg_regs_regs_0_sva_cse[72].ACLR +arst_n => reg_regs_regs_0_sva_cse[73].ACLR +arst_n => reg_regs_regs_0_sva_cse[74].ACLR +arst_n => reg_regs_regs_0_sva_cse[75].ACLR +arst_n => reg_regs_regs_0_sva_cse[76].ACLR +arst_n => reg_regs_regs_0_sva_cse[77].ACLR +arst_n => reg_regs_regs_0_sva_cse[78].ACLR +arst_n => reg_regs_regs_0_sva_cse[79].ACLR +arst_n => reg_regs_regs_0_sva_cse[80].ACLR +arst_n => reg_regs_regs_0_sva_cse[81].ACLR +arst_n => reg_regs_regs_0_sva_cse[82].ACLR +arst_n => reg_regs_regs_0_sva_cse[83].ACLR +arst_n => reg_regs_regs_0_sva_cse[84].ACLR +arst_n => reg_regs_regs_0_sva_cse[85].ACLR +arst_n => reg_regs_regs_0_sva_cse[86].ACLR +arst_n => reg_regs_regs_0_sva_cse[87].ACLR +arst_n => reg_regs_regs_0_sva_cse[88].ACLR +arst_n => reg_regs_regs_0_sva_cse[89].ACLR +arst_n => regs_regs_slc_regs_regs_2_2_itm[0].ACLR +arst_n => regs_regs_slc_regs_regs_2_2_itm[1].ACLR +arst_n => regs_regs_slc_regs_regs_2_2_itm[2].ACLR +arst_n => regs_regs_slc_regs_regs_2_2_itm[3].ACLR +arst_n => regs_regs_slc_regs_regs_2_2_itm[4].ACLR +arst_n => regs_regs_slc_regs_regs_2_2_itm[5].ACLR +arst_n => regs_regs_slc_regs_regs_2_2_itm[6].ACLR +arst_n => regs_regs_slc_regs_regs_2_2_itm[7].ACLR +arst_n => regs_regs_slc_regs_regs_2_2_itm[8].ACLR +arst_n => regs_regs_slc_regs_regs_2_2_itm[9].ACLR +arst_n => regs_regs_slc_regs_regs_2_1_itm[0].ACLR +arst_n => regs_regs_slc_regs_regs_2_1_itm[1].ACLR +arst_n => regs_regs_slc_regs_regs_2_1_itm[2].ACLR +arst_n => regs_regs_slc_regs_regs_2_1_itm[3].ACLR +arst_n => regs_regs_slc_regs_regs_2_1_itm[4].ACLR +arst_n => regs_regs_slc_regs_regs_2_1_itm[5].ACLR +arst_n => regs_regs_slc_regs_regs_2_1_itm[6].ACLR +arst_n => regs_regs_slc_regs_regs_2_1_itm[7].ACLR +arst_n => regs_regs_slc_regs_regs_2_1_itm[8].ACLR +arst_n => regs_regs_slc_regs_regs_2_1_itm[9].ACLR +arst_n => regs_regs_slc_regs_regs_2_itm[0].ACLR +arst_n => regs_regs_slc_regs_regs_2_itm[1].ACLR +arst_n => regs_regs_slc_regs_regs_2_itm[2].ACLR +arst_n => regs_regs_slc_regs_regs_2_itm[3].ACLR +arst_n => regs_regs_slc_regs_regs_2_itm[4].ACLR +arst_n => regs_regs_slc_regs_regs_2_itm[5].ACLR +arst_n => regs_regs_slc_regs_regs_2_itm[6].ACLR +arst_n => regs_regs_slc_regs_regs_2_itm[7].ACLR +arst_n => regs_regs_slc_regs_regs_2_itm[8].ACLR +arst_n => regs_regs_slc_regs_regs_2_itm[9].ACLR +arst_n => regs_regs_slc_regs_regs_2_3_itm[0].ACLR +arst_n => regs_regs_slc_regs_regs_2_3_itm[1].ACLR +arst_n => regs_regs_slc_regs_regs_2_3_itm[2].ACLR +arst_n => regs_regs_slc_regs_regs_2_3_itm[3].ACLR +arst_n => regs_regs_slc_regs_regs_2_3_itm[4].ACLR +arst_n => regs_regs_slc_regs_regs_2_3_itm[5].ACLR +arst_n => regs_regs_slc_regs_regs_2_3_itm[6].ACLR +arst_n => regs_regs_slc_regs_regs_2_3_itm[7].ACLR +arst_n => regs_regs_slc_regs_regs_2_3_itm[8].ACLR +arst_n => regs_regs_slc_regs_regs_2_3_itm[9].ACLR +arst_n => regs_regs_slc_regs_regs_2_5_itm[0].ACLR +arst_n => regs_regs_slc_regs_regs_2_5_itm[1].ACLR +arst_n => regs_regs_slc_regs_regs_2_5_itm[2].ACLR +arst_n => regs_regs_slc_regs_regs_2_5_itm[3].ACLR +arst_n => regs_regs_slc_regs_regs_2_5_itm[4].ACLR +arst_n => regs_regs_slc_regs_regs_2_5_itm[5].ACLR +arst_n => regs_regs_slc_regs_regs_2_5_itm[6].ACLR +arst_n => regs_regs_slc_regs_regs_2_5_itm[7].ACLR +arst_n => regs_regs_slc_regs_regs_2_5_itm[8].ACLR +arst_n => regs_regs_slc_regs_regs_2_5_itm[9].ACLR +arst_n => regs_regs_slc_regs_regs_2_4_itm[0].ACLR +arst_n => regs_regs_slc_regs_regs_2_4_itm[1].ACLR +arst_n => regs_regs_slc_regs_regs_2_4_itm[2].ACLR +arst_n => regs_regs_slc_regs_regs_2_4_itm[3].ACLR +arst_n => regs_regs_slc_regs_regs_2_4_itm[4].ACLR +arst_n => regs_regs_slc_regs_regs_2_4_itm[5].ACLR +arst_n => regs_regs_slc_regs_regs_2_4_itm[6].ACLR +arst_n => regs_regs_slc_regs_regs_2_4_itm[7].ACLR +arst_n => regs_regs_slc_regs_regs_2_4_itm[8].ACLR +arst_n => regs_regs_slc_regs_regs_2_4_itm[9].ACLR +arst_n => regs_regs_slc_regs_regs_2_9_itm[0].ACLR +arst_n => regs_regs_slc_regs_regs_2_9_itm[1].ACLR +arst_n => regs_regs_slc_regs_regs_2_9_itm[2].ACLR +arst_n => regs_regs_slc_regs_regs_2_9_itm[3].ACLR +arst_n => regs_regs_slc_regs_regs_2_9_itm[4].ACLR +arst_n => regs_regs_slc_regs_regs_2_9_itm[5].ACLR +arst_n => regs_regs_slc_regs_regs_2_9_itm[6].ACLR +arst_n => regs_regs_slc_regs_regs_2_9_itm[7].ACLR +arst_n => regs_regs_slc_regs_regs_2_9_itm[8].ACLR +arst_n => regs_regs_slc_regs_regs_2_9_itm[9].ACLR +arst_n => regs_regs_slc_regs_regs_2_11_itm[0].ACLR +arst_n => regs_regs_slc_regs_regs_2_11_itm[1].ACLR +arst_n => regs_regs_slc_regs_regs_2_11_itm[2].ACLR +arst_n => regs_regs_slc_regs_regs_2_11_itm[3].ACLR +arst_n => regs_regs_slc_regs_regs_2_11_itm[4].ACLR +arst_n => regs_regs_slc_regs_regs_2_11_itm[5].ACLR +arst_n => regs_regs_slc_regs_regs_2_11_itm[6].ACLR +arst_n => regs_regs_slc_regs_regs_2_11_itm[7].ACLR +arst_n => regs_regs_slc_regs_regs_2_11_itm[8].ACLR +arst_n => regs_regs_slc_regs_regs_2_11_itm[9].ACLR +arst_n => regs_regs_slc_regs_regs_2_10_itm[0].ACLR +arst_n => regs_regs_slc_regs_regs_2_10_itm[1].ACLR +arst_n => regs_regs_slc_regs_regs_2_10_itm[2].ACLR +arst_n => regs_regs_slc_regs_regs_2_10_itm[3].ACLR +arst_n => regs_regs_slc_regs_regs_2_10_itm[4].ACLR +arst_n => regs_regs_slc_regs_regs_2_10_itm[5].ACLR +arst_n => regs_regs_slc_regs_regs_2_10_itm[6].ACLR +arst_n => regs_regs_slc_regs_regs_2_10_itm[7].ACLR +arst_n => regs_regs_slc_regs_regs_2_10_itm[8].ACLR +arst_n => regs_regs_slc_regs_regs_2_10_itm[9].ACLR +arst_n => main_stage_0_2.ACLR +arst_n => ACC1_acc_655_itm_1[0].ACLR +arst_n => ACC1_acc_655_itm_1[1].ACLR +arst_n => ACC1_acc_655_itm_1[2].ACLR +arst_n => ACC1_acc_655_itm_1[3].ACLR +arst_n => ACC1_acc_655_itm_1[4].ACLR +arst_n => ACC1_acc_655_itm_1[5].ACLR +arst_n => ACC1_acc_655_itm_1[6].ACLR +arst_n => ACC1_acc_655_itm_1[7].ACLR +arst_n => ACC1_acc_655_itm_1[8].ACLR +arst_n => ACC1_acc_655_itm_1[9].ACLR +arst_n => ACC1_acc_655_itm_1[10].ACLR +arst_n => ACC1_acc_655_itm_1[11].ACLR +arst_n => ACC1_acc_652_itm_1[0].ACLR +arst_n => ACC1_acc_652_itm_1[1].ACLR +arst_n => ACC1_acc_652_itm_1[2].ACLR +arst_n => ACC1_acc_652_itm_1[3].ACLR +arst_n => ACC1_acc_652_itm_1[4].ACLR +arst_n => ACC1_acc_652_itm_1[5].ACLR +arst_n => ACC1_acc_652_itm_1[6].ACLR +arst_n => ACC1_acc_652_itm_1[7].ACLR +arst_n => ACC1_acc_652_itm_1[8].ACLR +arst_n => ACC1_acc_652_itm_1[9].ACLR +arst_n => ACC1_acc_652_itm_1[10].ACLR +arst_n => ACC1_3_slc_acc_10_psp_62_itm_1.ACLR +arst_n => ACC1_slc_ACC1_acc_228_psp_55_itm_1.ACLR +arst_n => slc_acc_20_psp_1_93_itm_1.ACLR +arst_n => ACC1_mul_57_itm_2[0].ACLR +arst_n => ACC1_mul_57_itm_2[1].ACLR +arst_n => ACC1_mul_57_itm_1_sg2[0].ACLR +arst_n => ACC1_mul_57_itm_1_sg2[1].ACLR +arst_n => ACC1_mul_57_itm_1_sg2[2].ACLR +arst_n => ACC1_mul_57_itm_1_sg2[3].ACLR +arst_n => ACC1_mul_57_itm_1_sg2[4].ACLR +arst_n => ACC1_acc_661_itm_1[0].ACLR +arst_n => ACC1_acc_661_itm_1[1].ACLR +arst_n => ACC1_acc_661_itm_1[2].ACLR +arst_n => ACC1_acc_661_itm_1[3].ACLR +arst_n => ACC1_acc_661_itm_1[4].ACLR +arst_n => ACC1_acc_661_itm_1[5].ACLR +arst_n => ACC1_acc_661_itm_1[6].ACLR +arst_n => ACC1_acc_661_itm_1[7].ACLR +arst_n => ACC1_acc_661_itm_1[8].ACLR +arst_n => ACC1_acc_661_itm_1[9].ACLR +arst_n => ACC1_acc_661_itm_1[10].ACLR +arst_n => ACC1_acc_661_itm_1[11].ACLR +arst_n => ACC1_acc_661_itm_1[12].ACLR +arst_n => ACC1_acc_661_itm_1[13].ACLR +arst_n => ACC1_acc_658_itm_1[0].ACLR +arst_n => ACC1_acc_658_itm_1[1].ACLR +arst_n => ACC1_acc_658_itm_1[2].ACLR +arst_n => ACC1_acc_658_itm_1[3].ACLR +arst_n => ACC1_acc_658_itm_1[4].ACLR +arst_n => ACC1_acc_658_itm_1[5].ACLR +arst_n => ACC1_acc_658_itm_1[6].ACLR +arst_n => ACC1_acc_658_itm_1[7].ACLR +arst_n => ACC1_acc_658_itm_1[8].ACLR +arst_n => ACC1_acc_658_itm_1[9].ACLR +arst_n => ACC1_acc_658_itm_1[10].ACLR +arst_n => ACC1_acc_658_itm_1[11].ACLR +arst_n => ACC1_acc_658_itm_1[12].ACLR +arst_n => ACC1_acc_659_itm_1[0].ACLR +arst_n => ACC1_acc_659_itm_1[1].ACLR +arst_n => ACC1_acc_659_itm_1[2].ACLR +arst_n => ACC1_acc_659_itm_1[3].ACLR +arst_n => ACC1_acc_659_itm_1[4].ACLR +arst_n => ACC1_acc_659_itm_1[5].ACLR +arst_n => ACC1_acc_659_itm_1[6].ACLR +arst_n => ACC1_acc_659_itm_1[7].ACLR +arst_n => ACC1_acc_659_itm_1[8].ACLR +arst_n => ACC1_acc_659_itm_1[9].ACLR +arst_n => ACC1_acc_659_itm_1[10].ACLR +arst_n => ACC1_acc_659_itm_1[11].ACLR +arst_n => ACC1_acc_659_itm_1[12].ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[0]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[1]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[2]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[3]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[4]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[5]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[6]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[7]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[8]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[9]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[10]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[11]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[12]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[13]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[14]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[15]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[16]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[17]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[18]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[19]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[20]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[21]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[22]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[23]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[24]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[25]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[26]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[27]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[28]~reg0.ACLR +arst_n => vout_rsc_mgc_out_stdreg_d[29]~reg0.ACLR +vin_rsc_mgc_in_wire_d[0] => Add43.IN22 +vin_rsc_mgc_in_wire_d[0] => reg_regs_regs_0_sva_cse[0].DATAIN +vin_rsc_mgc_in_wire_d[1] => Add43.IN21 +vin_rsc_mgc_in_wire_d[1] => reg_regs_regs_0_sva_cse[1].DATAIN +vin_rsc_mgc_in_wire_d[2] => Add43.IN20 +vin_rsc_mgc_in_wire_d[2] => reg_regs_regs_0_sva_cse[2].DATAIN +vin_rsc_mgc_in_wire_d[3] => Add43.IN19 +vin_rsc_mgc_in_wire_d[3] => reg_regs_regs_0_sva_cse[3].DATAIN +vin_rsc_mgc_in_wire_d[4] => Add43.IN18 +vin_rsc_mgc_in_wire_d[4] => reg_regs_regs_0_sva_cse[4].DATAIN +vin_rsc_mgc_in_wire_d[5] => Add43.IN17 +vin_rsc_mgc_in_wire_d[5] => reg_regs_regs_0_sva_cse[5].DATAIN +vin_rsc_mgc_in_wire_d[6] => Add43.IN16 +vin_rsc_mgc_in_wire_d[6] => reg_regs_regs_0_sva_cse[6].DATAIN +vin_rsc_mgc_in_wire_d[7] => Add43.IN15 +vin_rsc_mgc_in_wire_d[7] => reg_regs_regs_0_sva_cse[7].DATAIN +vin_rsc_mgc_in_wire_d[8] => Add43.IN14 +vin_rsc_mgc_in_wire_d[8] => reg_regs_regs_0_sva_cse[8].DATAIN +vin_rsc_mgc_in_wire_d[9] => Add43.IN12 +vin_rsc_mgc_in_wire_d[9] => Add43.IN13 +vin_rsc_mgc_in_wire_d[9] => reg_regs_regs_0_sva_cse[9].DATAIN +vin_rsc_mgc_in_wire_d[10] => Add42.IN22 +vin_rsc_mgc_in_wire_d[10] => reg_regs_regs_0_sva_cse[10].DATAIN +vin_rsc_mgc_in_wire_d[11] => Add42.IN21 +vin_rsc_mgc_in_wire_d[11] => reg_regs_regs_0_sva_cse[11].DATAIN +vin_rsc_mgc_in_wire_d[12] => Add42.IN20 +vin_rsc_mgc_in_wire_d[12] => reg_regs_regs_0_sva_cse[12].DATAIN +vin_rsc_mgc_in_wire_d[13] => Add42.IN19 +vin_rsc_mgc_in_wire_d[13] => reg_regs_regs_0_sva_cse[13].DATAIN +vin_rsc_mgc_in_wire_d[14] => Add42.IN18 +vin_rsc_mgc_in_wire_d[14] => reg_regs_regs_0_sva_cse[14].DATAIN +vin_rsc_mgc_in_wire_d[15] => Add42.IN17 +vin_rsc_mgc_in_wire_d[15] => reg_regs_regs_0_sva_cse[15].DATAIN +vin_rsc_mgc_in_wire_d[16] => Add42.IN16 +vin_rsc_mgc_in_wire_d[16] => reg_regs_regs_0_sva_cse[16].DATAIN +vin_rsc_mgc_in_wire_d[17] => Add42.IN15 +vin_rsc_mgc_in_wire_d[17] => reg_regs_regs_0_sva_cse[17].DATAIN +vin_rsc_mgc_in_wire_d[18] => Add42.IN14 +vin_rsc_mgc_in_wire_d[18] => reg_regs_regs_0_sva_cse[18].DATAIN +vin_rsc_mgc_in_wire_d[19] => Add42.IN12 +vin_rsc_mgc_in_wire_d[19] => Add42.IN13 +vin_rsc_mgc_in_wire_d[19] => reg_regs_regs_0_sva_cse[19].DATAIN +vin_rsc_mgc_in_wire_d[20] => Add42.IN11 +vin_rsc_mgc_in_wire_d[20] => reg_regs_regs_0_sva_cse[20].DATAIN +vin_rsc_mgc_in_wire_d[21] => Add42.IN10 +vin_rsc_mgc_in_wire_d[21] => reg_regs_regs_0_sva_cse[21].DATAIN +vin_rsc_mgc_in_wire_d[22] => Add42.IN9 +vin_rsc_mgc_in_wire_d[22] => reg_regs_regs_0_sva_cse[22].DATAIN +vin_rsc_mgc_in_wire_d[23] => Add42.IN8 +vin_rsc_mgc_in_wire_d[23] => reg_regs_regs_0_sva_cse[23].DATAIN +vin_rsc_mgc_in_wire_d[24] => Add42.IN7 +vin_rsc_mgc_in_wire_d[24] => reg_regs_regs_0_sva_cse[24].DATAIN +vin_rsc_mgc_in_wire_d[25] => Add42.IN6 +vin_rsc_mgc_in_wire_d[25] => reg_regs_regs_0_sva_cse[25].DATAIN +vin_rsc_mgc_in_wire_d[26] => Add42.IN5 +vin_rsc_mgc_in_wire_d[26] => reg_regs_regs_0_sva_cse[26].DATAIN +vin_rsc_mgc_in_wire_d[27] => Add42.IN4 +vin_rsc_mgc_in_wire_d[27] => reg_regs_regs_0_sva_cse[27].DATAIN +vin_rsc_mgc_in_wire_d[28] => Add42.IN3 +vin_rsc_mgc_in_wire_d[28] => reg_regs_regs_0_sva_cse[28].DATAIN +vin_rsc_mgc_in_wire_d[29] => Add42.IN1 +vin_rsc_mgc_in_wire_d[29] => Add42.IN2 +vin_rsc_mgc_in_wire_d[29] => reg_regs_regs_0_sva_cse[29].DATAIN +vin_rsc_mgc_in_wire_d[30] => Add45.IN11 +vin_rsc_mgc_in_wire_d[30] => reg_regs_regs_0_sva_cse[30].DATAIN +vin_rsc_mgc_in_wire_d[31] => Add45.IN10 +vin_rsc_mgc_in_wire_d[31] => reg_regs_regs_0_sva_cse[31].DATAIN +vin_rsc_mgc_in_wire_d[32] => Add45.IN9 +vin_rsc_mgc_in_wire_d[32] => reg_regs_regs_0_sva_cse[32].DATAIN +vin_rsc_mgc_in_wire_d[33] => Add45.IN8 +vin_rsc_mgc_in_wire_d[33] => reg_regs_regs_0_sva_cse[33].DATAIN +vin_rsc_mgc_in_wire_d[34] => Add45.IN7 +vin_rsc_mgc_in_wire_d[34] => reg_regs_regs_0_sva_cse[34].DATAIN +vin_rsc_mgc_in_wire_d[35] => Add45.IN6 +vin_rsc_mgc_in_wire_d[35] => reg_regs_regs_0_sva_cse[35].DATAIN +vin_rsc_mgc_in_wire_d[36] => Add45.IN5 +vin_rsc_mgc_in_wire_d[36] => reg_regs_regs_0_sva_cse[36].DATAIN +vin_rsc_mgc_in_wire_d[37] => Add45.IN4 +vin_rsc_mgc_in_wire_d[37] => reg_regs_regs_0_sva_cse[37].DATAIN +vin_rsc_mgc_in_wire_d[38] => Add45.IN3 +vin_rsc_mgc_in_wire_d[38] => reg_regs_regs_0_sva_cse[38].DATAIN +vin_rsc_mgc_in_wire_d[39] => Add45.IN1 +vin_rsc_mgc_in_wire_d[39] => Add45.IN2 +vin_rsc_mgc_in_wire_d[39] => reg_regs_regs_0_sva_cse[39].DATAIN +vin_rsc_mgc_in_wire_d[40] => Add45.IN22 +vin_rsc_mgc_in_wire_d[40] => reg_regs_regs_0_sva_cse[40].DATAIN +vin_rsc_mgc_in_wire_d[41] => Add45.IN21 +vin_rsc_mgc_in_wire_d[41] => reg_regs_regs_0_sva_cse[41].DATAIN +vin_rsc_mgc_in_wire_d[42] => Add45.IN20 +vin_rsc_mgc_in_wire_d[42] => reg_regs_regs_0_sva_cse[42].DATAIN +vin_rsc_mgc_in_wire_d[43] => Add45.IN19 +vin_rsc_mgc_in_wire_d[43] => reg_regs_regs_0_sva_cse[43].DATAIN +vin_rsc_mgc_in_wire_d[44] => Add45.IN18 +vin_rsc_mgc_in_wire_d[44] => reg_regs_regs_0_sva_cse[44].DATAIN +vin_rsc_mgc_in_wire_d[45] => Add45.IN17 +vin_rsc_mgc_in_wire_d[45] => reg_regs_regs_0_sva_cse[45].DATAIN +vin_rsc_mgc_in_wire_d[46] => Add45.IN16 +vin_rsc_mgc_in_wire_d[46] => reg_regs_regs_0_sva_cse[46].DATAIN +vin_rsc_mgc_in_wire_d[47] => Add45.IN15 +vin_rsc_mgc_in_wire_d[47] => reg_regs_regs_0_sva_cse[47].DATAIN +vin_rsc_mgc_in_wire_d[48] => Add45.IN14 +vin_rsc_mgc_in_wire_d[48] => reg_regs_regs_0_sva_cse[48].DATAIN +vin_rsc_mgc_in_wire_d[49] => Add45.IN12 +vin_rsc_mgc_in_wire_d[49] => Add45.IN13 +vin_rsc_mgc_in_wire_d[49] => reg_regs_regs_0_sva_cse[49].DATAIN +vin_rsc_mgc_in_wire_d[50] => Add46.IN22 +vin_rsc_mgc_in_wire_d[50] => reg_regs_regs_0_sva_cse[50].DATAIN +vin_rsc_mgc_in_wire_d[51] => Add46.IN21 +vin_rsc_mgc_in_wire_d[51] => reg_regs_regs_0_sva_cse[51].DATAIN +vin_rsc_mgc_in_wire_d[52] => Add46.IN20 +vin_rsc_mgc_in_wire_d[52] => reg_regs_regs_0_sva_cse[52].DATAIN +vin_rsc_mgc_in_wire_d[53] => Add46.IN19 +vin_rsc_mgc_in_wire_d[53] => reg_regs_regs_0_sva_cse[53].DATAIN +vin_rsc_mgc_in_wire_d[54] => Add46.IN18 +vin_rsc_mgc_in_wire_d[54] => reg_regs_regs_0_sva_cse[54].DATAIN +vin_rsc_mgc_in_wire_d[55] => Add46.IN17 +vin_rsc_mgc_in_wire_d[55] => reg_regs_regs_0_sva_cse[55].DATAIN +vin_rsc_mgc_in_wire_d[56] => Add46.IN16 +vin_rsc_mgc_in_wire_d[56] => reg_regs_regs_0_sva_cse[56].DATAIN +vin_rsc_mgc_in_wire_d[57] => Add46.IN15 +vin_rsc_mgc_in_wire_d[57] => reg_regs_regs_0_sva_cse[57].DATAIN +vin_rsc_mgc_in_wire_d[58] => Add46.IN14 +vin_rsc_mgc_in_wire_d[58] => reg_regs_regs_0_sva_cse[58].DATAIN +vin_rsc_mgc_in_wire_d[59] => Add46.IN12 +vin_rsc_mgc_in_wire_d[59] => Add46.IN13 +vin_rsc_mgc_in_wire_d[59] => reg_regs_regs_0_sva_cse[59].DATAIN +vin_rsc_mgc_in_wire_d[60] => Add25.IN22 +vin_rsc_mgc_in_wire_d[60] => Add131.IN22 +vin_rsc_mgc_in_wire_d[60] => reg_regs_regs_0_sva_cse[60].DATAIN +vin_rsc_mgc_in_wire_d[61] => Add25.IN21 +vin_rsc_mgc_in_wire_d[61] => Add131.IN21 +vin_rsc_mgc_in_wire_d[61] => reg_regs_regs_0_sva_cse[61].DATAIN +vin_rsc_mgc_in_wire_d[62] => Add25.IN20 +vin_rsc_mgc_in_wire_d[62] => Add131.IN20 +vin_rsc_mgc_in_wire_d[62] => reg_regs_regs_0_sva_cse[62].DATAIN +vin_rsc_mgc_in_wire_d[63] => Add25.IN19 +vin_rsc_mgc_in_wire_d[63] => Add131.IN19 +vin_rsc_mgc_in_wire_d[63] => reg_regs_regs_0_sva_cse[63].DATAIN +vin_rsc_mgc_in_wire_d[64] => Add25.IN18 +vin_rsc_mgc_in_wire_d[64] => Add131.IN18 +vin_rsc_mgc_in_wire_d[64] => reg_regs_regs_0_sva_cse[64].DATAIN +vin_rsc_mgc_in_wire_d[65] => Add25.IN17 +vin_rsc_mgc_in_wire_d[65] => Add131.IN17 +vin_rsc_mgc_in_wire_d[65] => reg_regs_regs_0_sva_cse[65].DATAIN +vin_rsc_mgc_in_wire_d[66] => Add25.IN16 +vin_rsc_mgc_in_wire_d[66] => Add131.IN16 +vin_rsc_mgc_in_wire_d[66] => reg_regs_regs_0_sva_cse[66].DATAIN +vin_rsc_mgc_in_wire_d[67] => Add25.IN15 +vin_rsc_mgc_in_wire_d[67] => Add131.IN15 +vin_rsc_mgc_in_wire_d[67] => reg_regs_regs_0_sva_cse[67].DATAIN +vin_rsc_mgc_in_wire_d[68] => Add25.IN14 +vin_rsc_mgc_in_wire_d[68] => Add131.IN14 +vin_rsc_mgc_in_wire_d[68] => reg_regs_regs_0_sva_cse[68].DATAIN +vin_rsc_mgc_in_wire_d[69] => Add25.IN12 +vin_rsc_mgc_in_wire_d[69] => Add25.IN13 +vin_rsc_mgc_in_wire_d[69] => Add131.IN12 +vin_rsc_mgc_in_wire_d[69] => Add131.IN13 +vin_rsc_mgc_in_wire_d[69] => reg_regs_regs_0_sva_cse[69].DATAIN +vin_rsc_mgc_in_wire_d[70] => Add25.IN11 +vin_rsc_mgc_in_wire_d[70] => Add130.IN22 +vin_rsc_mgc_in_wire_d[70] => reg_regs_regs_0_sva_cse[70].DATAIN +vin_rsc_mgc_in_wire_d[71] => Add25.IN10 +vin_rsc_mgc_in_wire_d[71] => Add130.IN21 +vin_rsc_mgc_in_wire_d[71] => reg_regs_regs_0_sva_cse[71].DATAIN +vin_rsc_mgc_in_wire_d[72] => Add25.IN9 +vin_rsc_mgc_in_wire_d[72] => Add130.IN20 +vin_rsc_mgc_in_wire_d[72] => reg_regs_regs_0_sva_cse[72].DATAIN +vin_rsc_mgc_in_wire_d[73] => Add25.IN8 +vin_rsc_mgc_in_wire_d[73] => Add130.IN19 +vin_rsc_mgc_in_wire_d[73] => reg_regs_regs_0_sva_cse[73].DATAIN +vin_rsc_mgc_in_wire_d[74] => Add25.IN7 +vin_rsc_mgc_in_wire_d[74] => Add130.IN18 +vin_rsc_mgc_in_wire_d[74] => reg_regs_regs_0_sva_cse[74].DATAIN +vin_rsc_mgc_in_wire_d[75] => Add25.IN6 +vin_rsc_mgc_in_wire_d[75] => Add130.IN17 +vin_rsc_mgc_in_wire_d[75] => reg_regs_regs_0_sva_cse[75].DATAIN +vin_rsc_mgc_in_wire_d[76] => Add25.IN5 +vin_rsc_mgc_in_wire_d[76] => Add130.IN16 +vin_rsc_mgc_in_wire_d[76] => reg_regs_regs_0_sva_cse[76].DATAIN +vin_rsc_mgc_in_wire_d[77] => Add25.IN4 +vin_rsc_mgc_in_wire_d[77] => Add130.IN15 +vin_rsc_mgc_in_wire_d[77] => reg_regs_regs_0_sva_cse[77].DATAIN +vin_rsc_mgc_in_wire_d[78] => Add25.IN3 +vin_rsc_mgc_in_wire_d[78] => Add130.IN14 +vin_rsc_mgc_in_wire_d[78] => reg_regs_regs_0_sva_cse[78].DATAIN +vin_rsc_mgc_in_wire_d[79] => Add25.IN1 +vin_rsc_mgc_in_wire_d[79] => Add25.IN2 +vin_rsc_mgc_in_wire_d[79] => Add130.IN12 +vin_rsc_mgc_in_wire_d[79] => Add130.IN13 +vin_rsc_mgc_in_wire_d[79] => reg_regs_regs_0_sva_cse[79].DATAIN +vin_rsc_mgc_in_wire_d[80] => Add26.IN26 +vin_rsc_mgc_in_wire_d[80] => Add130.IN11 +vin_rsc_mgc_in_wire_d[80] => reg_regs_regs_0_sva_cse[80].DATAIN +vin_rsc_mgc_in_wire_d[81] => Add26.IN25 +vin_rsc_mgc_in_wire_d[81] => Add130.IN10 +vin_rsc_mgc_in_wire_d[81] => reg_regs_regs_0_sva_cse[81].DATAIN +vin_rsc_mgc_in_wire_d[82] => Add26.IN24 +vin_rsc_mgc_in_wire_d[82] => Add130.IN9 +vin_rsc_mgc_in_wire_d[82] => reg_regs_regs_0_sva_cse[82].DATAIN +vin_rsc_mgc_in_wire_d[83] => Add26.IN23 +vin_rsc_mgc_in_wire_d[83] => Add130.IN8 +vin_rsc_mgc_in_wire_d[83] => reg_regs_regs_0_sva_cse[83].DATAIN +vin_rsc_mgc_in_wire_d[84] => Add26.IN22 +vin_rsc_mgc_in_wire_d[84] => Add130.IN7 +vin_rsc_mgc_in_wire_d[84] => reg_regs_regs_0_sva_cse[84].DATAIN +vin_rsc_mgc_in_wire_d[85] => Add26.IN21 +vin_rsc_mgc_in_wire_d[85] => Add130.IN6 +vin_rsc_mgc_in_wire_d[85] => reg_regs_regs_0_sva_cse[85].DATAIN +vin_rsc_mgc_in_wire_d[86] => Add26.IN20 +vin_rsc_mgc_in_wire_d[86] => Add130.IN5 +vin_rsc_mgc_in_wire_d[86] => reg_regs_regs_0_sva_cse[86].DATAIN +vin_rsc_mgc_in_wire_d[87] => Add26.IN19 +vin_rsc_mgc_in_wire_d[87] => Add130.IN4 +vin_rsc_mgc_in_wire_d[87] => reg_regs_regs_0_sva_cse[87].DATAIN +vin_rsc_mgc_in_wire_d[88] => Add26.IN18 +vin_rsc_mgc_in_wire_d[88] => Add130.IN3 +vin_rsc_mgc_in_wire_d[88] => reg_regs_regs_0_sva_cse[88].DATAIN +vin_rsc_mgc_in_wire_d[89] => Add26.IN14 +vin_rsc_mgc_in_wire_d[89] => Add26.IN15 +vin_rsc_mgc_in_wire_d[89] => Add26.IN16 +vin_rsc_mgc_in_wire_d[89] => Add26.IN17 +vin_rsc_mgc_in_wire_d[89] => Add130.IN1 +vin_rsc_mgc_in_wire_d[89] => Add130.IN2 +vin_rsc_mgc_in_wire_d[89] => reg_regs_regs_0_sva_cse[89].DATAIN +vout_rsc_mgc_out_stdreg_d[0] <= vout_rsc_mgc_out_stdreg_d[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[1] <= vout_rsc_mgc_out_stdreg_d[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[2] <= vout_rsc_mgc_out_stdreg_d[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[3] <= vout_rsc_mgc_out_stdreg_d[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[4] <= vout_rsc_mgc_out_stdreg_d[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[5] <= vout_rsc_mgc_out_stdreg_d[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[6] <= vout_rsc_mgc_out_stdreg_d[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[7] <= vout_rsc_mgc_out_stdreg_d[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[8] <= vout_rsc_mgc_out_stdreg_d[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[9] <= vout_rsc_mgc_out_stdreg_d[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[10] <= vout_rsc_mgc_out_stdreg_d[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[11] <= vout_rsc_mgc_out_stdreg_d[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[12] <= vout_rsc_mgc_out_stdreg_d[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[13] <= vout_rsc_mgc_out_stdreg_d[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[14] <= vout_rsc_mgc_out_stdreg_d[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[15] <= vout_rsc_mgc_out_stdreg_d[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[16] <= vout_rsc_mgc_out_stdreg_d[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[17] <= vout_rsc_mgc_out_stdreg_d[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[18] <= vout_rsc_mgc_out_stdreg_d[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[19] <= vout_rsc_mgc_out_stdreg_d[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[20] <= vout_rsc_mgc_out_stdreg_d[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[21] <= vout_rsc_mgc_out_stdreg_d[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[22] <= vout_rsc_mgc_out_stdreg_d[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[23] <= vout_rsc_mgc_out_stdreg_d[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[24] <= vout_rsc_mgc_out_stdreg_d[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[25] <= vout_rsc_mgc_out_stdreg_d[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[26] <= vout_rsc_mgc_out_stdreg_d[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[27] <= vout_rsc_mgc_out_stdreg_d[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[28] <= vout_rsc_mgc_out_stdreg_d[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +vout_rsc_mgc_out_stdreg_d[29] <= vout_rsc_mgc_out_stdreg_d[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2 +shiftin[0] => shift_taps_jpm:auto_generated.shiftin[0] +shiftin[1] => shift_taps_jpm:auto_generated.shiftin[1] +shiftin[2] => shift_taps_jpm:auto_generated.shiftin[2] +shiftin[3] => shift_taps_jpm:auto_generated.shiftin[3] +shiftin[4] => shift_taps_jpm:auto_generated.shiftin[4] +shiftin[5] => shift_taps_jpm:auto_generated.shiftin[5] +shiftin[6] => shift_taps_jpm:auto_generated.shiftin[6] +shiftin[7] => shift_taps_jpm:auto_generated.shiftin[7] +shiftin[8] => shift_taps_jpm:auto_generated.shiftin[8] +shiftin[9] => shift_taps_jpm:auto_generated.shiftin[9] +shiftin[10] => shift_taps_jpm:auto_generated.shiftin[10] +shiftin[11] => shift_taps_jpm:auto_generated.shiftin[11] +shiftin[12] => shift_taps_jpm:auto_generated.shiftin[12] +shiftin[13] => shift_taps_jpm:auto_generated.shiftin[13] +shiftin[14] => shift_taps_jpm:auto_generated.shiftin[14] +shiftin[15] => shift_taps_jpm:auto_generated.shiftin[15] +shiftin[16] => shift_taps_jpm:auto_generated.shiftin[16] +shiftin[17] => shift_taps_jpm:auto_generated.shiftin[17] +shiftin[18] => shift_taps_jpm:auto_generated.shiftin[18] +shiftin[19] => shift_taps_jpm:auto_generated.shiftin[19] +shiftin[20] => shift_taps_jpm:auto_generated.shiftin[20] +shiftin[21] => shift_taps_jpm:auto_generated.shiftin[21] +shiftin[22] => shift_taps_jpm:auto_generated.shiftin[22] +shiftin[23] => shift_taps_jpm:auto_generated.shiftin[23] +shiftin[24] => shift_taps_jpm:auto_generated.shiftin[24] +shiftin[25] => shift_taps_jpm:auto_generated.shiftin[25] +shiftin[26] => shift_taps_jpm:auto_generated.shiftin[26] +shiftin[27] => shift_taps_jpm:auto_generated.shiftin[27] +shiftin[28] => shift_taps_jpm:auto_generated.shiftin[28] +shiftin[29] => shift_taps_jpm:auto_generated.shiftin[29] +clock => shift_taps_jpm:auto_generated.clock +clken => shift_taps_jpm:auto_generated.clken +shiftout[0] <= <GND> +shiftout[1] <= <GND> +shiftout[2] <= <GND> +shiftout[3] <= <GND> +shiftout[4] <= <GND> +shiftout[5] <= <GND> +shiftout[6] <= <GND> +shiftout[7] <= <GND> +shiftout[8] <= <GND> +shiftout[9] <= <GND> +shiftout[10] <= <GND> +shiftout[11] <= <GND> +shiftout[12] <= <GND> +shiftout[13] <= <GND> +shiftout[14] <= <GND> +shiftout[15] <= <GND> +shiftout[16] <= <GND> +shiftout[17] <= <GND> +shiftout[18] <= <GND> +shiftout[19] <= <GND> +shiftout[20] <= <GND> +shiftout[21] <= <GND> +shiftout[22] <= <GND> +shiftout[23] <= <GND> +shiftout[24] <= <GND> +shiftout[25] <= <GND> +shiftout[26] <= <GND> +shiftout[27] <= <GND> +shiftout[28] <= <GND> +shiftout[29] <= <GND> +taps[0] <= shift_taps_jpm:auto_generated.taps[0] +taps[1] <= shift_taps_jpm:auto_generated.taps[1] +taps[2] <= shift_taps_jpm:auto_generated.taps[2] +taps[3] <= shift_taps_jpm:auto_generated.taps[3] +taps[4] <= shift_taps_jpm:auto_generated.taps[4] +taps[5] <= shift_taps_jpm:auto_generated.taps[5] +taps[6] <= shift_taps_jpm:auto_generated.taps[6] +taps[7] <= shift_taps_jpm:auto_generated.taps[7] +taps[8] <= shift_taps_jpm:auto_generated.taps[8] +taps[9] <= shift_taps_jpm:auto_generated.taps[9] +taps[10] <= shift_taps_jpm:auto_generated.taps[10] +taps[11] <= shift_taps_jpm:auto_generated.taps[11] +taps[12] <= shift_taps_jpm:auto_generated.taps[12] +taps[13] <= shift_taps_jpm:auto_generated.taps[13] +taps[14] <= shift_taps_jpm:auto_generated.taps[14] +taps[15] <= shift_taps_jpm:auto_generated.taps[15] +taps[16] <= shift_taps_jpm:auto_generated.taps[16] +taps[17] <= shift_taps_jpm:auto_generated.taps[17] +taps[18] <= shift_taps_jpm:auto_generated.taps[18] +taps[19] <= shift_taps_jpm:auto_generated.taps[19] +taps[20] <= shift_taps_jpm:auto_generated.taps[20] +taps[21] <= shift_taps_jpm:auto_generated.taps[21] +taps[22] <= shift_taps_jpm:auto_generated.taps[22] +taps[23] <= shift_taps_jpm:auto_generated.taps[23] +taps[24] <= shift_taps_jpm:auto_generated.taps[24] +taps[25] <= shift_taps_jpm:auto_generated.taps[25] +taps[26] <= shift_taps_jpm:auto_generated.taps[26] +taps[27] <= shift_taps_jpm:auto_generated.taps[27] +taps[28] <= shift_taps_jpm:auto_generated.taps[28] +taps[29] <= shift_taps_jpm:auto_generated.taps[29] +taps[30] <= shift_taps_jpm:auto_generated.taps[30] +taps[31] <= shift_taps_jpm:auto_generated.taps[31] +taps[32] <= shift_taps_jpm:auto_generated.taps[32] +taps[33] <= shift_taps_jpm:auto_generated.taps[33] +taps[34] <= shift_taps_jpm:auto_generated.taps[34] +taps[35] <= shift_taps_jpm:auto_generated.taps[35] +taps[36] <= shift_taps_jpm:auto_generated.taps[36] +taps[37] <= shift_taps_jpm:auto_generated.taps[37] +taps[38] <= shift_taps_jpm:auto_generated.taps[38] +taps[39] <= shift_taps_jpm:auto_generated.taps[39] +taps[40] <= shift_taps_jpm:auto_generated.taps[40] +taps[41] <= shift_taps_jpm:auto_generated.taps[41] +taps[42] <= shift_taps_jpm:auto_generated.taps[42] +taps[43] <= shift_taps_jpm:auto_generated.taps[43] +taps[44] <= shift_taps_jpm:auto_generated.taps[44] +taps[45] <= shift_taps_jpm:auto_generated.taps[45] +taps[46] <= shift_taps_jpm:auto_generated.taps[46] +taps[47] <= shift_taps_jpm:auto_generated.taps[47] +taps[48] <= shift_taps_jpm:auto_generated.taps[48] +taps[49] <= shift_taps_jpm:auto_generated.taps[49] +taps[50] <= shift_taps_jpm:auto_generated.taps[50] +taps[51] <= shift_taps_jpm:auto_generated.taps[51] +taps[52] <= shift_taps_jpm:auto_generated.taps[52] +taps[53] <= shift_taps_jpm:auto_generated.taps[53] +taps[54] <= shift_taps_jpm:auto_generated.taps[54] +taps[55] <= shift_taps_jpm:auto_generated.taps[55] +taps[56] <= shift_taps_jpm:auto_generated.taps[56] +taps[57] <= shift_taps_jpm:auto_generated.taps[57] +taps[58] <= shift_taps_jpm:auto_generated.taps[58] +taps[59] <= shift_taps_jpm:auto_generated.taps[59] +taps[60] <= shift_taps_jpm:auto_generated.taps[60] +taps[61] <= shift_taps_jpm:auto_generated.taps[61] +taps[62] <= shift_taps_jpm:auto_generated.taps[62] +taps[63] <= shift_taps_jpm:auto_generated.taps[63] +taps[64] <= shift_taps_jpm:auto_generated.taps[64] +taps[65] <= shift_taps_jpm:auto_generated.taps[65] +taps[66] <= shift_taps_jpm:auto_generated.taps[66] +taps[67] <= shift_taps_jpm:auto_generated.taps[67] +taps[68] <= shift_taps_jpm:auto_generated.taps[68] +taps[69] <= shift_taps_jpm:auto_generated.taps[69] +taps[70] <= shift_taps_jpm:auto_generated.taps[70] +taps[71] <= shift_taps_jpm:auto_generated.taps[71] +taps[72] <= shift_taps_jpm:auto_generated.taps[72] +taps[73] <= shift_taps_jpm:auto_generated.taps[73] +taps[74] <= shift_taps_jpm:auto_generated.taps[74] +taps[75] <= shift_taps_jpm:auto_generated.taps[75] +taps[76] <= shift_taps_jpm:auto_generated.taps[76] +taps[77] <= shift_taps_jpm:auto_generated.taps[77] +taps[78] <= shift_taps_jpm:auto_generated.taps[78] +taps[79] <= shift_taps_jpm:auto_generated.taps[79] +taps[80] <= shift_taps_jpm:auto_generated.taps[80] +taps[81] <= shift_taps_jpm:auto_generated.taps[81] +taps[82] <= shift_taps_jpm:auto_generated.taps[82] +taps[83] <= shift_taps_jpm:auto_generated.taps[83] +taps[84] <= shift_taps_jpm:auto_generated.taps[84] +taps[85] <= shift_taps_jpm:auto_generated.taps[85] +taps[86] <= shift_taps_jpm:auto_generated.taps[86] +taps[87] <= shift_taps_jpm:auto_generated.taps[87] +taps[88] <= shift_taps_jpm:auto_generated.taps[88] +taps[89] <= shift_taps_jpm:auto_generated.taps[89] +aclr => ~NO_FANOUT~ + + +|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated +clken => altsyncram_5n81:altsyncram2.clocken0 +clken => cntr_1tf:cntr1.clk_en +clock => altsyncram_5n81:altsyncram2.clock0 +clock => cntr_1tf:cntr1.clock +shiftin[0] => altsyncram_5n81:altsyncram2.data_a[0] +shiftin[1] => altsyncram_5n81:altsyncram2.data_a[1] +shiftin[2] => altsyncram_5n81:altsyncram2.data_a[2] +shiftin[3] => altsyncram_5n81:altsyncram2.data_a[3] +shiftin[4] => altsyncram_5n81:altsyncram2.data_a[4] +shiftin[5] => altsyncram_5n81:altsyncram2.data_a[5] +shiftin[6] => altsyncram_5n81:altsyncram2.data_a[6] +shiftin[7] => altsyncram_5n81:altsyncram2.data_a[7] +shiftin[8] => altsyncram_5n81:altsyncram2.data_a[8] +shiftin[9] => altsyncram_5n81:altsyncram2.data_a[9] +shiftin[10] => altsyncram_5n81:altsyncram2.data_a[10] +shiftin[11] => altsyncram_5n81:altsyncram2.data_a[11] +shiftin[12] => altsyncram_5n81:altsyncram2.data_a[12] +shiftin[13] => altsyncram_5n81:altsyncram2.data_a[13] +shiftin[14] => altsyncram_5n81:altsyncram2.data_a[14] +shiftin[15] => altsyncram_5n81:altsyncram2.data_a[15] +shiftin[16] => altsyncram_5n81:altsyncram2.data_a[16] +shiftin[17] => altsyncram_5n81:altsyncram2.data_a[17] +shiftin[18] => altsyncram_5n81:altsyncram2.data_a[18] +shiftin[19] => altsyncram_5n81:altsyncram2.data_a[19] +shiftin[20] => altsyncram_5n81:altsyncram2.data_a[20] +shiftin[21] => altsyncram_5n81:altsyncram2.data_a[21] +shiftin[22] => altsyncram_5n81:altsyncram2.data_a[22] +shiftin[23] => altsyncram_5n81:altsyncram2.data_a[23] +shiftin[24] => altsyncram_5n81:altsyncram2.data_a[24] +shiftin[25] => altsyncram_5n81:altsyncram2.data_a[25] +shiftin[26] => altsyncram_5n81:altsyncram2.data_a[26] +shiftin[27] => altsyncram_5n81:altsyncram2.data_a[27] +shiftin[28] => altsyncram_5n81:altsyncram2.data_a[28] +shiftin[29] => altsyncram_5n81:altsyncram2.data_a[29] +shiftout[0] <= altsyncram_5n81:altsyncram2.q_b[60] +shiftout[1] <= altsyncram_5n81:altsyncram2.q_b[61] +shiftout[2] <= altsyncram_5n81:altsyncram2.q_b[62] +shiftout[3] <= altsyncram_5n81:altsyncram2.q_b[63] +shiftout[4] <= altsyncram_5n81:altsyncram2.q_b[64] +shiftout[5] <= altsyncram_5n81:altsyncram2.q_b[65] +shiftout[6] <= altsyncram_5n81:altsyncram2.q_b[66] +shiftout[7] <= altsyncram_5n81:altsyncram2.q_b[67] +shiftout[8] <= altsyncram_5n81:altsyncram2.q_b[68] +shiftout[9] <= altsyncram_5n81:altsyncram2.q_b[69] +shiftout[10] <= altsyncram_5n81:altsyncram2.q_b[70] +shiftout[11] <= altsyncram_5n81:altsyncram2.q_b[71] +shiftout[12] <= altsyncram_5n81:altsyncram2.q_b[72] +shiftout[13] <= altsyncram_5n81:altsyncram2.q_b[73] +shiftout[14] <= altsyncram_5n81:altsyncram2.q_b[74] +shiftout[15] <= altsyncram_5n81:altsyncram2.q_b[75] +shiftout[16] <= altsyncram_5n81:altsyncram2.q_b[76] +shiftout[17] <= altsyncram_5n81:altsyncram2.q_b[77] +shiftout[18] <= altsyncram_5n81:altsyncram2.q_b[78] +shiftout[19] <= altsyncram_5n81:altsyncram2.q_b[79] +shiftout[20] <= altsyncram_5n81:altsyncram2.q_b[80] +shiftout[21] <= altsyncram_5n81:altsyncram2.q_b[81] +shiftout[22] <= altsyncram_5n81:altsyncram2.q_b[82] +shiftout[23] <= altsyncram_5n81:altsyncram2.q_b[83] +shiftout[24] <= altsyncram_5n81:altsyncram2.q_b[84] +shiftout[25] <= altsyncram_5n81:altsyncram2.q_b[85] +shiftout[26] <= altsyncram_5n81:altsyncram2.q_b[86] +shiftout[27] <= altsyncram_5n81:altsyncram2.q_b[87] +shiftout[28] <= altsyncram_5n81:altsyncram2.q_b[88] +shiftout[29] <= altsyncram_5n81:altsyncram2.q_b[89] +taps[0] <= altsyncram_5n81:altsyncram2.q_b[0] +taps[1] <= altsyncram_5n81:altsyncram2.q_b[1] +taps[2] <= altsyncram_5n81:altsyncram2.q_b[2] +taps[3] <= altsyncram_5n81:altsyncram2.q_b[3] +taps[4] <= altsyncram_5n81:altsyncram2.q_b[4] +taps[5] <= altsyncram_5n81:altsyncram2.q_b[5] +taps[6] <= altsyncram_5n81:altsyncram2.q_b[6] +taps[7] <= altsyncram_5n81:altsyncram2.q_b[7] +taps[8] <= altsyncram_5n81:altsyncram2.q_b[8] +taps[9] <= altsyncram_5n81:altsyncram2.q_b[9] +taps[10] <= altsyncram_5n81:altsyncram2.q_b[10] +taps[11] <= altsyncram_5n81:altsyncram2.q_b[11] +taps[12] <= altsyncram_5n81:altsyncram2.q_b[12] +taps[13] <= altsyncram_5n81:altsyncram2.q_b[13] +taps[14] <= altsyncram_5n81:altsyncram2.q_b[14] +taps[15] <= altsyncram_5n81:altsyncram2.q_b[15] +taps[16] <= altsyncram_5n81:altsyncram2.q_b[16] +taps[17] <= altsyncram_5n81:altsyncram2.q_b[17] +taps[18] <= altsyncram_5n81:altsyncram2.q_b[18] +taps[19] <= altsyncram_5n81:altsyncram2.q_b[19] +taps[20] <= altsyncram_5n81:altsyncram2.q_b[20] +taps[21] <= altsyncram_5n81:altsyncram2.q_b[21] +taps[22] <= altsyncram_5n81:altsyncram2.q_b[22] +taps[23] <= altsyncram_5n81:altsyncram2.q_b[23] +taps[24] <= altsyncram_5n81:altsyncram2.q_b[24] +taps[25] <= altsyncram_5n81:altsyncram2.q_b[25] +taps[26] <= altsyncram_5n81:altsyncram2.q_b[26] +taps[27] <= altsyncram_5n81:altsyncram2.q_b[27] +taps[28] <= altsyncram_5n81:altsyncram2.q_b[28] +taps[29] <= altsyncram_5n81:altsyncram2.q_b[29] +taps[30] <= altsyncram_5n81:altsyncram2.q_b[30] +taps[31] <= altsyncram_5n81:altsyncram2.q_b[31] +taps[32] <= altsyncram_5n81:altsyncram2.q_b[32] +taps[33] <= altsyncram_5n81:altsyncram2.q_b[33] +taps[34] <= altsyncram_5n81:altsyncram2.q_b[34] +taps[35] <= altsyncram_5n81:altsyncram2.q_b[35] +taps[36] <= altsyncram_5n81:altsyncram2.q_b[36] +taps[37] <= altsyncram_5n81:altsyncram2.q_b[37] +taps[38] <= altsyncram_5n81:altsyncram2.q_b[38] +taps[39] <= altsyncram_5n81:altsyncram2.q_b[39] +taps[40] <= altsyncram_5n81:altsyncram2.q_b[40] +taps[41] <= altsyncram_5n81:altsyncram2.q_b[41] +taps[42] <= altsyncram_5n81:altsyncram2.q_b[42] +taps[43] <= altsyncram_5n81:altsyncram2.q_b[43] +taps[44] <= altsyncram_5n81:altsyncram2.q_b[44] +taps[45] <= altsyncram_5n81:altsyncram2.q_b[45] +taps[46] <= altsyncram_5n81:altsyncram2.q_b[46] +taps[47] <= altsyncram_5n81:altsyncram2.q_b[47] +taps[48] <= altsyncram_5n81:altsyncram2.q_b[48] +taps[49] <= altsyncram_5n81:altsyncram2.q_b[49] +taps[50] <= altsyncram_5n81:altsyncram2.q_b[50] +taps[51] <= altsyncram_5n81:altsyncram2.q_b[51] +taps[52] <= altsyncram_5n81:altsyncram2.q_b[52] +taps[53] <= altsyncram_5n81:altsyncram2.q_b[53] +taps[54] <= altsyncram_5n81:altsyncram2.q_b[54] +taps[55] <= altsyncram_5n81:altsyncram2.q_b[55] +taps[56] <= altsyncram_5n81:altsyncram2.q_b[56] +taps[57] <= altsyncram_5n81:altsyncram2.q_b[57] +taps[58] <= altsyncram_5n81:altsyncram2.q_b[58] +taps[59] <= altsyncram_5n81:altsyncram2.q_b[59] +taps[60] <= altsyncram_5n81:altsyncram2.q_b[60] +taps[61] <= altsyncram_5n81:altsyncram2.q_b[61] +taps[62] <= altsyncram_5n81:altsyncram2.q_b[62] +taps[63] <= altsyncram_5n81:altsyncram2.q_b[63] +taps[64] <= altsyncram_5n81:altsyncram2.q_b[64] +taps[65] <= altsyncram_5n81:altsyncram2.q_b[65] +taps[66] <= altsyncram_5n81:altsyncram2.q_b[66] +taps[67] <= altsyncram_5n81:altsyncram2.q_b[67] +taps[68] <= altsyncram_5n81:altsyncram2.q_b[68] +taps[69] <= altsyncram_5n81:altsyncram2.q_b[69] +taps[70] <= altsyncram_5n81:altsyncram2.q_b[70] +taps[71] <= altsyncram_5n81:altsyncram2.q_b[71] +taps[72] <= altsyncram_5n81:altsyncram2.q_b[72] +taps[73] <= altsyncram_5n81:altsyncram2.q_b[73] +taps[74] <= altsyncram_5n81:altsyncram2.q_b[74] +taps[75] <= altsyncram_5n81:altsyncram2.q_b[75] +taps[76] <= altsyncram_5n81:altsyncram2.q_b[76] +taps[77] <= altsyncram_5n81:altsyncram2.q_b[77] +taps[78] <= altsyncram_5n81:altsyncram2.q_b[78] +taps[79] <= altsyncram_5n81:altsyncram2.q_b[79] +taps[80] <= altsyncram_5n81:altsyncram2.q_b[80] +taps[81] <= altsyncram_5n81:altsyncram2.q_b[81] +taps[82] <= altsyncram_5n81:altsyncram2.q_b[82] +taps[83] <= altsyncram_5n81:altsyncram2.q_b[83] +taps[84] <= altsyncram_5n81:altsyncram2.q_b[84] +taps[85] <= altsyncram_5n81:altsyncram2.q_b[85] +taps[86] <= altsyncram_5n81:altsyncram2.q_b[86] +taps[87] <= altsyncram_5n81:altsyncram2.q_b[87] +taps[88] <= altsyncram_5n81:altsyncram2.q_b[88] +taps[89] <= altsyncram_5n81:altsyncram2.q_b[89] + + +|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2 +address_a[0] => ram_block3a0.PORTAADDR +address_a[0] => ram_block3a1.PORTAADDR +address_a[0] => ram_block3a2.PORTAADDR +address_a[0] => ram_block3a3.PORTAADDR +address_a[0] => ram_block3a4.PORTAADDR +address_a[0] => ram_block3a5.PORTAADDR +address_a[0] => ram_block3a6.PORTAADDR +address_a[0] => ram_block3a7.PORTAADDR +address_a[0] => ram_block3a8.PORTAADDR +address_a[0] => ram_block3a9.PORTAADDR +address_a[0] => ram_block3a10.PORTAADDR +address_a[0] => ram_block3a11.PORTAADDR +address_a[0] => ram_block3a12.PORTAADDR +address_a[0] => ram_block3a13.PORTAADDR +address_a[0] => ram_block3a14.PORTAADDR +address_a[0] => ram_block3a15.PORTAADDR +address_a[0] => ram_block3a16.PORTAADDR +address_a[0] => ram_block3a17.PORTAADDR +address_a[0] => ram_block3a18.PORTAADDR +address_a[0] => ram_block3a19.PORTAADDR +address_a[0] => ram_block3a20.PORTAADDR +address_a[0] => ram_block3a21.PORTAADDR +address_a[0] => ram_block3a22.PORTAADDR +address_a[0] => ram_block3a23.PORTAADDR +address_a[0] => ram_block3a24.PORTAADDR +address_a[0] => ram_block3a25.PORTAADDR +address_a[0] => ram_block3a26.PORTAADDR +address_a[0] => ram_block3a27.PORTAADDR +address_a[0] => ram_block3a28.PORTAADDR +address_a[0] => ram_block3a29.PORTAADDR +address_a[0] => ram_block3a30.PORTAADDR +address_a[0] => ram_block3a31.PORTAADDR +address_a[0] => ram_block3a32.PORTAADDR +address_a[0] => ram_block3a33.PORTAADDR +address_a[0] => ram_block3a34.PORTAADDR +address_a[0] => ram_block3a35.PORTAADDR +address_a[0] => ram_block3a36.PORTAADDR +address_a[0] => ram_block3a37.PORTAADDR +address_a[0] => ram_block3a38.PORTAADDR +address_a[0] => ram_block3a39.PORTAADDR +address_a[0] => ram_block3a40.PORTAADDR +address_a[0] => ram_block3a41.PORTAADDR +address_a[0] => ram_block3a42.PORTAADDR +address_a[0] => ram_block3a43.PORTAADDR +address_a[0] => ram_block3a44.PORTAADDR +address_a[0] => ram_block3a45.PORTAADDR +address_a[0] => ram_block3a46.PORTAADDR +address_a[0] => ram_block3a47.PORTAADDR +address_a[0] => ram_block3a48.PORTAADDR +address_a[0] => ram_block3a49.PORTAADDR +address_a[0] => ram_block3a50.PORTAADDR +address_a[0] => ram_block3a51.PORTAADDR +address_a[0] => ram_block3a52.PORTAADDR +address_a[0] => ram_block3a53.PORTAADDR +address_a[0] => ram_block3a54.PORTAADDR +address_a[0] => ram_block3a55.PORTAADDR +address_a[0] => ram_block3a56.PORTAADDR +address_a[0] => ram_block3a57.PORTAADDR +address_a[0] => ram_block3a58.PORTAADDR +address_a[0] => ram_block3a59.PORTAADDR +address_a[0] => ram_block3a60.PORTAADDR +address_a[0] => ram_block3a61.PORTAADDR +address_a[0] => ram_block3a62.PORTAADDR +address_a[0] => ram_block3a63.PORTAADDR +address_a[0] => ram_block3a64.PORTAADDR +address_a[0] => ram_block3a65.PORTAADDR +address_a[0] => ram_block3a66.PORTAADDR +address_a[0] => ram_block3a67.PORTAADDR +address_a[0] => ram_block3a68.PORTAADDR +address_a[0] => ram_block3a69.PORTAADDR +address_a[0] => ram_block3a70.PORTAADDR +address_a[0] => ram_block3a71.PORTAADDR +address_a[0] => ram_block3a72.PORTAADDR +address_a[0] => ram_block3a73.PORTAADDR +address_a[0] => ram_block3a74.PORTAADDR +address_a[0] => ram_block3a75.PORTAADDR +address_a[0] => ram_block3a76.PORTAADDR +address_a[0] => ram_block3a77.PORTAADDR +address_a[0] => ram_block3a78.PORTAADDR +address_a[0] => ram_block3a79.PORTAADDR +address_a[0] => ram_block3a80.PORTAADDR +address_a[0] => ram_block3a81.PORTAADDR +address_a[0] => ram_block3a82.PORTAADDR +address_a[0] => ram_block3a83.PORTAADDR +address_a[0] => ram_block3a84.PORTAADDR +address_a[0] => ram_block3a85.PORTAADDR +address_a[0] => ram_block3a86.PORTAADDR +address_a[0] => ram_block3a87.PORTAADDR +address_a[0] => ram_block3a88.PORTAADDR +address_a[0] => ram_block3a89.PORTAADDR +address_a[1] => ram_block3a0.PORTAADDR1 +address_a[1] => ram_block3a1.PORTAADDR1 +address_a[1] => ram_block3a2.PORTAADDR1 +address_a[1] => ram_block3a3.PORTAADDR1 +address_a[1] => ram_block3a4.PORTAADDR1 +address_a[1] => ram_block3a5.PORTAADDR1 +address_a[1] => ram_block3a6.PORTAADDR1 +address_a[1] => ram_block3a7.PORTAADDR1 +address_a[1] => ram_block3a8.PORTAADDR1 +address_a[1] => ram_block3a9.PORTAADDR1 +address_a[1] => ram_block3a10.PORTAADDR1 +address_a[1] => ram_block3a11.PORTAADDR1 +address_a[1] => ram_block3a12.PORTAADDR1 +address_a[1] => ram_block3a13.PORTAADDR1 +address_a[1] => ram_block3a14.PORTAADDR1 +address_a[1] => ram_block3a15.PORTAADDR1 +address_a[1] => ram_block3a16.PORTAADDR1 +address_a[1] => ram_block3a17.PORTAADDR1 +address_a[1] => ram_block3a18.PORTAADDR1 +address_a[1] => ram_block3a19.PORTAADDR1 +address_a[1] => ram_block3a20.PORTAADDR1 +address_a[1] => ram_block3a21.PORTAADDR1 +address_a[1] => ram_block3a22.PORTAADDR1 +address_a[1] => ram_block3a23.PORTAADDR1 +address_a[1] => ram_block3a24.PORTAADDR1 +address_a[1] => ram_block3a25.PORTAADDR1 +address_a[1] => ram_block3a26.PORTAADDR1 +address_a[1] => ram_block3a27.PORTAADDR1 +address_a[1] => ram_block3a28.PORTAADDR1 +address_a[1] => ram_block3a29.PORTAADDR1 +address_a[1] => ram_block3a30.PORTAADDR1 +address_a[1] => ram_block3a31.PORTAADDR1 +address_a[1] => ram_block3a32.PORTAADDR1 +address_a[1] => ram_block3a33.PORTAADDR1 +address_a[1] => ram_block3a34.PORTAADDR1 +address_a[1] => ram_block3a35.PORTAADDR1 +address_a[1] => ram_block3a36.PORTAADDR1 +address_a[1] => ram_block3a37.PORTAADDR1 +address_a[1] => ram_block3a38.PORTAADDR1 +address_a[1] => ram_block3a39.PORTAADDR1 +address_a[1] => ram_block3a40.PORTAADDR1 +address_a[1] => ram_block3a41.PORTAADDR1 +address_a[1] => ram_block3a42.PORTAADDR1 +address_a[1] => ram_block3a43.PORTAADDR1 +address_a[1] => ram_block3a44.PORTAADDR1 +address_a[1] => ram_block3a45.PORTAADDR1 +address_a[1] => ram_block3a46.PORTAADDR1 +address_a[1] => ram_block3a47.PORTAADDR1 +address_a[1] => ram_block3a48.PORTAADDR1 +address_a[1] => ram_block3a49.PORTAADDR1 +address_a[1] => ram_block3a50.PORTAADDR1 +address_a[1] => ram_block3a51.PORTAADDR1 +address_a[1] => ram_block3a52.PORTAADDR1 +address_a[1] => ram_block3a53.PORTAADDR1 +address_a[1] => ram_block3a54.PORTAADDR1 +address_a[1] => ram_block3a55.PORTAADDR1 +address_a[1] => ram_block3a56.PORTAADDR1 +address_a[1] => ram_block3a57.PORTAADDR1 +address_a[1] => ram_block3a58.PORTAADDR1 +address_a[1] => ram_block3a59.PORTAADDR1 +address_a[1] => ram_block3a60.PORTAADDR1 +address_a[1] => ram_block3a61.PORTAADDR1 +address_a[1] => ram_block3a62.PORTAADDR1 +address_a[1] => ram_block3a63.PORTAADDR1 +address_a[1] => ram_block3a64.PORTAADDR1 +address_a[1] => ram_block3a65.PORTAADDR1 +address_a[1] => ram_block3a66.PORTAADDR1 +address_a[1] => ram_block3a67.PORTAADDR1 +address_a[1] => ram_block3a68.PORTAADDR1 +address_a[1] => ram_block3a69.PORTAADDR1 +address_a[1] => ram_block3a70.PORTAADDR1 +address_a[1] => ram_block3a71.PORTAADDR1 +address_a[1] => ram_block3a72.PORTAADDR1 +address_a[1] => ram_block3a73.PORTAADDR1 +address_a[1] => ram_block3a74.PORTAADDR1 +address_a[1] => ram_block3a75.PORTAADDR1 +address_a[1] => ram_block3a76.PORTAADDR1 +address_a[1] => ram_block3a77.PORTAADDR1 +address_a[1] => ram_block3a78.PORTAADDR1 +address_a[1] => ram_block3a79.PORTAADDR1 +address_a[1] => ram_block3a80.PORTAADDR1 +address_a[1] => ram_block3a81.PORTAADDR1 +address_a[1] => ram_block3a82.PORTAADDR1 +address_a[1] => ram_block3a83.PORTAADDR1 +address_a[1] => ram_block3a84.PORTAADDR1 +address_a[1] => ram_block3a85.PORTAADDR1 +address_a[1] => ram_block3a86.PORTAADDR1 +address_a[1] => ram_block3a87.PORTAADDR1 +address_a[1] => ram_block3a88.PORTAADDR1 +address_a[1] => ram_block3a89.PORTAADDR1 +address_a[2] => ram_block3a0.PORTAADDR2 +address_a[2] => ram_block3a1.PORTAADDR2 +address_a[2] => ram_block3a2.PORTAADDR2 +address_a[2] => ram_block3a3.PORTAADDR2 +address_a[2] => ram_block3a4.PORTAADDR2 +address_a[2] => ram_block3a5.PORTAADDR2 +address_a[2] => ram_block3a6.PORTAADDR2 +address_a[2] => ram_block3a7.PORTAADDR2 +address_a[2] => ram_block3a8.PORTAADDR2 +address_a[2] => ram_block3a9.PORTAADDR2 +address_a[2] => ram_block3a10.PORTAADDR2 +address_a[2] => ram_block3a11.PORTAADDR2 +address_a[2] => ram_block3a12.PORTAADDR2 +address_a[2] => ram_block3a13.PORTAADDR2 +address_a[2] => ram_block3a14.PORTAADDR2 +address_a[2] => ram_block3a15.PORTAADDR2 +address_a[2] => ram_block3a16.PORTAADDR2 +address_a[2] => ram_block3a17.PORTAADDR2 +address_a[2] => ram_block3a18.PORTAADDR2 +address_a[2] => ram_block3a19.PORTAADDR2 +address_a[2] => ram_block3a20.PORTAADDR2 +address_a[2] => ram_block3a21.PORTAADDR2 +address_a[2] => ram_block3a22.PORTAADDR2 +address_a[2] => ram_block3a23.PORTAADDR2 +address_a[2] => ram_block3a24.PORTAADDR2 +address_a[2] => ram_block3a25.PORTAADDR2 +address_a[2] => ram_block3a26.PORTAADDR2 +address_a[2] => ram_block3a27.PORTAADDR2 +address_a[2] => ram_block3a28.PORTAADDR2 +address_a[2] => ram_block3a29.PORTAADDR2 +address_a[2] => ram_block3a30.PORTAADDR2 +address_a[2] => ram_block3a31.PORTAADDR2 +address_a[2] => ram_block3a32.PORTAADDR2 +address_a[2] => ram_block3a33.PORTAADDR2 +address_a[2] => ram_block3a34.PORTAADDR2 +address_a[2] => ram_block3a35.PORTAADDR2 +address_a[2] => ram_block3a36.PORTAADDR2 +address_a[2] => ram_block3a37.PORTAADDR2 +address_a[2] => ram_block3a38.PORTAADDR2 +address_a[2] => ram_block3a39.PORTAADDR2 +address_a[2] => ram_block3a40.PORTAADDR2 +address_a[2] => ram_block3a41.PORTAADDR2 +address_a[2] => ram_block3a42.PORTAADDR2 +address_a[2] => ram_block3a43.PORTAADDR2 +address_a[2] => ram_block3a44.PORTAADDR2 +address_a[2] => ram_block3a45.PORTAADDR2 +address_a[2] => ram_block3a46.PORTAADDR2 +address_a[2] => ram_block3a47.PORTAADDR2 +address_a[2] => ram_block3a48.PORTAADDR2 +address_a[2] => ram_block3a49.PORTAADDR2 +address_a[2] => ram_block3a50.PORTAADDR2 +address_a[2] => ram_block3a51.PORTAADDR2 +address_a[2] => ram_block3a52.PORTAADDR2 +address_a[2] => ram_block3a53.PORTAADDR2 +address_a[2] => ram_block3a54.PORTAADDR2 +address_a[2] => ram_block3a55.PORTAADDR2 +address_a[2] => ram_block3a56.PORTAADDR2 +address_a[2] => ram_block3a57.PORTAADDR2 +address_a[2] => ram_block3a58.PORTAADDR2 +address_a[2] => ram_block3a59.PORTAADDR2 +address_a[2] => ram_block3a60.PORTAADDR2 +address_a[2] => ram_block3a61.PORTAADDR2 +address_a[2] => ram_block3a62.PORTAADDR2 +address_a[2] => ram_block3a63.PORTAADDR2 +address_a[2] => ram_block3a64.PORTAADDR2 +address_a[2] => ram_block3a65.PORTAADDR2 +address_a[2] => ram_block3a66.PORTAADDR2 +address_a[2] => ram_block3a67.PORTAADDR2 +address_a[2] => ram_block3a68.PORTAADDR2 +address_a[2] => ram_block3a69.PORTAADDR2 +address_a[2] => ram_block3a70.PORTAADDR2 +address_a[2] => ram_block3a71.PORTAADDR2 +address_a[2] => ram_block3a72.PORTAADDR2 +address_a[2] => ram_block3a73.PORTAADDR2 +address_a[2] => ram_block3a74.PORTAADDR2 +address_a[2] => ram_block3a75.PORTAADDR2 +address_a[2] => ram_block3a76.PORTAADDR2 +address_a[2] => ram_block3a77.PORTAADDR2 +address_a[2] => ram_block3a78.PORTAADDR2 +address_a[2] => ram_block3a79.PORTAADDR2 +address_a[2] => ram_block3a80.PORTAADDR2 +address_a[2] => ram_block3a81.PORTAADDR2 +address_a[2] => ram_block3a82.PORTAADDR2 +address_a[2] => ram_block3a83.PORTAADDR2 +address_a[2] => ram_block3a84.PORTAADDR2 +address_a[2] => ram_block3a85.PORTAADDR2 +address_a[2] => ram_block3a86.PORTAADDR2 +address_a[2] => ram_block3a87.PORTAADDR2 +address_a[2] => ram_block3a88.PORTAADDR2 +address_a[2] => ram_block3a89.PORTAADDR2 +address_a[3] => ram_block3a0.PORTAADDR3 +address_a[3] => ram_block3a1.PORTAADDR3 +address_a[3] => ram_block3a2.PORTAADDR3 +address_a[3] => ram_block3a3.PORTAADDR3 +address_a[3] => ram_block3a4.PORTAADDR3 +address_a[3] => ram_block3a5.PORTAADDR3 +address_a[3] => ram_block3a6.PORTAADDR3 +address_a[3] => ram_block3a7.PORTAADDR3 +address_a[3] => ram_block3a8.PORTAADDR3 +address_a[3] => ram_block3a9.PORTAADDR3 +address_a[3] => ram_block3a10.PORTAADDR3 +address_a[3] => ram_block3a11.PORTAADDR3 +address_a[3] => ram_block3a12.PORTAADDR3 +address_a[3] => ram_block3a13.PORTAADDR3 +address_a[3] => ram_block3a14.PORTAADDR3 +address_a[3] => ram_block3a15.PORTAADDR3 +address_a[3] => ram_block3a16.PORTAADDR3 +address_a[3] => ram_block3a17.PORTAADDR3 +address_a[3] => ram_block3a18.PORTAADDR3 +address_a[3] => ram_block3a19.PORTAADDR3 +address_a[3] => ram_block3a20.PORTAADDR3 +address_a[3] => ram_block3a21.PORTAADDR3 +address_a[3] => ram_block3a22.PORTAADDR3 +address_a[3] => ram_block3a23.PORTAADDR3 +address_a[3] => ram_block3a24.PORTAADDR3 +address_a[3] => ram_block3a25.PORTAADDR3 +address_a[3] => ram_block3a26.PORTAADDR3 +address_a[3] => ram_block3a27.PORTAADDR3 +address_a[3] => ram_block3a28.PORTAADDR3 +address_a[3] => ram_block3a29.PORTAADDR3 +address_a[3] => ram_block3a30.PORTAADDR3 +address_a[3] => ram_block3a31.PORTAADDR3 +address_a[3] => ram_block3a32.PORTAADDR3 +address_a[3] => ram_block3a33.PORTAADDR3 +address_a[3] => ram_block3a34.PORTAADDR3 +address_a[3] => ram_block3a35.PORTAADDR3 +address_a[3] => ram_block3a36.PORTAADDR3 +address_a[3] => ram_block3a37.PORTAADDR3 +address_a[3] => ram_block3a38.PORTAADDR3 +address_a[3] => ram_block3a39.PORTAADDR3 +address_a[3] => ram_block3a40.PORTAADDR3 +address_a[3] => ram_block3a41.PORTAADDR3 +address_a[3] => ram_block3a42.PORTAADDR3 +address_a[3] => ram_block3a43.PORTAADDR3 +address_a[3] => ram_block3a44.PORTAADDR3 +address_a[3] => ram_block3a45.PORTAADDR3 +address_a[3] => ram_block3a46.PORTAADDR3 +address_a[3] => ram_block3a47.PORTAADDR3 +address_a[3] => ram_block3a48.PORTAADDR3 +address_a[3] => ram_block3a49.PORTAADDR3 +address_a[3] => ram_block3a50.PORTAADDR3 +address_a[3] => ram_block3a51.PORTAADDR3 +address_a[3] => ram_block3a52.PORTAADDR3 +address_a[3] => ram_block3a53.PORTAADDR3 +address_a[3] => ram_block3a54.PORTAADDR3 +address_a[3] => ram_block3a55.PORTAADDR3 +address_a[3] => ram_block3a56.PORTAADDR3 +address_a[3] => ram_block3a57.PORTAADDR3 +address_a[3] => ram_block3a58.PORTAADDR3 +address_a[3] => ram_block3a59.PORTAADDR3 +address_a[3] => ram_block3a60.PORTAADDR3 +address_a[3] => ram_block3a61.PORTAADDR3 +address_a[3] => ram_block3a62.PORTAADDR3 +address_a[3] => ram_block3a63.PORTAADDR3 +address_a[3] => ram_block3a64.PORTAADDR3 +address_a[3] => ram_block3a65.PORTAADDR3 +address_a[3] => ram_block3a66.PORTAADDR3 +address_a[3] => ram_block3a67.PORTAADDR3 +address_a[3] => ram_block3a68.PORTAADDR3 +address_a[3] => ram_block3a69.PORTAADDR3 +address_a[3] => ram_block3a70.PORTAADDR3 +address_a[3] => ram_block3a71.PORTAADDR3 +address_a[3] => ram_block3a72.PORTAADDR3 +address_a[3] => ram_block3a73.PORTAADDR3 +address_a[3] => ram_block3a74.PORTAADDR3 +address_a[3] => ram_block3a75.PORTAADDR3 +address_a[3] => ram_block3a76.PORTAADDR3 +address_a[3] => ram_block3a77.PORTAADDR3 +address_a[3] => ram_block3a78.PORTAADDR3 +address_a[3] => ram_block3a79.PORTAADDR3 +address_a[3] => ram_block3a80.PORTAADDR3 +address_a[3] => ram_block3a81.PORTAADDR3 +address_a[3] => ram_block3a82.PORTAADDR3 +address_a[3] => ram_block3a83.PORTAADDR3 +address_a[3] => ram_block3a84.PORTAADDR3 +address_a[3] => ram_block3a85.PORTAADDR3 +address_a[3] => ram_block3a86.PORTAADDR3 +address_a[3] => ram_block3a87.PORTAADDR3 +address_a[3] => ram_block3a88.PORTAADDR3 +address_a[3] => ram_block3a89.PORTAADDR3 +address_a[4] => ram_block3a0.PORTAADDR4 +address_a[4] => ram_block3a1.PORTAADDR4 +address_a[4] => ram_block3a2.PORTAADDR4 +address_a[4] => ram_block3a3.PORTAADDR4 +address_a[4] => ram_block3a4.PORTAADDR4 +address_a[4] => ram_block3a5.PORTAADDR4 +address_a[4] => ram_block3a6.PORTAADDR4 +address_a[4] => ram_block3a7.PORTAADDR4 +address_a[4] => ram_block3a8.PORTAADDR4 +address_a[4] => ram_block3a9.PORTAADDR4 +address_a[4] => ram_block3a10.PORTAADDR4 +address_a[4] => ram_block3a11.PORTAADDR4 +address_a[4] => ram_block3a12.PORTAADDR4 +address_a[4] => ram_block3a13.PORTAADDR4 +address_a[4] => ram_block3a14.PORTAADDR4 +address_a[4] => ram_block3a15.PORTAADDR4 +address_a[4] => ram_block3a16.PORTAADDR4 +address_a[4] => ram_block3a17.PORTAADDR4 +address_a[4] => ram_block3a18.PORTAADDR4 +address_a[4] => ram_block3a19.PORTAADDR4 +address_a[4] => ram_block3a20.PORTAADDR4 +address_a[4] => ram_block3a21.PORTAADDR4 +address_a[4] => ram_block3a22.PORTAADDR4 +address_a[4] => ram_block3a23.PORTAADDR4 +address_a[4] => ram_block3a24.PORTAADDR4 +address_a[4] => ram_block3a25.PORTAADDR4 +address_a[4] => ram_block3a26.PORTAADDR4 +address_a[4] => ram_block3a27.PORTAADDR4 +address_a[4] => ram_block3a28.PORTAADDR4 +address_a[4] => ram_block3a29.PORTAADDR4 +address_a[4] => ram_block3a30.PORTAADDR4 +address_a[4] => ram_block3a31.PORTAADDR4 +address_a[4] => ram_block3a32.PORTAADDR4 +address_a[4] => ram_block3a33.PORTAADDR4 +address_a[4] => ram_block3a34.PORTAADDR4 +address_a[4] => ram_block3a35.PORTAADDR4 +address_a[4] => ram_block3a36.PORTAADDR4 +address_a[4] => ram_block3a37.PORTAADDR4 +address_a[4] => ram_block3a38.PORTAADDR4 +address_a[4] => ram_block3a39.PORTAADDR4 +address_a[4] => ram_block3a40.PORTAADDR4 +address_a[4] => ram_block3a41.PORTAADDR4 +address_a[4] => ram_block3a42.PORTAADDR4 +address_a[4] => ram_block3a43.PORTAADDR4 +address_a[4] => ram_block3a44.PORTAADDR4 +address_a[4] => ram_block3a45.PORTAADDR4 +address_a[4] => ram_block3a46.PORTAADDR4 +address_a[4] => ram_block3a47.PORTAADDR4 +address_a[4] => ram_block3a48.PORTAADDR4 +address_a[4] => ram_block3a49.PORTAADDR4 +address_a[4] => ram_block3a50.PORTAADDR4 +address_a[4] => ram_block3a51.PORTAADDR4 +address_a[4] => ram_block3a52.PORTAADDR4 +address_a[4] => ram_block3a53.PORTAADDR4 +address_a[4] => ram_block3a54.PORTAADDR4 +address_a[4] => ram_block3a55.PORTAADDR4 +address_a[4] => ram_block3a56.PORTAADDR4 +address_a[4] => ram_block3a57.PORTAADDR4 +address_a[4] => ram_block3a58.PORTAADDR4 +address_a[4] => ram_block3a59.PORTAADDR4 +address_a[4] => ram_block3a60.PORTAADDR4 +address_a[4] => ram_block3a61.PORTAADDR4 +address_a[4] => ram_block3a62.PORTAADDR4 +address_a[4] => ram_block3a63.PORTAADDR4 +address_a[4] => ram_block3a64.PORTAADDR4 +address_a[4] => ram_block3a65.PORTAADDR4 +address_a[4] => ram_block3a66.PORTAADDR4 +address_a[4] => ram_block3a67.PORTAADDR4 +address_a[4] => ram_block3a68.PORTAADDR4 +address_a[4] => ram_block3a69.PORTAADDR4 +address_a[4] => ram_block3a70.PORTAADDR4 +address_a[4] => ram_block3a71.PORTAADDR4 +address_a[4] => ram_block3a72.PORTAADDR4 +address_a[4] => ram_block3a73.PORTAADDR4 +address_a[4] => ram_block3a74.PORTAADDR4 +address_a[4] => ram_block3a75.PORTAADDR4 +address_a[4] => ram_block3a76.PORTAADDR4 +address_a[4] => ram_block3a77.PORTAADDR4 +address_a[4] => ram_block3a78.PORTAADDR4 +address_a[4] => ram_block3a79.PORTAADDR4 +address_a[4] => ram_block3a80.PORTAADDR4 +address_a[4] => ram_block3a81.PORTAADDR4 +address_a[4] => ram_block3a82.PORTAADDR4 +address_a[4] => ram_block3a83.PORTAADDR4 +address_a[4] => ram_block3a84.PORTAADDR4 +address_a[4] => ram_block3a85.PORTAADDR4 +address_a[4] => ram_block3a86.PORTAADDR4 +address_a[4] => ram_block3a87.PORTAADDR4 +address_a[4] => ram_block3a88.PORTAADDR4 +address_a[4] => ram_block3a89.PORTAADDR4 +address_a[5] => ram_block3a0.PORTAADDR5 +address_a[5] => ram_block3a1.PORTAADDR5 +address_a[5] => ram_block3a2.PORTAADDR5 +address_a[5] => ram_block3a3.PORTAADDR5 +address_a[5] => ram_block3a4.PORTAADDR5 +address_a[5] => ram_block3a5.PORTAADDR5 +address_a[5] => ram_block3a6.PORTAADDR5 +address_a[5] => ram_block3a7.PORTAADDR5 +address_a[5] => ram_block3a8.PORTAADDR5 +address_a[5] => ram_block3a9.PORTAADDR5 +address_a[5] => ram_block3a10.PORTAADDR5 +address_a[5] => ram_block3a11.PORTAADDR5 +address_a[5] => ram_block3a12.PORTAADDR5 +address_a[5] => ram_block3a13.PORTAADDR5 +address_a[5] => ram_block3a14.PORTAADDR5 +address_a[5] => ram_block3a15.PORTAADDR5 +address_a[5] => ram_block3a16.PORTAADDR5 +address_a[5] => ram_block3a17.PORTAADDR5 +address_a[5] => ram_block3a18.PORTAADDR5 +address_a[5] => ram_block3a19.PORTAADDR5 +address_a[5] => ram_block3a20.PORTAADDR5 +address_a[5] => ram_block3a21.PORTAADDR5 +address_a[5] => ram_block3a22.PORTAADDR5 +address_a[5] => ram_block3a23.PORTAADDR5 +address_a[5] => ram_block3a24.PORTAADDR5 +address_a[5] => ram_block3a25.PORTAADDR5 +address_a[5] => ram_block3a26.PORTAADDR5 +address_a[5] => ram_block3a27.PORTAADDR5 +address_a[5] => ram_block3a28.PORTAADDR5 +address_a[5] => ram_block3a29.PORTAADDR5 +address_a[5] => ram_block3a30.PORTAADDR5 +address_a[5] => ram_block3a31.PORTAADDR5 +address_a[5] => ram_block3a32.PORTAADDR5 +address_a[5] => ram_block3a33.PORTAADDR5 +address_a[5] => ram_block3a34.PORTAADDR5 +address_a[5] => ram_block3a35.PORTAADDR5 +address_a[5] => ram_block3a36.PORTAADDR5 +address_a[5] => ram_block3a37.PORTAADDR5 +address_a[5] => ram_block3a38.PORTAADDR5 +address_a[5] => ram_block3a39.PORTAADDR5 +address_a[5] => ram_block3a40.PORTAADDR5 +address_a[5] => ram_block3a41.PORTAADDR5 +address_a[5] => ram_block3a42.PORTAADDR5 +address_a[5] => ram_block3a43.PORTAADDR5 +address_a[5] => ram_block3a44.PORTAADDR5 +address_a[5] => ram_block3a45.PORTAADDR5 +address_a[5] => ram_block3a46.PORTAADDR5 +address_a[5] => ram_block3a47.PORTAADDR5 +address_a[5] => ram_block3a48.PORTAADDR5 +address_a[5] => ram_block3a49.PORTAADDR5 +address_a[5] => ram_block3a50.PORTAADDR5 +address_a[5] => ram_block3a51.PORTAADDR5 +address_a[5] => ram_block3a52.PORTAADDR5 +address_a[5] => ram_block3a53.PORTAADDR5 +address_a[5] => ram_block3a54.PORTAADDR5 +address_a[5] => ram_block3a55.PORTAADDR5 +address_a[5] => ram_block3a56.PORTAADDR5 +address_a[5] => ram_block3a57.PORTAADDR5 +address_a[5] => ram_block3a58.PORTAADDR5 +address_a[5] => ram_block3a59.PORTAADDR5 +address_a[5] => ram_block3a60.PORTAADDR5 +address_a[5] => ram_block3a61.PORTAADDR5 +address_a[5] => ram_block3a62.PORTAADDR5 +address_a[5] => ram_block3a63.PORTAADDR5 +address_a[5] => ram_block3a64.PORTAADDR5 +address_a[5] => ram_block3a65.PORTAADDR5 +address_a[5] => ram_block3a66.PORTAADDR5 +address_a[5] => ram_block3a67.PORTAADDR5 +address_a[5] => ram_block3a68.PORTAADDR5 +address_a[5] => ram_block3a69.PORTAADDR5 +address_a[5] => ram_block3a70.PORTAADDR5 +address_a[5] => ram_block3a71.PORTAADDR5 +address_a[5] => ram_block3a72.PORTAADDR5 +address_a[5] => ram_block3a73.PORTAADDR5 +address_a[5] => ram_block3a74.PORTAADDR5 +address_a[5] => ram_block3a75.PORTAADDR5 +address_a[5] => ram_block3a76.PORTAADDR5 +address_a[5] => ram_block3a77.PORTAADDR5 +address_a[5] => ram_block3a78.PORTAADDR5 +address_a[5] => ram_block3a79.PORTAADDR5 +address_a[5] => ram_block3a80.PORTAADDR5 +address_a[5] => ram_block3a81.PORTAADDR5 +address_a[5] => ram_block3a82.PORTAADDR5 +address_a[5] => ram_block3a83.PORTAADDR5 +address_a[5] => ram_block3a84.PORTAADDR5 +address_a[5] => ram_block3a85.PORTAADDR5 +address_a[5] => ram_block3a86.PORTAADDR5 +address_a[5] => ram_block3a87.PORTAADDR5 +address_a[5] => ram_block3a88.PORTAADDR5 +address_a[5] => ram_block3a89.PORTAADDR5 +address_a[6] => ram_block3a0.PORTAADDR6 +address_a[6] => ram_block3a1.PORTAADDR6 +address_a[6] => ram_block3a2.PORTAADDR6 +address_a[6] => ram_block3a3.PORTAADDR6 +address_a[6] => ram_block3a4.PORTAADDR6 +address_a[6] => ram_block3a5.PORTAADDR6 +address_a[6] => ram_block3a6.PORTAADDR6 +address_a[6] => ram_block3a7.PORTAADDR6 +address_a[6] => ram_block3a8.PORTAADDR6 +address_a[6] => ram_block3a9.PORTAADDR6 +address_a[6] => ram_block3a10.PORTAADDR6 +address_a[6] => ram_block3a11.PORTAADDR6 +address_a[6] => ram_block3a12.PORTAADDR6 +address_a[6] => ram_block3a13.PORTAADDR6 +address_a[6] => ram_block3a14.PORTAADDR6 +address_a[6] => ram_block3a15.PORTAADDR6 +address_a[6] => ram_block3a16.PORTAADDR6 +address_a[6] => ram_block3a17.PORTAADDR6 +address_a[6] => ram_block3a18.PORTAADDR6 +address_a[6] => ram_block3a19.PORTAADDR6 +address_a[6] => ram_block3a20.PORTAADDR6 +address_a[6] => ram_block3a21.PORTAADDR6 +address_a[6] => ram_block3a22.PORTAADDR6 +address_a[6] => ram_block3a23.PORTAADDR6 +address_a[6] => ram_block3a24.PORTAADDR6 +address_a[6] => ram_block3a25.PORTAADDR6 +address_a[6] => ram_block3a26.PORTAADDR6 +address_a[6] => ram_block3a27.PORTAADDR6 +address_a[6] => ram_block3a28.PORTAADDR6 +address_a[6] => ram_block3a29.PORTAADDR6 +address_a[6] => ram_block3a30.PORTAADDR6 +address_a[6] => ram_block3a31.PORTAADDR6 +address_a[6] => ram_block3a32.PORTAADDR6 +address_a[6] => ram_block3a33.PORTAADDR6 +address_a[6] => ram_block3a34.PORTAADDR6 +address_a[6] => ram_block3a35.PORTAADDR6 +address_a[6] => ram_block3a36.PORTAADDR6 +address_a[6] => ram_block3a37.PORTAADDR6 +address_a[6] => ram_block3a38.PORTAADDR6 +address_a[6] => ram_block3a39.PORTAADDR6 +address_a[6] => ram_block3a40.PORTAADDR6 +address_a[6] => ram_block3a41.PORTAADDR6 +address_a[6] => ram_block3a42.PORTAADDR6 +address_a[6] => ram_block3a43.PORTAADDR6 +address_a[6] => ram_block3a44.PORTAADDR6 +address_a[6] => ram_block3a45.PORTAADDR6 +address_a[6] => ram_block3a46.PORTAADDR6 +address_a[6] => ram_block3a47.PORTAADDR6 +address_a[6] => ram_block3a48.PORTAADDR6 +address_a[6] => ram_block3a49.PORTAADDR6 +address_a[6] => ram_block3a50.PORTAADDR6 +address_a[6] => ram_block3a51.PORTAADDR6 +address_a[6] => ram_block3a52.PORTAADDR6 +address_a[6] => ram_block3a53.PORTAADDR6 +address_a[6] => ram_block3a54.PORTAADDR6 +address_a[6] => ram_block3a55.PORTAADDR6 +address_a[6] => ram_block3a56.PORTAADDR6 +address_a[6] => ram_block3a57.PORTAADDR6 +address_a[6] => ram_block3a58.PORTAADDR6 +address_a[6] => ram_block3a59.PORTAADDR6 +address_a[6] => ram_block3a60.PORTAADDR6 +address_a[6] => ram_block3a61.PORTAADDR6 +address_a[6] => ram_block3a62.PORTAADDR6 +address_a[6] => ram_block3a63.PORTAADDR6 +address_a[6] => ram_block3a64.PORTAADDR6 +address_a[6] => ram_block3a65.PORTAADDR6 +address_a[6] => ram_block3a66.PORTAADDR6 +address_a[6] => ram_block3a67.PORTAADDR6 +address_a[6] => ram_block3a68.PORTAADDR6 +address_a[6] => ram_block3a69.PORTAADDR6 +address_a[6] => ram_block3a70.PORTAADDR6 +address_a[6] => ram_block3a71.PORTAADDR6 +address_a[6] => ram_block3a72.PORTAADDR6 +address_a[6] => ram_block3a73.PORTAADDR6 +address_a[6] => ram_block3a74.PORTAADDR6 +address_a[6] => ram_block3a75.PORTAADDR6 +address_a[6] => ram_block3a76.PORTAADDR6 +address_a[6] => ram_block3a77.PORTAADDR6 +address_a[6] => ram_block3a78.PORTAADDR6 +address_a[6] => ram_block3a79.PORTAADDR6 +address_a[6] => ram_block3a80.PORTAADDR6 +address_a[6] => ram_block3a81.PORTAADDR6 +address_a[6] => ram_block3a82.PORTAADDR6 +address_a[6] => ram_block3a83.PORTAADDR6 +address_a[6] => ram_block3a84.PORTAADDR6 +address_a[6] => ram_block3a85.PORTAADDR6 +address_a[6] => ram_block3a86.PORTAADDR6 +address_a[6] => ram_block3a87.PORTAADDR6 +address_a[6] => ram_block3a88.PORTAADDR6 +address_a[6] => ram_block3a89.PORTAADDR6 +address_a[7] => ram_block3a0.PORTAADDR7 +address_a[7] => ram_block3a1.PORTAADDR7 +address_a[7] => ram_block3a2.PORTAADDR7 +address_a[7] => ram_block3a3.PORTAADDR7 +address_a[7] => ram_block3a4.PORTAADDR7 +address_a[7] => ram_block3a5.PORTAADDR7 +address_a[7] => ram_block3a6.PORTAADDR7 +address_a[7] => ram_block3a7.PORTAADDR7 +address_a[7] => ram_block3a8.PORTAADDR7 +address_a[7] => ram_block3a9.PORTAADDR7 +address_a[7] => ram_block3a10.PORTAADDR7 +address_a[7] => ram_block3a11.PORTAADDR7 +address_a[7] => ram_block3a12.PORTAADDR7 +address_a[7] => ram_block3a13.PORTAADDR7 +address_a[7] => ram_block3a14.PORTAADDR7 +address_a[7] => ram_block3a15.PORTAADDR7 +address_a[7] => ram_block3a16.PORTAADDR7 +address_a[7] => ram_block3a17.PORTAADDR7 +address_a[7] => ram_block3a18.PORTAADDR7 +address_a[7] => ram_block3a19.PORTAADDR7 +address_a[7] => ram_block3a20.PORTAADDR7 +address_a[7] => ram_block3a21.PORTAADDR7 +address_a[7] => ram_block3a22.PORTAADDR7 +address_a[7] => ram_block3a23.PORTAADDR7 +address_a[7] => ram_block3a24.PORTAADDR7 +address_a[7] => ram_block3a25.PORTAADDR7 +address_a[7] => ram_block3a26.PORTAADDR7 +address_a[7] => ram_block3a27.PORTAADDR7 +address_a[7] => ram_block3a28.PORTAADDR7 +address_a[7] => ram_block3a29.PORTAADDR7 +address_a[7] => ram_block3a30.PORTAADDR7 +address_a[7] => ram_block3a31.PORTAADDR7 +address_a[7] => ram_block3a32.PORTAADDR7 +address_a[7] => ram_block3a33.PORTAADDR7 +address_a[7] => ram_block3a34.PORTAADDR7 +address_a[7] => ram_block3a35.PORTAADDR7 +address_a[7] => ram_block3a36.PORTAADDR7 +address_a[7] => ram_block3a37.PORTAADDR7 +address_a[7] => ram_block3a38.PORTAADDR7 +address_a[7] => ram_block3a39.PORTAADDR7 +address_a[7] => ram_block3a40.PORTAADDR7 +address_a[7] => ram_block3a41.PORTAADDR7 +address_a[7] => ram_block3a42.PORTAADDR7 +address_a[7] => ram_block3a43.PORTAADDR7 +address_a[7] => ram_block3a44.PORTAADDR7 +address_a[7] => ram_block3a45.PORTAADDR7 +address_a[7] => ram_block3a46.PORTAADDR7 +address_a[7] => ram_block3a47.PORTAADDR7 +address_a[7] => ram_block3a48.PORTAADDR7 +address_a[7] => ram_block3a49.PORTAADDR7 +address_a[7] => ram_block3a50.PORTAADDR7 +address_a[7] => ram_block3a51.PORTAADDR7 +address_a[7] => ram_block3a52.PORTAADDR7 +address_a[7] => ram_block3a53.PORTAADDR7 +address_a[7] => ram_block3a54.PORTAADDR7 +address_a[7] => ram_block3a55.PORTAADDR7 +address_a[7] => ram_block3a56.PORTAADDR7 +address_a[7] => ram_block3a57.PORTAADDR7 +address_a[7] => ram_block3a58.PORTAADDR7 +address_a[7] => ram_block3a59.PORTAADDR7 +address_a[7] => ram_block3a60.PORTAADDR7 +address_a[7] => ram_block3a61.PORTAADDR7 +address_a[7] => ram_block3a62.PORTAADDR7 +address_a[7] => ram_block3a63.PORTAADDR7 +address_a[7] => ram_block3a64.PORTAADDR7 +address_a[7] => ram_block3a65.PORTAADDR7 +address_a[7] => ram_block3a66.PORTAADDR7 +address_a[7] => ram_block3a67.PORTAADDR7 +address_a[7] => ram_block3a68.PORTAADDR7 +address_a[7] => ram_block3a69.PORTAADDR7 +address_a[7] => ram_block3a70.PORTAADDR7 +address_a[7] => ram_block3a71.PORTAADDR7 +address_a[7] => ram_block3a72.PORTAADDR7 +address_a[7] => ram_block3a73.PORTAADDR7 +address_a[7] => ram_block3a74.PORTAADDR7 +address_a[7] => ram_block3a75.PORTAADDR7 +address_a[7] => ram_block3a76.PORTAADDR7 +address_a[7] => ram_block3a77.PORTAADDR7 +address_a[7] => ram_block3a78.PORTAADDR7 +address_a[7] => ram_block3a79.PORTAADDR7 +address_a[7] => ram_block3a80.PORTAADDR7 +address_a[7] => ram_block3a81.PORTAADDR7 +address_a[7] => ram_block3a82.PORTAADDR7 +address_a[7] => ram_block3a83.PORTAADDR7 +address_a[7] => ram_block3a84.PORTAADDR7 +address_a[7] => ram_block3a85.PORTAADDR7 +address_a[7] => ram_block3a86.PORTAADDR7 +address_a[7] => ram_block3a87.PORTAADDR7 +address_a[7] => ram_block3a88.PORTAADDR7 +address_a[7] => ram_block3a89.PORTAADDR7 +address_a[8] => ram_block3a0.PORTAADDR8 +address_a[8] => ram_block3a1.PORTAADDR8 +address_a[8] => ram_block3a2.PORTAADDR8 +address_a[8] => ram_block3a3.PORTAADDR8 +address_a[8] => ram_block3a4.PORTAADDR8 +address_a[8] => ram_block3a5.PORTAADDR8 +address_a[8] => ram_block3a6.PORTAADDR8 +address_a[8] => ram_block3a7.PORTAADDR8 +address_a[8] => ram_block3a8.PORTAADDR8 +address_a[8] => ram_block3a9.PORTAADDR8 +address_a[8] => ram_block3a10.PORTAADDR8 +address_a[8] => ram_block3a11.PORTAADDR8 +address_a[8] => ram_block3a12.PORTAADDR8 +address_a[8] => ram_block3a13.PORTAADDR8 +address_a[8] => ram_block3a14.PORTAADDR8 +address_a[8] => ram_block3a15.PORTAADDR8 +address_a[8] => ram_block3a16.PORTAADDR8 +address_a[8] => ram_block3a17.PORTAADDR8 +address_a[8] => ram_block3a18.PORTAADDR8 +address_a[8] => ram_block3a19.PORTAADDR8 +address_a[8] => ram_block3a20.PORTAADDR8 +address_a[8] => ram_block3a21.PORTAADDR8 +address_a[8] => ram_block3a22.PORTAADDR8 +address_a[8] => ram_block3a23.PORTAADDR8 +address_a[8] => ram_block3a24.PORTAADDR8 +address_a[8] => ram_block3a25.PORTAADDR8 +address_a[8] => ram_block3a26.PORTAADDR8 +address_a[8] => ram_block3a27.PORTAADDR8 +address_a[8] => ram_block3a28.PORTAADDR8 +address_a[8] => ram_block3a29.PORTAADDR8 +address_a[8] => ram_block3a30.PORTAADDR8 +address_a[8] => ram_block3a31.PORTAADDR8 +address_a[8] => ram_block3a32.PORTAADDR8 +address_a[8] => ram_block3a33.PORTAADDR8 +address_a[8] => ram_block3a34.PORTAADDR8 +address_a[8] => ram_block3a35.PORTAADDR8 +address_a[8] => ram_block3a36.PORTAADDR8 +address_a[8] => ram_block3a37.PORTAADDR8 +address_a[8] => ram_block3a38.PORTAADDR8 +address_a[8] => ram_block3a39.PORTAADDR8 +address_a[8] => ram_block3a40.PORTAADDR8 +address_a[8] => ram_block3a41.PORTAADDR8 +address_a[8] => ram_block3a42.PORTAADDR8 +address_a[8] => ram_block3a43.PORTAADDR8 +address_a[8] => ram_block3a44.PORTAADDR8 +address_a[8] => ram_block3a45.PORTAADDR8 +address_a[8] => ram_block3a46.PORTAADDR8 +address_a[8] => ram_block3a47.PORTAADDR8 +address_a[8] => ram_block3a48.PORTAADDR8 +address_a[8] => ram_block3a49.PORTAADDR8 +address_a[8] => ram_block3a50.PORTAADDR8 +address_a[8] => ram_block3a51.PORTAADDR8 +address_a[8] => ram_block3a52.PORTAADDR8 +address_a[8] => ram_block3a53.PORTAADDR8 +address_a[8] => ram_block3a54.PORTAADDR8 +address_a[8] => ram_block3a55.PORTAADDR8 +address_a[8] => ram_block3a56.PORTAADDR8 +address_a[8] => ram_block3a57.PORTAADDR8 +address_a[8] => ram_block3a58.PORTAADDR8 +address_a[8] => ram_block3a59.PORTAADDR8 +address_a[8] => ram_block3a60.PORTAADDR8 +address_a[8] => ram_block3a61.PORTAADDR8 +address_a[8] => ram_block3a62.PORTAADDR8 +address_a[8] => ram_block3a63.PORTAADDR8 +address_a[8] => ram_block3a64.PORTAADDR8 +address_a[8] => ram_block3a65.PORTAADDR8 +address_a[8] => ram_block3a66.PORTAADDR8 +address_a[8] => ram_block3a67.PORTAADDR8 +address_a[8] => ram_block3a68.PORTAADDR8 +address_a[8] => ram_block3a69.PORTAADDR8 +address_a[8] => ram_block3a70.PORTAADDR8 +address_a[8] => ram_block3a71.PORTAADDR8 +address_a[8] => ram_block3a72.PORTAADDR8 +address_a[8] => ram_block3a73.PORTAADDR8 +address_a[8] => ram_block3a74.PORTAADDR8 +address_a[8] => ram_block3a75.PORTAADDR8 +address_a[8] => ram_block3a76.PORTAADDR8 +address_a[8] => ram_block3a77.PORTAADDR8 +address_a[8] => ram_block3a78.PORTAADDR8 +address_a[8] => ram_block3a79.PORTAADDR8 +address_a[8] => ram_block3a80.PORTAADDR8 +address_a[8] => ram_block3a81.PORTAADDR8 +address_a[8] => ram_block3a82.PORTAADDR8 +address_a[8] => ram_block3a83.PORTAADDR8 +address_a[8] => ram_block3a84.PORTAADDR8 +address_a[8] => ram_block3a85.PORTAADDR8 +address_a[8] => ram_block3a86.PORTAADDR8 +address_a[8] => ram_block3a87.PORTAADDR8 +address_a[8] => ram_block3a88.PORTAADDR8 +address_a[8] => ram_block3a89.PORTAADDR8 +address_a[9] => ram_block3a0.PORTAADDR9 +address_a[9] => ram_block3a1.PORTAADDR9 +address_a[9] => ram_block3a2.PORTAADDR9 +address_a[9] => ram_block3a3.PORTAADDR9 +address_a[9] => ram_block3a4.PORTAADDR9 +address_a[9] => ram_block3a5.PORTAADDR9 +address_a[9] => ram_block3a6.PORTAADDR9 +address_a[9] => ram_block3a7.PORTAADDR9 +address_a[9] => ram_block3a8.PORTAADDR9 +address_a[9] => ram_block3a9.PORTAADDR9 +address_a[9] => ram_block3a10.PORTAADDR9 +address_a[9] => ram_block3a11.PORTAADDR9 +address_a[9] => ram_block3a12.PORTAADDR9 +address_a[9] => ram_block3a13.PORTAADDR9 +address_a[9] => ram_block3a14.PORTAADDR9 +address_a[9] => ram_block3a15.PORTAADDR9 +address_a[9] => ram_block3a16.PORTAADDR9 +address_a[9] => ram_block3a17.PORTAADDR9 +address_a[9] => ram_block3a18.PORTAADDR9 +address_a[9] => ram_block3a19.PORTAADDR9 +address_a[9] => ram_block3a20.PORTAADDR9 +address_a[9] => ram_block3a21.PORTAADDR9 +address_a[9] => ram_block3a22.PORTAADDR9 +address_a[9] => ram_block3a23.PORTAADDR9 +address_a[9] => ram_block3a24.PORTAADDR9 +address_a[9] => ram_block3a25.PORTAADDR9 +address_a[9] => ram_block3a26.PORTAADDR9 +address_a[9] => ram_block3a27.PORTAADDR9 +address_a[9] => ram_block3a28.PORTAADDR9 +address_a[9] => ram_block3a29.PORTAADDR9 +address_a[9] => ram_block3a30.PORTAADDR9 +address_a[9] => ram_block3a31.PORTAADDR9 +address_a[9] => ram_block3a32.PORTAADDR9 +address_a[9] => ram_block3a33.PORTAADDR9 +address_a[9] => ram_block3a34.PORTAADDR9 +address_a[9] => ram_block3a35.PORTAADDR9 +address_a[9] => ram_block3a36.PORTAADDR9 +address_a[9] => ram_block3a37.PORTAADDR9 +address_a[9] => ram_block3a38.PORTAADDR9 +address_a[9] => ram_block3a39.PORTAADDR9 +address_a[9] => ram_block3a40.PORTAADDR9 +address_a[9] => ram_block3a41.PORTAADDR9 +address_a[9] => ram_block3a42.PORTAADDR9 +address_a[9] => ram_block3a43.PORTAADDR9 +address_a[9] => ram_block3a44.PORTAADDR9 +address_a[9] => ram_block3a45.PORTAADDR9 +address_a[9] => ram_block3a46.PORTAADDR9 +address_a[9] => ram_block3a47.PORTAADDR9 +address_a[9] => ram_block3a48.PORTAADDR9 +address_a[9] => ram_block3a49.PORTAADDR9 +address_a[9] => ram_block3a50.PORTAADDR9 +address_a[9] => ram_block3a51.PORTAADDR9 +address_a[9] => ram_block3a52.PORTAADDR9 +address_a[9] => ram_block3a53.PORTAADDR9 +address_a[9] => ram_block3a54.PORTAADDR9 +address_a[9] => ram_block3a55.PORTAADDR9 +address_a[9] => ram_block3a56.PORTAADDR9 +address_a[9] => ram_block3a57.PORTAADDR9 +address_a[9] => ram_block3a58.PORTAADDR9 +address_a[9] => ram_block3a59.PORTAADDR9 +address_a[9] => ram_block3a60.PORTAADDR9 +address_a[9] => ram_block3a61.PORTAADDR9 +address_a[9] => ram_block3a62.PORTAADDR9 +address_a[9] => ram_block3a63.PORTAADDR9 +address_a[9] => ram_block3a64.PORTAADDR9 +address_a[9] => ram_block3a65.PORTAADDR9 +address_a[9] => ram_block3a66.PORTAADDR9 +address_a[9] => ram_block3a67.PORTAADDR9 +address_a[9] => ram_block3a68.PORTAADDR9 +address_a[9] => ram_block3a69.PORTAADDR9 +address_a[9] => ram_block3a70.PORTAADDR9 +address_a[9] => ram_block3a71.PORTAADDR9 +address_a[9] => ram_block3a72.PORTAADDR9 +address_a[9] => ram_block3a73.PORTAADDR9 +address_a[9] => ram_block3a74.PORTAADDR9 +address_a[9] => ram_block3a75.PORTAADDR9 +address_a[9] => ram_block3a76.PORTAADDR9 +address_a[9] => ram_block3a77.PORTAADDR9 +address_a[9] => ram_block3a78.PORTAADDR9 +address_a[9] => ram_block3a79.PORTAADDR9 +address_a[9] => ram_block3a80.PORTAADDR9 +address_a[9] => ram_block3a81.PORTAADDR9 +address_a[9] => ram_block3a82.PORTAADDR9 +address_a[9] => ram_block3a83.PORTAADDR9 +address_a[9] => ram_block3a84.PORTAADDR9 +address_a[9] => ram_block3a85.PORTAADDR9 +address_a[9] => ram_block3a86.PORTAADDR9 +address_a[9] => ram_block3a87.PORTAADDR9 +address_a[9] => ram_block3a88.PORTAADDR9 +address_a[9] => ram_block3a89.PORTAADDR9 +address_b[0] => ram_block3a0.PORTBADDR +address_b[0] => ram_block3a1.PORTBADDR +address_b[0] => ram_block3a2.PORTBADDR +address_b[0] => ram_block3a3.PORTBADDR +address_b[0] => ram_block3a4.PORTBADDR +address_b[0] => ram_block3a5.PORTBADDR +address_b[0] => ram_block3a6.PORTBADDR +address_b[0] => ram_block3a7.PORTBADDR +address_b[0] => ram_block3a8.PORTBADDR +address_b[0] => ram_block3a9.PORTBADDR +address_b[0] => ram_block3a10.PORTBADDR +address_b[0] => ram_block3a11.PORTBADDR +address_b[0] => ram_block3a12.PORTBADDR +address_b[0] => ram_block3a13.PORTBADDR +address_b[0] => ram_block3a14.PORTBADDR +address_b[0] => ram_block3a15.PORTBADDR +address_b[0] => ram_block3a16.PORTBADDR +address_b[0] => ram_block3a17.PORTBADDR +address_b[0] => ram_block3a18.PORTBADDR +address_b[0] => ram_block3a19.PORTBADDR +address_b[0] => ram_block3a20.PORTBADDR +address_b[0] => ram_block3a21.PORTBADDR +address_b[0] => ram_block3a22.PORTBADDR +address_b[0] => ram_block3a23.PORTBADDR +address_b[0] => ram_block3a24.PORTBADDR +address_b[0] => ram_block3a25.PORTBADDR +address_b[0] => ram_block3a26.PORTBADDR +address_b[0] => ram_block3a27.PORTBADDR +address_b[0] => ram_block3a28.PORTBADDR +address_b[0] => ram_block3a29.PORTBADDR +address_b[0] => ram_block3a30.PORTBADDR +address_b[0] => ram_block3a31.PORTBADDR +address_b[0] => ram_block3a32.PORTBADDR +address_b[0] => ram_block3a33.PORTBADDR +address_b[0] => ram_block3a34.PORTBADDR +address_b[0] => ram_block3a35.PORTBADDR +address_b[0] => ram_block3a36.PORTBADDR +address_b[0] => ram_block3a37.PORTBADDR +address_b[0] => ram_block3a38.PORTBADDR +address_b[0] => ram_block3a39.PORTBADDR +address_b[0] => ram_block3a40.PORTBADDR +address_b[0] => ram_block3a41.PORTBADDR +address_b[0] => ram_block3a42.PORTBADDR +address_b[0] => ram_block3a43.PORTBADDR +address_b[0] => ram_block3a44.PORTBADDR +address_b[0] => ram_block3a45.PORTBADDR +address_b[0] => ram_block3a46.PORTBADDR +address_b[0] => ram_block3a47.PORTBADDR +address_b[0] => ram_block3a48.PORTBADDR +address_b[0] => ram_block3a49.PORTBADDR +address_b[0] => ram_block3a50.PORTBADDR +address_b[0] => ram_block3a51.PORTBADDR +address_b[0] => ram_block3a52.PORTBADDR +address_b[0] => ram_block3a53.PORTBADDR +address_b[0] => ram_block3a54.PORTBADDR +address_b[0] => ram_block3a55.PORTBADDR +address_b[0] => ram_block3a56.PORTBADDR +address_b[0] => ram_block3a57.PORTBADDR +address_b[0] => ram_block3a58.PORTBADDR +address_b[0] => ram_block3a59.PORTBADDR +address_b[0] => ram_block3a60.PORTBADDR +address_b[0] => ram_block3a61.PORTBADDR +address_b[0] => ram_block3a62.PORTBADDR +address_b[0] => ram_block3a63.PORTBADDR +address_b[0] => ram_block3a64.PORTBADDR +address_b[0] => ram_block3a65.PORTBADDR +address_b[0] => ram_block3a66.PORTBADDR +address_b[0] => ram_block3a67.PORTBADDR +address_b[0] => ram_block3a68.PORTBADDR +address_b[0] => ram_block3a69.PORTBADDR +address_b[0] => ram_block3a70.PORTBADDR +address_b[0] => ram_block3a71.PORTBADDR +address_b[0] => ram_block3a72.PORTBADDR +address_b[0] => ram_block3a73.PORTBADDR +address_b[0] => ram_block3a74.PORTBADDR +address_b[0] => ram_block3a75.PORTBADDR +address_b[0] => ram_block3a76.PORTBADDR +address_b[0] => ram_block3a77.PORTBADDR +address_b[0] => ram_block3a78.PORTBADDR +address_b[0] => ram_block3a79.PORTBADDR +address_b[0] => ram_block3a80.PORTBADDR +address_b[0] => ram_block3a81.PORTBADDR +address_b[0] => ram_block3a82.PORTBADDR +address_b[0] => ram_block3a83.PORTBADDR +address_b[0] => ram_block3a84.PORTBADDR +address_b[0] => ram_block3a85.PORTBADDR +address_b[0] => ram_block3a86.PORTBADDR +address_b[0] => ram_block3a87.PORTBADDR +address_b[0] => ram_block3a88.PORTBADDR +address_b[0] => ram_block3a89.PORTBADDR +address_b[1] => ram_block3a0.PORTBADDR1 +address_b[1] => ram_block3a1.PORTBADDR1 +address_b[1] => ram_block3a2.PORTBADDR1 +address_b[1] => ram_block3a3.PORTBADDR1 +address_b[1] => ram_block3a4.PORTBADDR1 +address_b[1] => ram_block3a5.PORTBADDR1 +address_b[1] => ram_block3a6.PORTBADDR1 +address_b[1] => ram_block3a7.PORTBADDR1 +address_b[1] => ram_block3a8.PORTBADDR1 +address_b[1] => ram_block3a9.PORTBADDR1 +address_b[1] => ram_block3a10.PORTBADDR1 +address_b[1] => ram_block3a11.PORTBADDR1 +address_b[1] => ram_block3a12.PORTBADDR1 +address_b[1] => ram_block3a13.PORTBADDR1 +address_b[1] => ram_block3a14.PORTBADDR1 +address_b[1] => ram_block3a15.PORTBADDR1 +address_b[1] => ram_block3a16.PORTBADDR1 +address_b[1] => ram_block3a17.PORTBADDR1 +address_b[1] => ram_block3a18.PORTBADDR1 +address_b[1] => ram_block3a19.PORTBADDR1 +address_b[1] => ram_block3a20.PORTBADDR1 +address_b[1] => ram_block3a21.PORTBADDR1 +address_b[1] => ram_block3a22.PORTBADDR1 +address_b[1] => ram_block3a23.PORTBADDR1 +address_b[1] => ram_block3a24.PORTBADDR1 +address_b[1] => ram_block3a25.PORTBADDR1 +address_b[1] => ram_block3a26.PORTBADDR1 +address_b[1] => ram_block3a27.PORTBADDR1 +address_b[1] => ram_block3a28.PORTBADDR1 +address_b[1] => ram_block3a29.PORTBADDR1 +address_b[1] => ram_block3a30.PORTBADDR1 +address_b[1] => ram_block3a31.PORTBADDR1 +address_b[1] => ram_block3a32.PORTBADDR1 +address_b[1] => ram_block3a33.PORTBADDR1 +address_b[1] => ram_block3a34.PORTBADDR1 +address_b[1] => ram_block3a35.PORTBADDR1 +address_b[1] => ram_block3a36.PORTBADDR1 +address_b[1] => ram_block3a37.PORTBADDR1 +address_b[1] => ram_block3a38.PORTBADDR1 +address_b[1] => ram_block3a39.PORTBADDR1 +address_b[1] => ram_block3a40.PORTBADDR1 +address_b[1] => ram_block3a41.PORTBADDR1 +address_b[1] => ram_block3a42.PORTBADDR1 +address_b[1] => ram_block3a43.PORTBADDR1 +address_b[1] => ram_block3a44.PORTBADDR1 +address_b[1] => ram_block3a45.PORTBADDR1 +address_b[1] => ram_block3a46.PORTBADDR1 +address_b[1] => ram_block3a47.PORTBADDR1 +address_b[1] => ram_block3a48.PORTBADDR1 +address_b[1] => ram_block3a49.PORTBADDR1 +address_b[1] => ram_block3a50.PORTBADDR1 +address_b[1] => ram_block3a51.PORTBADDR1 +address_b[1] => ram_block3a52.PORTBADDR1 +address_b[1] => ram_block3a53.PORTBADDR1 +address_b[1] => ram_block3a54.PORTBADDR1 +address_b[1] => ram_block3a55.PORTBADDR1 +address_b[1] => ram_block3a56.PORTBADDR1 +address_b[1] => ram_block3a57.PORTBADDR1 +address_b[1] => ram_block3a58.PORTBADDR1 +address_b[1] => ram_block3a59.PORTBADDR1 +address_b[1] => ram_block3a60.PORTBADDR1 +address_b[1] => ram_block3a61.PORTBADDR1 +address_b[1] => ram_block3a62.PORTBADDR1 +address_b[1] => ram_block3a63.PORTBADDR1 +address_b[1] => ram_block3a64.PORTBADDR1 +address_b[1] => ram_block3a65.PORTBADDR1 +address_b[1] => ram_block3a66.PORTBADDR1 +address_b[1] => ram_block3a67.PORTBADDR1 +address_b[1] => ram_block3a68.PORTBADDR1 +address_b[1] => ram_block3a69.PORTBADDR1 +address_b[1] => ram_block3a70.PORTBADDR1 +address_b[1] => ram_block3a71.PORTBADDR1 +address_b[1] => ram_block3a72.PORTBADDR1 +address_b[1] => ram_block3a73.PORTBADDR1 +address_b[1] => ram_block3a74.PORTBADDR1 +address_b[1] => ram_block3a75.PORTBADDR1 +address_b[1] => ram_block3a76.PORTBADDR1 +address_b[1] => ram_block3a77.PORTBADDR1 +address_b[1] => ram_block3a78.PORTBADDR1 +address_b[1] => ram_block3a79.PORTBADDR1 +address_b[1] => ram_block3a80.PORTBADDR1 +address_b[1] => ram_block3a81.PORTBADDR1 +address_b[1] => ram_block3a82.PORTBADDR1 +address_b[1] => ram_block3a83.PORTBADDR1 +address_b[1] => ram_block3a84.PORTBADDR1 +address_b[1] => ram_block3a85.PORTBADDR1 +address_b[1] => ram_block3a86.PORTBADDR1 +address_b[1] => ram_block3a87.PORTBADDR1 +address_b[1] => ram_block3a88.PORTBADDR1 +address_b[1] => ram_block3a89.PORTBADDR1 +address_b[2] => ram_block3a0.PORTBADDR2 +address_b[2] => ram_block3a1.PORTBADDR2 +address_b[2] => ram_block3a2.PORTBADDR2 +address_b[2] => ram_block3a3.PORTBADDR2 +address_b[2] => ram_block3a4.PORTBADDR2 +address_b[2] => ram_block3a5.PORTBADDR2 +address_b[2] => ram_block3a6.PORTBADDR2 +address_b[2] => ram_block3a7.PORTBADDR2 +address_b[2] => ram_block3a8.PORTBADDR2 +address_b[2] => ram_block3a9.PORTBADDR2 +address_b[2] => ram_block3a10.PORTBADDR2 +address_b[2] => ram_block3a11.PORTBADDR2 +address_b[2] => ram_block3a12.PORTBADDR2 +address_b[2] => ram_block3a13.PORTBADDR2 +address_b[2] => ram_block3a14.PORTBADDR2 +address_b[2] => ram_block3a15.PORTBADDR2 +address_b[2] => ram_block3a16.PORTBADDR2 +address_b[2] => ram_block3a17.PORTBADDR2 +address_b[2] => ram_block3a18.PORTBADDR2 +address_b[2] => ram_block3a19.PORTBADDR2 +address_b[2] => ram_block3a20.PORTBADDR2 +address_b[2] => ram_block3a21.PORTBADDR2 +address_b[2] => ram_block3a22.PORTBADDR2 +address_b[2] => ram_block3a23.PORTBADDR2 +address_b[2] => ram_block3a24.PORTBADDR2 +address_b[2] => ram_block3a25.PORTBADDR2 +address_b[2] => ram_block3a26.PORTBADDR2 +address_b[2] => ram_block3a27.PORTBADDR2 +address_b[2] => ram_block3a28.PORTBADDR2 +address_b[2] => ram_block3a29.PORTBADDR2 +address_b[2] => ram_block3a30.PORTBADDR2 +address_b[2] => ram_block3a31.PORTBADDR2 +address_b[2] => ram_block3a32.PORTBADDR2 +address_b[2] => ram_block3a33.PORTBADDR2 +address_b[2] => ram_block3a34.PORTBADDR2 +address_b[2] => ram_block3a35.PORTBADDR2 +address_b[2] => ram_block3a36.PORTBADDR2 +address_b[2] => ram_block3a37.PORTBADDR2 +address_b[2] => ram_block3a38.PORTBADDR2 +address_b[2] => ram_block3a39.PORTBADDR2 +address_b[2] => ram_block3a40.PORTBADDR2 +address_b[2] => ram_block3a41.PORTBADDR2 +address_b[2] => ram_block3a42.PORTBADDR2 +address_b[2] => ram_block3a43.PORTBADDR2 +address_b[2] => ram_block3a44.PORTBADDR2 +address_b[2] => ram_block3a45.PORTBADDR2 +address_b[2] => ram_block3a46.PORTBADDR2 +address_b[2] => ram_block3a47.PORTBADDR2 +address_b[2] => ram_block3a48.PORTBADDR2 +address_b[2] => ram_block3a49.PORTBADDR2 +address_b[2] => ram_block3a50.PORTBADDR2 +address_b[2] => ram_block3a51.PORTBADDR2 +address_b[2] => ram_block3a52.PORTBADDR2 +address_b[2] => ram_block3a53.PORTBADDR2 +address_b[2] => ram_block3a54.PORTBADDR2 +address_b[2] => ram_block3a55.PORTBADDR2 +address_b[2] => ram_block3a56.PORTBADDR2 +address_b[2] => ram_block3a57.PORTBADDR2 +address_b[2] => ram_block3a58.PORTBADDR2 +address_b[2] => ram_block3a59.PORTBADDR2 +address_b[2] => ram_block3a60.PORTBADDR2 +address_b[2] => ram_block3a61.PORTBADDR2 +address_b[2] => ram_block3a62.PORTBADDR2 +address_b[2] => ram_block3a63.PORTBADDR2 +address_b[2] => ram_block3a64.PORTBADDR2 +address_b[2] => ram_block3a65.PORTBADDR2 +address_b[2] => ram_block3a66.PORTBADDR2 +address_b[2] => ram_block3a67.PORTBADDR2 +address_b[2] => ram_block3a68.PORTBADDR2 +address_b[2] => ram_block3a69.PORTBADDR2 +address_b[2] => ram_block3a70.PORTBADDR2 +address_b[2] => ram_block3a71.PORTBADDR2 +address_b[2] => ram_block3a72.PORTBADDR2 +address_b[2] => ram_block3a73.PORTBADDR2 +address_b[2] => ram_block3a74.PORTBADDR2 +address_b[2] => ram_block3a75.PORTBADDR2 +address_b[2] => ram_block3a76.PORTBADDR2 +address_b[2] => ram_block3a77.PORTBADDR2 +address_b[2] => ram_block3a78.PORTBADDR2 +address_b[2] => ram_block3a79.PORTBADDR2 +address_b[2] => ram_block3a80.PORTBADDR2 +address_b[2] => ram_block3a81.PORTBADDR2 +address_b[2] => ram_block3a82.PORTBADDR2 +address_b[2] => ram_block3a83.PORTBADDR2 +address_b[2] => ram_block3a84.PORTBADDR2 +address_b[2] => ram_block3a85.PORTBADDR2 +address_b[2] => ram_block3a86.PORTBADDR2 +address_b[2] => ram_block3a87.PORTBADDR2 +address_b[2] => ram_block3a88.PORTBADDR2 +address_b[2] => ram_block3a89.PORTBADDR2 +address_b[3] => ram_block3a0.PORTBADDR3 +address_b[3] => ram_block3a1.PORTBADDR3 +address_b[3] => ram_block3a2.PORTBADDR3 +address_b[3] => ram_block3a3.PORTBADDR3 +address_b[3] => ram_block3a4.PORTBADDR3 +address_b[3] => ram_block3a5.PORTBADDR3 +address_b[3] => ram_block3a6.PORTBADDR3 +address_b[3] => ram_block3a7.PORTBADDR3 +address_b[3] => ram_block3a8.PORTBADDR3 +address_b[3] => ram_block3a9.PORTBADDR3 +address_b[3] => ram_block3a10.PORTBADDR3 +address_b[3] => ram_block3a11.PORTBADDR3 +address_b[3] => ram_block3a12.PORTBADDR3 +address_b[3] => ram_block3a13.PORTBADDR3 +address_b[3] => ram_block3a14.PORTBADDR3 +address_b[3] => ram_block3a15.PORTBADDR3 +address_b[3] => ram_block3a16.PORTBADDR3 +address_b[3] => ram_block3a17.PORTBADDR3 +address_b[3] => ram_block3a18.PORTBADDR3 +address_b[3] => ram_block3a19.PORTBADDR3 +address_b[3] => ram_block3a20.PORTBADDR3 +address_b[3] => ram_block3a21.PORTBADDR3 +address_b[3] => ram_block3a22.PORTBADDR3 +address_b[3] => ram_block3a23.PORTBADDR3 +address_b[3] => ram_block3a24.PORTBADDR3 +address_b[3] => ram_block3a25.PORTBADDR3 +address_b[3] => ram_block3a26.PORTBADDR3 +address_b[3] => ram_block3a27.PORTBADDR3 +address_b[3] => ram_block3a28.PORTBADDR3 +address_b[3] => ram_block3a29.PORTBADDR3 +address_b[3] => ram_block3a30.PORTBADDR3 +address_b[3] => ram_block3a31.PORTBADDR3 +address_b[3] => ram_block3a32.PORTBADDR3 +address_b[3] => ram_block3a33.PORTBADDR3 +address_b[3] => ram_block3a34.PORTBADDR3 +address_b[3] => ram_block3a35.PORTBADDR3 +address_b[3] => ram_block3a36.PORTBADDR3 +address_b[3] => ram_block3a37.PORTBADDR3 +address_b[3] => ram_block3a38.PORTBADDR3 +address_b[3] => ram_block3a39.PORTBADDR3 +address_b[3] => ram_block3a40.PORTBADDR3 +address_b[3] => ram_block3a41.PORTBADDR3 +address_b[3] => ram_block3a42.PORTBADDR3 +address_b[3] => ram_block3a43.PORTBADDR3 +address_b[3] => ram_block3a44.PORTBADDR3 +address_b[3] => ram_block3a45.PORTBADDR3 +address_b[3] => ram_block3a46.PORTBADDR3 +address_b[3] => ram_block3a47.PORTBADDR3 +address_b[3] => ram_block3a48.PORTBADDR3 +address_b[3] => ram_block3a49.PORTBADDR3 +address_b[3] => ram_block3a50.PORTBADDR3 +address_b[3] => ram_block3a51.PORTBADDR3 +address_b[3] => ram_block3a52.PORTBADDR3 +address_b[3] => ram_block3a53.PORTBADDR3 +address_b[3] => ram_block3a54.PORTBADDR3 +address_b[3] => ram_block3a55.PORTBADDR3 +address_b[3] => ram_block3a56.PORTBADDR3 +address_b[3] => ram_block3a57.PORTBADDR3 +address_b[3] => ram_block3a58.PORTBADDR3 +address_b[3] => ram_block3a59.PORTBADDR3 +address_b[3] => ram_block3a60.PORTBADDR3 +address_b[3] => ram_block3a61.PORTBADDR3 +address_b[3] => ram_block3a62.PORTBADDR3 +address_b[3] => ram_block3a63.PORTBADDR3 +address_b[3] => ram_block3a64.PORTBADDR3 +address_b[3] => ram_block3a65.PORTBADDR3 +address_b[3] => ram_block3a66.PORTBADDR3 +address_b[3] => ram_block3a67.PORTBADDR3 +address_b[3] => ram_block3a68.PORTBADDR3 +address_b[3] => ram_block3a69.PORTBADDR3 +address_b[3] => ram_block3a70.PORTBADDR3 +address_b[3] => ram_block3a71.PORTBADDR3 +address_b[3] => ram_block3a72.PORTBADDR3 +address_b[3] => ram_block3a73.PORTBADDR3 +address_b[3] => ram_block3a74.PORTBADDR3 +address_b[3] => ram_block3a75.PORTBADDR3 +address_b[3] => ram_block3a76.PORTBADDR3 +address_b[3] => ram_block3a77.PORTBADDR3 +address_b[3] => ram_block3a78.PORTBADDR3 +address_b[3] => ram_block3a79.PORTBADDR3 +address_b[3] => ram_block3a80.PORTBADDR3 +address_b[3] => ram_block3a81.PORTBADDR3 +address_b[3] => ram_block3a82.PORTBADDR3 +address_b[3] => ram_block3a83.PORTBADDR3 +address_b[3] => ram_block3a84.PORTBADDR3 +address_b[3] => ram_block3a85.PORTBADDR3 +address_b[3] => ram_block3a86.PORTBADDR3 +address_b[3] => ram_block3a87.PORTBADDR3 +address_b[3] => ram_block3a88.PORTBADDR3 +address_b[3] => ram_block3a89.PORTBADDR3 +address_b[4] => ram_block3a0.PORTBADDR4 +address_b[4] => ram_block3a1.PORTBADDR4 +address_b[4] => ram_block3a2.PORTBADDR4 +address_b[4] => ram_block3a3.PORTBADDR4 +address_b[4] => ram_block3a4.PORTBADDR4 +address_b[4] => ram_block3a5.PORTBADDR4 +address_b[4] => ram_block3a6.PORTBADDR4 +address_b[4] => ram_block3a7.PORTBADDR4 +address_b[4] => ram_block3a8.PORTBADDR4 +address_b[4] => ram_block3a9.PORTBADDR4 +address_b[4] => ram_block3a10.PORTBADDR4 +address_b[4] => ram_block3a11.PORTBADDR4 +address_b[4] => ram_block3a12.PORTBADDR4 +address_b[4] => ram_block3a13.PORTBADDR4 +address_b[4] => ram_block3a14.PORTBADDR4 +address_b[4] => ram_block3a15.PORTBADDR4 +address_b[4] => ram_block3a16.PORTBADDR4 +address_b[4] => ram_block3a17.PORTBADDR4 +address_b[4] => ram_block3a18.PORTBADDR4 +address_b[4] => ram_block3a19.PORTBADDR4 +address_b[4] => ram_block3a20.PORTBADDR4 +address_b[4] => ram_block3a21.PORTBADDR4 +address_b[4] => ram_block3a22.PORTBADDR4 +address_b[4] => ram_block3a23.PORTBADDR4 +address_b[4] => ram_block3a24.PORTBADDR4 +address_b[4] => ram_block3a25.PORTBADDR4 +address_b[4] => ram_block3a26.PORTBADDR4 +address_b[4] => ram_block3a27.PORTBADDR4 +address_b[4] => ram_block3a28.PORTBADDR4 +address_b[4] => ram_block3a29.PORTBADDR4 +address_b[4] => ram_block3a30.PORTBADDR4 +address_b[4] => ram_block3a31.PORTBADDR4 +address_b[4] => ram_block3a32.PORTBADDR4 +address_b[4] => ram_block3a33.PORTBADDR4 +address_b[4] => ram_block3a34.PORTBADDR4 +address_b[4] => ram_block3a35.PORTBADDR4 +address_b[4] => ram_block3a36.PORTBADDR4 +address_b[4] => ram_block3a37.PORTBADDR4 +address_b[4] => ram_block3a38.PORTBADDR4 +address_b[4] => ram_block3a39.PORTBADDR4 +address_b[4] => ram_block3a40.PORTBADDR4 +address_b[4] => ram_block3a41.PORTBADDR4 +address_b[4] => ram_block3a42.PORTBADDR4 +address_b[4] => ram_block3a43.PORTBADDR4 +address_b[4] => ram_block3a44.PORTBADDR4 +address_b[4] => ram_block3a45.PORTBADDR4 +address_b[4] => ram_block3a46.PORTBADDR4 +address_b[4] => ram_block3a47.PORTBADDR4 +address_b[4] => ram_block3a48.PORTBADDR4 +address_b[4] => ram_block3a49.PORTBADDR4 +address_b[4] => ram_block3a50.PORTBADDR4 +address_b[4] => ram_block3a51.PORTBADDR4 +address_b[4] => ram_block3a52.PORTBADDR4 +address_b[4] => ram_block3a53.PORTBADDR4 +address_b[4] => ram_block3a54.PORTBADDR4 +address_b[4] => ram_block3a55.PORTBADDR4 +address_b[4] => ram_block3a56.PORTBADDR4 +address_b[4] => ram_block3a57.PORTBADDR4 +address_b[4] => ram_block3a58.PORTBADDR4 +address_b[4] => ram_block3a59.PORTBADDR4 +address_b[4] => ram_block3a60.PORTBADDR4 +address_b[4] => ram_block3a61.PORTBADDR4 +address_b[4] => ram_block3a62.PORTBADDR4 +address_b[4] => ram_block3a63.PORTBADDR4 +address_b[4] => ram_block3a64.PORTBADDR4 +address_b[4] => ram_block3a65.PORTBADDR4 +address_b[4] => ram_block3a66.PORTBADDR4 +address_b[4] => ram_block3a67.PORTBADDR4 +address_b[4] => ram_block3a68.PORTBADDR4 +address_b[4] => ram_block3a69.PORTBADDR4 +address_b[4] => ram_block3a70.PORTBADDR4 +address_b[4] => ram_block3a71.PORTBADDR4 +address_b[4] => ram_block3a72.PORTBADDR4 +address_b[4] => ram_block3a73.PORTBADDR4 +address_b[4] => ram_block3a74.PORTBADDR4 +address_b[4] => ram_block3a75.PORTBADDR4 +address_b[4] => ram_block3a76.PORTBADDR4 +address_b[4] => ram_block3a77.PORTBADDR4 +address_b[4] => ram_block3a78.PORTBADDR4 +address_b[4] => ram_block3a79.PORTBADDR4 +address_b[4] => ram_block3a80.PORTBADDR4 +address_b[4] => ram_block3a81.PORTBADDR4 +address_b[4] => ram_block3a82.PORTBADDR4 +address_b[4] => ram_block3a83.PORTBADDR4 +address_b[4] => ram_block3a84.PORTBADDR4 +address_b[4] => ram_block3a85.PORTBADDR4 +address_b[4] => ram_block3a86.PORTBADDR4 +address_b[4] => ram_block3a87.PORTBADDR4 +address_b[4] => ram_block3a88.PORTBADDR4 +address_b[4] => ram_block3a89.PORTBADDR4 +address_b[5] => ram_block3a0.PORTBADDR5 +address_b[5] => ram_block3a1.PORTBADDR5 +address_b[5] => ram_block3a2.PORTBADDR5 +address_b[5] => ram_block3a3.PORTBADDR5 +address_b[5] => ram_block3a4.PORTBADDR5 +address_b[5] => ram_block3a5.PORTBADDR5 +address_b[5] => ram_block3a6.PORTBADDR5 +address_b[5] => ram_block3a7.PORTBADDR5 +address_b[5] => ram_block3a8.PORTBADDR5 +address_b[5] => ram_block3a9.PORTBADDR5 +address_b[5] => ram_block3a10.PORTBADDR5 +address_b[5] => ram_block3a11.PORTBADDR5 +address_b[5] => ram_block3a12.PORTBADDR5 +address_b[5] => ram_block3a13.PORTBADDR5 +address_b[5] => ram_block3a14.PORTBADDR5 +address_b[5] => ram_block3a15.PORTBADDR5 +address_b[5] => ram_block3a16.PORTBADDR5 +address_b[5] => ram_block3a17.PORTBADDR5 +address_b[5] => ram_block3a18.PORTBADDR5 +address_b[5] => ram_block3a19.PORTBADDR5 +address_b[5] => ram_block3a20.PORTBADDR5 +address_b[5] => ram_block3a21.PORTBADDR5 +address_b[5] => ram_block3a22.PORTBADDR5 +address_b[5] => ram_block3a23.PORTBADDR5 +address_b[5] => ram_block3a24.PORTBADDR5 +address_b[5] => ram_block3a25.PORTBADDR5 +address_b[5] => ram_block3a26.PORTBADDR5 +address_b[5] => ram_block3a27.PORTBADDR5 +address_b[5] => ram_block3a28.PORTBADDR5 +address_b[5] => ram_block3a29.PORTBADDR5 +address_b[5] => ram_block3a30.PORTBADDR5 +address_b[5] => ram_block3a31.PORTBADDR5 +address_b[5] => ram_block3a32.PORTBADDR5 +address_b[5] => ram_block3a33.PORTBADDR5 +address_b[5] => ram_block3a34.PORTBADDR5 +address_b[5] => ram_block3a35.PORTBADDR5 +address_b[5] => ram_block3a36.PORTBADDR5 +address_b[5] => ram_block3a37.PORTBADDR5 +address_b[5] => ram_block3a38.PORTBADDR5 +address_b[5] => ram_block3a39.PORTBADDR5 +address_b[5] => ram_block3a40.PORTBADDR5 +address_b[5] => ram_block3a41.PORTBADDR5 +address_b[5] => ram_block3a42.PORTBADDR5 +address_b[5] => ram_block3a43.PORTBADDR5 +address_b[5] => ram_block3a44.PORTBADDR5 +address_b[5] => ram_block3a45.PORTBADDR5 +address_b[5] => ram_block3a46.PORTBADDR5 +address_b[5] => ram_block3a47.PORTBADDR5 +address_b[5] => ram_block3a48.PORTBADDR5 +address_b[5] => ram_block3a49.PORTBADDR5 +address_b[5] => ram_block3a50.PORTBADDR5 +address_b[5] => ram_block3a51.PORTBADDR5 +address_b[5] => ram_block3a52.PORTBADDR5 +address_b[5] => ram_block3a53.PORTBADDR5 +address_b[5] => ram_block3a54.PORTBADDR5 +address_b[5] => ram_block3a55.PORTBADDR5 +address_b[5] => ram_block3a56.PORTBADDR5 +address_b[5] => ram_block3a57.PORTBADDR5 +address_b[5] => ram_block3a58.PORTBADDR5 +address_b[5] => ram_block3a59.PORTBADDR5 +address_b[5] => ram_block3a60.PORTBADDR5 +address_b[5] => ram_block3a61.PORTBADDR5 +address_b[5] => ram_block3a62.PORTBADDR5 +address_b[5] => ram_block3a63.PORTBADDR5 +address_b[5] => ram_block3a64.PORTBADDR5 +address_b[5] => ram_block3a65.PORTBADDR5 +address_b[5] => ram_block3a66.PORTBADDR5 +address_b[5] => ram_block3a67.PORTBADDR5 +address_b[5] => ram_block3a68.PORTBADDR5 +address_b[5] => ram_block3a69.PORTBADDR5 +address_b[5] => ram_block3a70.PORTBADDR5 +address_b[5] => ram_block3a71.PORTBADDR5 +address_b[5] => ram_block3a72.PORTBADDR5 +address_b[5] => ram_block3a73.PORTBADDR5 +address_b[5] => ram_block3a74.PORTBADDR5 +address_b[5] => ram_block3a75.PORTBADDR5 +address_b[5] => ram_block3a76.PORTBADDR5 +address_b[5] => ram_block3a77.PORTBADDR5 +address_b[5] => ram_block3a78.PORTBADDR5 +address_b[5] => ram_block3a79.PORTBADDR5 +address_b[5] => ram_block3a80.PORTBADDR5 +address_b[5] => ram_block3a81.PORTBADDR5 +address_b[5] => ram_block3a82.PORTBADDR5 +address_b[5] => ram_block3a83.PORTBADDR5 +address_b[5] => ram_block3a84.PORTBADDR5 +address_b[5] => ram_block3a85.PORTBADDR5 +address_b[5] => ram_block3a86.PORTBADDR5 +address_b[5] => ram_block3a87.PORTBADDR5 +address_b[5] => ram_block3a88.PORTBADDR5 +address_b[5] => ram_block3a89.PORTBADDR5 +address_b[6] => ram_block3a0.PORTBADDR6 +address_b[6] => ram_block3a1.PORTBADDR6 +address_b[6] => ram_block3a2.PORTBADDR6 +address_b[6] => ram_block3a3.PORTBADDR6 +address_b[6] => ram_block3a4.PORTBADDR6 +address_b[6] => ram_block3a5.PORTBADDR6 +address_b[6] => ram_block3a6.PORTBADDR6 +address_b[6] => ram_block3a7.PORTBADDR6 +address_b[6] => ram_block3a8.PORTBADDR6 +address_b[6] => ram_block3a9.PORTBADDR6 +address_b[6] => ram_block3a10.PORTBADDR6 +address_b[6] => ram_block3a11.PORTBADDR6 +address_b[6] => ram_block3a12.PORTBADDR6 +address_b[6] => ram_block3a13.PORTBADDR6 +address_b[6] => ram_block3a14.PORTBADDR6 +address_b[6] => ram_block3a15.PORTBADDR6 +address_b[6] => ram_block3a16.PORTBADDR6 +address_b[6] => ram_block3a17.PORTBADDR6 +address_b[6] => ram_block3a18.PORTBADDR6 +address_b[6] => ram_block3a19.PORTBADDR6 +address_b[6] => ram_block3a20.PORTBADDR6 +address_b[6] => ram_block3a21.PORTBADDR6 +address_b[6] => ram_block3a22.PORTBADDR6 +address_b[6] => ram_block3a23.PORTBADDR6 +address_b[6] => ram_block3a24.PORTBADDR6 +address_b[6] => ram_block3a25.PORTBADDR6 +address_b[6] => ram_block3a26.PORTBADDR6 +address_b[6] => ram_block3a27.PORTBADDR6 +address_b[6] => ram_block3a28.PORTBADDR6 +address_b[6] => ram_block3a29.PORTBADDR6 +address_b[6] => ram_block3a30.PORTBADDR6 +address_b[6] => ram_block3a31.PORTBADDR6 +address_b[6] => ram_block3a32.PORTBADDR6 +address_b[6] => ram_block3a33.PORTBADDR6 +address_b[6] => ram_block3a34.PORTBADDR6 +address_b[6] => ram_block3a35.PORTBADDR6 +address_b[6] => ram_block3a36.PORTBADDR6 +address_b[6] => ram_block3a37.PORTBADDR6 +address_b[6] => ram_block3a38.PORTBADDR6 +address_b[6] => ram_block3a39.PORTBADDR6 +address_b[6] => ram_block3a40.PORTBADDR6 +address_b[6] => ram_block3a41.PORTBADDR6 +address_b[6] => ram_block3a42.PORTBADDR6 +address_b[6] => ram_block3a43.PORTBADDR6 +address_b[6] => ram_block3a44.PORTBADDR6 +address_b[6] => ram_block3a45.PORTBADDR6 +address_b[6] => ram_block3a46.PORTBADDR6 +address_b[6] => ram_block3a47.PORTBADDR6 +address_b[6] => ram_block3a48.PORTBADDR6 +address_b[6] => ram_block3a49.PORTBADDR6 +address_b[6] => ram_block3a50.PORTBADDR6 +address_b[6] => ram_block3a51.PORTBADDR6 +address_b[6] => ram_block3a52.PORTBADDR6 +address_b[6] => ram_block3a53.PORTBADDR6 +address_b[6] => ram_block3a54.PORTBADDR6 +address_b[6] => ram_block3a55.PORTBADDR6 +address_b[6] => ram_block3a56.PORTBADDR6 +address_b[6] => ram_block3a57.PORTBADDR6 +address_b[6] => ram_block3a58.PORTBADDR6 +address_b[6] => ram_block3a59.PORTBADDR6 +address_b[6] => ram_block3a60.PORTBADDR6 +address_b[6] => ram_block3a61.PORTBADDR6 +address_b[6] => ram_block3a62.PORTBADDR6 +address_b[6] => ram_block3a63.PORTBADDR6 +address_b[6] => ram_block3a64.PORTBADDR6 +address_b[6] => ram_block3a65.PORTBADDR6 +address_b[6] => ram_block3a66.PORTBADDR6 +address_b[6] => ram_block3a67.PORTBADDR6 +address_b[6] => ram_block3a68.PORTBADDR6 +address_b[6] => ram_block3a69.PORTBADDR6 +address_b[6] => ram_block3a70.PORTBADDR6 +address_b[6] => ram_block3a71.PORTBADDR6 +address_b[6] => ram_block3a72.PORTBADDR6 +address_b[6] => ram_block3a73.PORTBADDR6 +address_b[6] => ram_block3a74.PORTBADDR6 +address_b[6] => ram_block3a75.PORTBADDR6 +address_b[6] => ram_block3a76.PORTBADDR6 +address_b[6] => ram_block3a77.PORTBADDR6 +address_b[6] => ram_block3a78.PORTBADDR6 +address_b[6] => ram_block3a79.PORTBADDR6 +address_b[6] => ram_block3a80.PORTBADDR6 +address_b[6] => ram_block3a81.PORTBADDR6 +address_b[6] => ram_block3a82.PORTBADDR6 +address_b[6] => ram_block3a83.PORTBADDR6 +address_b[6] => ram_block3a84.PORTBADDR6 +address_b[6] => ram_block3a85.PORTBADDR6 +address_b[6] => ram_block3a86.PORTBADDR6 +address_b[6] => ram_block3a87.PORTBADDR6 +address_b[6] => ram_block3a88.PORTBADDR6 +address_b[6] => ram_block3a89.PORTBADDR6 +address_b[7] => ram_block3a0.PORTBADDR7 +address_b[7] => ram_block3a1.PORTBADDR7 +address_b[7] => ram_block3a2.PORTBADDR7 +address_b[7] => ram_block3a3.PORTBADDR7 +address_b[7] => ram_block3a4.PORTBADDR7 +address_b[7] => ram_block3a5.PORTBADDR7 +address_b[7] => ram_block3a6.PORTBADDR7 +address_b[7] => ram_block3a7.PORTBADDR7 +address_b[7] => ram_block3a8.PORTBADDR7 +address_b[7] => ram_block3a9.PORTBADDR7 +address_b[7] => ram_block3a10.PORTBADDR7 +address_b[7] => ram_block3a11.PORTBADDR7 +address_b[7] => ram_block3a12.PORTBADDR7 +address_b[7] => ram_block3a13.PORTBADDR7 +address_b[7] => ram_block3a14.PORTBADDR7 +address_b[7] => ram_block3a15.PORTBADDR7 +address_b[7] => ram_block3a16.PORTBADDR7 +address_b[7] => ram_block3a17.PORTBADDR7 +address_b[7] => ram_block3a18.PORTBADDR7 +address_b[7] => ram_block3a19.PORTBADDR7 +address_b[7] => ram_block3a20.PORTBADDR7 +address_b[7] => ram_block3a21.PORTBADDR7 +address_b[7] => ram_block3a22.PORTBADDR7 +address_b[7] => ram_block3a23.PORTBADDR7 +address_b[7] => ram_block3a24.PORTBADDR7 +address_b[7] => ram_block3a25.PORTBADDR7 +address_b[7] => ram_block3a26.PORTBADDR7 +address_b[7] => ram_block3a27.PORTBADDR7 +address_b[7] => ram_block3a28.PORTBADDR7 +address_b[7] => ram_block3a29.PORTBADDR7 +address_b[7] => ram_block3a30.PORTBADDR7 +address_b[7] => ram_block3a31.PORTBADDR7 +address_b[7] => ram_block3a32.PORTBADDR7 +address_b[7] => ram_block3a33.PORTBADDR7 +address_b[7] => ram_block3a34.PORTBADDR7 +address_b[7] => ram_block3a35.PORTBADDR7 +address_b[7] => ram_block3a36.PORTBADDR7 +address_b[7] => ram_block3a37.PORTBADDR7 +address_b[7] => ram_block3a38.PORTBADDR7 +address_b[7] => ram_block3a39.PORTBADDR7 +address_b[7] => ram_block3a40.PORTBADDR7 +address_b[7] => ram_block3a41.PORTBADDR7 +address_b[7] => ram_block3a42.PORTBADDR7 +address_b[7] => ram_block3a43.PORTBADDR7 +address_b[7] => ram_block3a44.PORTBADDR7 +address_b[7] => ram_block3a45.PORTBADDR7 +address_b[7] => ram_block3a46.PORTBADDR7 +address_b[7] => ram_block3a47.PORTBADDR7 +address_b[7] => ram_block3a48.PORTBADDR7 +address_b[7] => ram_block3a49.PORTBADDR7 +address_b[7] => ram_block3a50.PORTBADDR7 +address_b[7] => ram_block3a51.PORTBADDR7 +address_b[7] => ram_block3a52.PORTBADDR7 +address_b[7] => ram_block3a53.PORTBADDR7 +address_b[7] => ram_block3a54.PORTBADDR7 +address_b[7] => ram_block3a55.PORTBADDR7 +address_b[7] => ram_block3a56.PORTBADDR7 +address_b[7] => ram_block3a57.PORTBADDR7 +address_b[7] => ram_block3a58.PORTBADDR7 +address_b[7] => ram_block3a59.PORTBADDR7 +address_b[7] => ram_block3a60.PORTBADDR7 +address_b[7] => ram_block3a61.PORTBADDR7 +address_b[7] => ram_block3a62.PORTBADDR7 +address_b[7] => ram_block3a63.PORTBADDR7 +address_b[7] => ram_block3a64.PORTBADDR7 +address_b[7] => ram_block3a65.PORTBADDR7 +address_b[7] => ram_block3a66.PORTBADDR7 +address_b[7] => ram_block3a67.PORTBADDR7 +address_b[7] => ram_block3a68.PORTBADDR7 +address_b[7] => ram_block3a69.PORTBADDR7 +address_b[7] => ram_block3a70.PORTBADDR7 +address_b[7] => ram_block3a71.PORTBADDR7 +address_b[7] => ram_block3a72.PORTBADDR7 +address_b[7] => ram_block3a73.PORTBADDR7 +address_b[7] => ram_block3a74.PORTBADDR7 +address_b[7] => ram_block3a75.PORTBADDR7 +address_b[7] => ram_block3a76.PORTBADDR7 +address_b[7] => ram_block3a77.PORTBADDR7 +address_b[7] => ram_block3a78.PORTBADDR7 +address_b[7] => ram_block3a79.PORTBADDR7 +address_b[7] => ram_block3a80.PORTBADDR7 +address_b[7] => ram_block3a81.PORTBADDR7 +address_b[7] => ram_block3a82.PORTBADDR7 +address_b[7] => ram_block3a83.PORTBADDR7 +address_b[7] => ram_block3a84.PORTBADDR7 +address_b[7] => ram_block3a85.PORTBADDR7 +address_b[7] => ram_block3a86.PORTBADDR7 +address_b[7] => ram_block3a87.PORTBADDR7 +address_b[7] => ram_block3a88.PORTBADDR7 +address_b[7] => ram_block3a89.PORTBADDR7 +address_b[8] => ram_block3a0.PORTBADDR8 +address_b[8] => ram_block3a1.PORTBADDR8 +address_b[8] => ram_block3a2.PORTBADDR8 +address_b[8] => ram_block3a3.PORTBADDR8 +address_b[8] => ram_block3a4.PORTBADDR8 +address_b[8] => ram_block3a5.PORTBADDR8 +address_b[8] => ram_block3a6.PORTBADDR8 +address_b[8] => ram_block3a7.PORTBADDR8 +address_b[8] => ram_block3a8.PORTBADDR8 +address_b[8] => ram_block3a9.PORTBADDR8 +address_b[8] => ram_block3a10.PORTBADDR8 +address_b[8] => ram_block3a11.PORTBADDR8 +address_b[8] => ram_block3a12.PORTBADDR8 +address_b[8] => ram_block3a13.PORTBADDR8 +address_b[8] => ram_block3a14.PORTBADDR8 +address_b[8] => ram_block3a15.PORTBADDR8 +address_b[8] => ram_block3a16.PORTBADDR8 +address_b[8] => ram_block3a17.PORTBADDR8 +address_b[8] => ram_block3a18.PORTBADDR8 +address_b[8] => ram_block3a19.PORTBADDR8 +address_b[8] => ram_block3a20.PORTBADDR8 +address_b[8] => ram_block3a21.PORTBADDR8 +address_b[8] => ram_block3a22.PORTBADDR8 +address_b[8] => ram_block3a23.PORTBADDR8 +address_b[8] => ram_block3a24.PORTBADDR8 +address_b[8] => ram_block3a25.PORTBADDR8 +address_b[8] => ram_block3a26.PORTBADDR8 +address_b[8] => ram_block3a27.PORTBADDR8 +address_b[8] => ram_block3a28.PORTBADDR8 +address_b[8] => ram_block3a29.PORTBADDR8 +address_b[8] => ram_block3a30.PORTBADDR8 +address_b[8] => ram_block3a31.PORTBADDR8 +address_b[8] => ram_block3a32.PORTBADDR8 +address_b[8] => ram_block3a33.PORTBADDR8 +address_b[8] => ram_block3a34.PORTBADDR8 +address_b[8] => ram_block3a35.PORTBADDR8 +address_b[8] => ram_block3a36.PORTBADDR8 +address_b[8] => ram_block3a37.PORTBADDR8 +address_b[8] => ram_block3a38.PORTBADDR8 +address_b[8] => ram_block3a39.PORTBADDR8 +address_b[8] => ram_block3a40.PORTBADDR8 +address_b[8] => ram_block3a41.PORTBADDR8 +address_b[8] => ram_block3a42.PORTBADDR8 +address_b[8] => ram_block3a43.PORTBADDR8 +address_b[8] => ram_block3a44.PORTBADDR8 +address_b[8] => ram_block3a45.PORTBADDR8 +address_b[8] => ram_block3a46.PORTBADDR8 +address_b[8] => ram_block3a47.PORTBADDR8 +address_b[8] => ram_block3a48.PORTBADDR8 +address_b[8] => ram_block3a49.PORTBADDR8 +address_b[8] => ram_block3a50.PORTBADDR8 +address_b[8] => ram_block3a51.PORTBADDR8 +address_b[8] => ram_block3a52.PORTBADDR8 +address_b[8] => ram_block3a53.PORTBADDR8 +address_b[8] => ram_block3a54.PORTBADDR8 +address_b[8] => ram_block3a55.PORTBADDR8 +address_b[8] => ram_block3a56.PORTBADDR8 +address_b[8] => ram_block3a57.PORTBADDR8 +address_b[8] => ram_block3a58.PORTBADDR8 +address_b[8] => ram_block3a59.PORTBADDR8 +address_b[8] => ram_block3a60.PORTBADDR8 +address_b[8] => ram_block3a61.PORTBADDR8 +address_b[8] => ram_block3a62.PORTBADDR8 +address_b[8] => ram_block3a63.PORTBADDR8 +address_b[8] => ram_block3a64.PORTBADDR8 +address_b[8] => ram_block3a65.PORTBADDR8 +address_b[8] => ram_block3a66.PORTBADDR8 +address_b[8] => ram_block3a67.PORTBADDR8 +address_b[8] => ram_block3a68.PORTBADDR8 +address_b[8] => ram_block3a69.PORTBADDR8 +address_b[8] => ram_block3a70.PORTBADDR8 +address_b[8] => ram_block3a71.PORTBADDR8 +address_b[8] => ram_block3a72.PORTBADDR8 +address_b[8] => ram_block3a73.PORTBADDR8 +address_b[8] => ram_block3a74.PORTBADDR8 +address_b[8] => ram_block3a75.PORTBADDR8 +address_b[8] => ram_block3a76.PORTBADDR8 +address_b[8] => ram_block3a77.PORTBADDR8 +address_b[8] => ram_block3a78.PORTBADDR8 +address_b[8] => ram_block3a79.PORTBADDR8 +address_b[8] => ram_block3a80.PORTBADDR8 +address_b[8] => ram_block3a81.PORTBADDR8 +address_b[8] => ram_block3a82.PORTBADDR8 +address_b[8] => ram_block3a83.PORTBADDR8 +address_b[8] => ram_block3a84.PORTBADDR8 +address_b[8] => ram_block3a85.PORTBADDR8 +address_b[8] => ram_block3a86.PORTBADDR8 +address_b[8] => ram_block3a87.PORTBADDR8 +address_b[8] => ram_block3a88.PORTBADDR8 +address_b[8] => ram_block3a89.PORTBADDR8 +address_b[9] => ram_block3a0.PORTBADDR9 +address_b[9] => ram_block3a1.PORTBADDR9 +address_b[9] => ram_block3a2.PORTBADDR9 +address_b[9] => ram_block3a3.PORTBADDR9 +address_b[9] => ram_block3a4.PORTBADDR9 +address_b[9] => ram_block3a5.PORTBADDR9 +address_b[9] => ram_block3a6.PORTBADDR9 +address_b[9] => ram_block3a7.PORTBADDR9 +address_b[9] => ram_block3a8.PORTBADDR9 +address_b[9] => ram_block3a9.PORTBADDR9 +address_b[9] => ram_block3a10.PORTBADDR9 +address_b[9] => ram_block3a11.PORTBADDR9 +address_b[9] => ram_block3a12.PORTBADDR9 +address_b[9] => ram_block3a13.PORTBADDR9 +address_b[9] => ram_block3a14.PORTBADDR9 +address_b[9] => ram_block3a15.PORTBADDR9 +address_b[9] => ram_block3a16.PORTBADDR9 +address_b[9] => ram_block3a17.PORTBADDR9 +address_b[9] => ram_block3a18.PORTBADDR9 +address_b[9] => ram_block3a19.PORTBADDR9 +address_b[9] => ram_block3a20.PORTBADDR9 +address_b[9] => ram_block3a21.PORTBADDR9 +address_b[9] => ram_block3a22.PORTBADDR9 +address_b[9] => ram_block3a23.PORTBADDR9 +address_b[9] => ram_block3a24.PORTBADDR9 +address_b[9] => ram_block3a25.PORTBADDR9 +address_b[9] => ram_block3a26.PORTBADDR9 +address_b[9] => ram_block3a27.PORTBADDR9 +address_b[9] => ram_block3a28.PORTBADDR9 +address_b[9] => ram_block3a29.PORTBADDR9 +address_b[9] => ram_block3a30.PORTBADDR9 +address_b[9] => ram_block3a31.PORTBADDR9 +address_b[9] => ram_block3a32.PORTBADDR9 +address_b[9] => ram_block3a33.PORTBADDR9 +address_b[9] => ram_block3a34.PORTBADDR9 +address_b[9] => ram_block3a35.PORTBADDR9 +address_b[9] => ram_block3a36.PORTBADDR9 +address_b[9] => ram_block3a37.PORTBADDR9 +address_b[9] => ram_block3a38.PORTBADDR9 +address_b[9] => ram_block3a39.PORTBADDR9 +address_b[9] => ram_block3a40.PORTBADDR9 +address_b[9] => ram_block3a41.PORTBADDR9 +address_b[9] => ram_block3a42.PORTBADDR9 +address_b[9] => ram_block3a43.PORTBADDR9 +address_b[9] => ram_block3a44.PORTBADDR9 +address_b[9] => ram_block3a45.PORTBADDR9 +address_b[9] => ram_block3a46.PORTBADDR9 +address_b[9] => ram_block3a47.PORTBADDR9 +address_b[9] => ram_block3a48.PORTBADDR9 +address_b[9] => ram_block3a49.PORTBADDR9 +address_b[9] => ram_block3a50.PORTBADDR9 +address_b[9] => ram_block3a51.PORTBADDR9 +address_b[9] => ram_block3a52.PORTBADDR9 +address_b[9] => ram_block3a53.PORTBADDR9 +address_b[9] => ram_block3a54.PORTBADDR9 +address_b[9] => ram_block3a55.PORTBADDR9 +address_b[9] => ram_block3a56.PORTBADDR9 +address_b[9] => ram_block3a57.PORTBADDR9 +address_b[9] => ram_block3a58.PORTBADDR9 +address_b[9] => ram_block3a59.PORTBADDR9 +address_b[9] => ram_block3a60.PORTBADDR9 +address_b[9] => ram_block3a61.PORTBADDR9 +address_b[9] => ram_block3a62.PORTBADDR9 +address_b[9] => ram_block3a63.PORTBADDR9 +address_b[9] => ram_block3a64.PORTBADDR9 +address_b[9] => ram_block3a65.PORTBADDR9 +address_b[9] => ram_block3a66.PORTBADDR9 +address_b[9] => ram_block3a67.PORTBADDR9 +address_b[9] => ram_block3a68.PORTBADDR9 +address_b[9] => ram_block3a69.PORTBADDR9 +address_b[9] => ram_block3a70.PORTBADDR9 +address_b[9] => ram_block3a71.PORTBADDR9 +address_b[9] => ram_block3a72.PORTBADDR9 +address_b[9] => ram_block3a73.PORTBADDR9 +address_b[9] => ram_block3a74.PORTBADDR9 +address_b[9] => ram_block3a75.PORTBADDR9 +address_b[9] => ram_block3a76.PORTBADDR9 +address_b[9] => ram_block3a77.PORTBADDR9 +address_b[9] => ram_block3a78.PORTBADDR9 +address_b[9] => ram_block3a79.PORTBADDR9 +address_b[9] => ram_block3a80.PORTBADDR9 +address_b[9] => ram_block3a81.PORTBADDR9 +address_b[9] => ram_block3a82.PORTBADDR9 +address_b[9] => ram_block3a83.PORTBADDR9 +address_b[9] => ram_block3a84.PORTBADDR9 +address_b[9] => ram_block3a85.PORTBADDR9 +address_b[9] => ram_block3a86.PORTBADDR9 +address_b[9] => ram_block3a87.PORTBADDR9 +address_b[9] => ram_block3a88.PORTBADDR9 +address_b[9] => ram_block3a89.PORTBADDR9 +clock0 => ram_block3a0.CLK0 +clock0 => ram_block3a1.CLK0 +clock0 => ram_block3a2.CLK0 +clock0 => ram_block3a3.CLK0 +clock0 => ram_block3a4.CLK0 +clock0 => ram_block3a5.CLK0 +clock0 => ram_block3a6.CLK0 +clock0 => ram_block3a7.CLK0 +clock0 => ram_block3a8.CLK0 +clock0 => ram_block3a9.CLK0 +clock0 => ram_block3a10.CLK0 +clock0 => ram_block3a11.CLK0 +clock0 => ram_block3a12.CLK0 +clock0 => ram_block3a13.CLK0 +clock0 => ram_block3a14.CLK0 +clock0 => ram_block3a15.CLK0 +clock0 => ram_block3a16.CLK0 +clock0 => ram_block3a17.CLK0 +clock0 => ram_block3a18.CLK0 +clock0 => ram_block3a19.CLK0 +clock0 => ram_block3a20.CLK0 +clock0 => ram_block3a21.CLK0 +clock0 => ram_block3a22.CLK0 +clock0 => ram_block3a23.CLK0 +clock0 => ram_block3a24.CLK0 +clock0 => ram_block3a25.CLK0 +clock0 => ram_block3a26.CLK0 +clock0 => ram_block3a27.CLK0 +clock0 => ram_block3a28.CLK0 +clock0 => ram_block3a29.CLK0 +clock0 => ram_block3a30.CLK0 +clock0 => ram_block3a31.CLK0 +clock0 => ram_block3a32.CLK0 +clock0 => ram_block3a33.CLK0 +clock0 => ram_block3a34.CLK0 +clock0 => ram_block3a35.CLK0 +clock0 => ram_block3a36.CLK0 +clock0 => ram_block3a37.CLK0 +clock0 => ram_block3a38.CLK0 +clock0 => ram_block3a39.CLK0 +clock0 => ram_block3a40.CLK0 +clock0 => ram_block3a41.CLK0 +clock0 => ram_block3a42.CLK0 +clock0 => ram_block3a43.CLK0 +clock0 => ram_block3a44.CLK0 +clock0 => ram_block3a45.CLK0 +clock0 => ram_block3a46.CLK0 +clock0 => ram_block3a47.CLK0 +clock0 => ram_block3a48.CLK0 +clock0 => ram_block3a49.CLK0 +clock0 => ram_block3a50.CLK0 +clock0 => ram_block3a51.CLK0 +clock0 => ram_block3a52.CLK0 +clock0 => ram_block3a53.CLK0 +clock0 => ram_block3a54.CLK0 +clock0 => ram_block3a55.CLK0 +clock0 => ram_block3a56.CLK0 +clock0 => ram_block3a57.CLK0 +clock0 => ram_block3a58.CLK0 +clock0 => ram_block3a59.CLK0 +clock0 => ram_block3a60.CLK0 +clock0 => ram_block3a61.CLK0 +clock0 => ram_block3a62.CLK0 +clock0 => ram_block3a63.CLK0 +clock0 => ram_block3a64.CLK0 +clock0 => ram_block3a65.CLK0 +clock0 => ram_block3a66.CLK0 +clock0 => ram_block3a67.CLK0 +clock0 => ram_block3a68.CLK0 +clock0 => ram_block3a69.CLK0 +clock0 => ram_block3a70.CLK0 +clock0 => ram_block3a71.CLK0 +clock0 => ram_block3a72.CLK0 +clock0 => ram_block3a73.CLK0 +clock0 => ram_block3a74.CLK0 +clock0 => ram_block3a75.CLK0 +clock0 => ram_block3a76.CLK0 +clock0 => ram_block3a77.CLK0 +clock0 => ram_block3a78.CLK0 +clock0 => ram_block3a79.CLK0 +clock0 => ram_block3a80.CLK0 +clock0 => ram_block3a81.CLK0 +clock0 => ram_block3a82.CLK0 +clock0 => ram_block3a83.CLK0 +clock0 => ram_block3a84.CLK0 +clock0 => ram_block3a85.CLK0 +clock0 => ram_block3a86.CLK0 +clock0 => ram_block3a87.CLK0 +clock0 => ram_block3a88.CLK0 +clock0 => ram_block3a89.CLK0 +clocken0 => ram_block3a0.ENA0 +clocken0 => ram_block3a1.ENA0 +clocken0 => ram_block3a2.ENA0 +clocken0 => ram_block3a3.ENA0 +clocken0 => ram_block3a4.ENA0 +clocken0 => ram_block3a5.ENA0 +clocken0 => ram_block3a6.ENA0 +clocken0 => ram_block3a7.ENA0 +clocken0 => ram_block3a8.ENA0 +clocken0 => ram_block3a9.ENA0 +clocken0 => ram_block3a10.ENA0 +clocken0 => ram_block3a11.ENA0 +clocken0 => ram_block3a12.ENA0 +clocken0 => ram_block3a13.ENA0 +clocken0 => ram_block3a14.ENA0 +clocken0 => ram_block3a15.ENA0 +clocken0 => ram_block3a16.ENA0 +clocken0 => ram_block3a17.ENA0 +clocken0 => ram_block3a18.ENA0 +clocken0 => ram_block3a19.ENA0 +clocken0 => ram_block3a20.ENA0 +clocken0 => ram_block3a21.ENA0 +clocken0 => ram_block3a22.ENA0 +clocken0 => ram_block3a23.ENA0 +clocken0 => ram_block3a24.ENA0 +clocken0 => ram_block3a25.ENA0 +clocken0 => ram_block3a26.ENA0 +clocken0 => ram_block3a27.ENA0 +clocken0 => ram_block3a28.ENA0 +clocken0 => ram_block3a29.ENA0 +clocken0 => ram_block3a30.ENA0 +clocken0 => ram_block3a31.ENA0 +clocken0 => ram_block3a32.ENA0 +clocken0 => ram_block3a33.ENA0 +clocken0 => ram_block3a34.ENA0 +clocken0 => ram_block3a35.ENA0 +clocken0 => ram_block3a36.ENA0 +clocken0 => ram_block3a37.ENA0 +clocken0 => ram_block3a38.ENA0 +clocken0 => ram_block3a39.ENA0 +clocken0 => ram_block3a40.ENA0 +clocken0 => ram_block3a41.ENA0 +clocken0 => ram_block3a42.ENA0 +clocken0 => ram_block3a43.ENA0 +clocken0 => ram_block3a44.ENA0 +clocken0 => ram_block3a45.ENA0 +clocken0 => ram_block3a46.ENA0 +clocken0 => ram_block3a47.ENA0 +clocken0 => ram_block3a48.ENA0 +clocken0 => ram_block3a49.ENA0 +clocken0 => ram_block3a50.ENA0 +clocken0 => ram_block3a51.ENA0 +clocken0 => ram_block3a52.ENA0 +clocken0 => ram_block3a53.ENA0 +clocken0 => ram_block3a54.ENA0 +clocken0 => ram_block3a55.ENA0 +clocken0 => ram_block3a56.ENA0 +clocken0 => ram_block3a57.ENA0 +clocken0 => ram_block3a58.ENA0 +clocken0 => ram_block3a59.ENA0 +clocken0 => ram_block3a60.ENA0 +clocken0 => ram_block3a61.ENA0 +clocken0 => ram_block3a62.ENA0 +clocken0 => ram_block3a63.ENA0 +clocken0 => ram_block3a64.ENA0 +clocken0 => ram_block3a65.ENA0 +clocken0 => ram_block3a66.ENA0 +clocken0 => ram_block3a67.ENA0 +clocken0 => ram_block3a68.ENA0 +clocken0 => ram_block3a69.ENA0 +clocken0 => ram_block3a70.ENA0 +clocken0 => ram_block3a71.ENA0 +clocken0 => ram_block3a72.ENA0 +clocken0 => ram_block3a73.ENA0 +clocken0 => ram_block3a74.ENA0 +clocken0 => ram_block3a75.ENA0 +clocken0 => ram_block3a76.ENA0 +clocken0 => ram_block3a77.ENA0 +clocken0 => ram_block3a78.ENA0 +clocken0 => ram_block3a79.ENA0 +clocken0 => ram_block3a80.ENA0 +clocken0 => ram_block3a81.ENA0 +clocken0 => ram_block3a82.ENA0 +clocken0 => ram_block3a83.ENA0 +clocken0 => ram_block3a84.ENA0 +clocken0 => ram_block3a85.ENA0 +clocken0 => ram_block3a86.ENA0 +clocken0 => ram_block3a87.ENA0 +clocken0 => ram_block3a88.ENA0 +clocken0 => ram_block3a89.ENA0 +data_a[0] => ram_block3a0.PORTADATAIN +data_a[1] => ram_block3a1.PORTADATAIN +data_a[2] => ram_block3a2.PORTADATAIN +data_a[3] => ram_block3a3.PORTADATAIN +data_a[4] => ram_block3a4.PORTADATAIN +data_a[5] => ram_block3a5.PORTADATAIN +data_a[6] => ram_block3a6.PORTADATAIN +data_a[7] => ram_block3a7.PORTADATAIN +data_a[8] => ram_block3a8.PORTADATAIN +data_a[9] => ram_block3a9.PORTADATAIN +data_a[10] => ram_block3a10.PORTADATAIN +data_a[11] => ram_block3a11.PORTADATAIN +data_a[12] => ram_block3a12.PORTADATAIN +data_a[13] => ram_block3a13.PORTADATAIN +data_a[14] => ram_block3a14.PORTADATAIN +data_a[15] => ram_block3a15.PORTADATAIN +data_a[16] => ram_block3a16.PORTADATAIN +data_a[17] => ram_block3a17.PORTADATAIN +data_a[18] => ram_block3a18.PORTADATAIN +data_a[19] => ram_block3a19.PORTADATAIN +data_a[20] => ram_block3a20.PORTADATAIN +data_a[21] => ram_block3a21.PORTADATAIN +data_a[22] => ram_block3a22.PORTADATAIN +data_a[23] => ram_block3a23.PORTADATAIN +data_a[24] => ram_block3a24.PORTADATAIN +data_a[25] => ram_block3a25.PORTADATAIN +data_a[26] => ram_block3a26.PORTADATAIN +data_a[27] => ram_block3a27.PORTADATAIN +data_a[28] => ram_block3a28.PORTADATAIN +data_a[29] => ram_block3a29.PORTADATAIN +data_a[30] => ram_block3a30.PORTADATAIN +data_a[31] => ram_block3a31.PORTADATAIN +data_a[32] => ram_block3a32.PORTADATAIN +data_a[33] => ram_block3a33.PORTADATAIN +data_a[34] => ram_block3a34.PORTADATAIN +data_a[35] => ram_block3a35.PORTADATAIN +data_a[36] => ram_block3a36.PORTADATAIN +data_a[37] => ram_block3a37.PORTADATAIN +data_a[38] => ram_block3a38.PORTADATAIN +data_a[39] => ram_block3a39.PORTADATAIN +data_a[40] => ram_block3a40.PORTADATAIN +data_a[41] => ram_block3a41.PORTADATAIN +data_a[42] => ram_block3a42.PORTADATAIN +data_a[43] => ram_block3a43.PORTADATAIN +data_a[44] => ram_block3a44.PORTADATAIN +data_a[45] => ram_block3a45.PORTADATAIN +data_a[46] => ram_block3a46.PORTADATAIN +data_a[47] => ram_block3a47.PORTADATAIN +data_a[48] => ram_block3a48.PORTADATAIN +data_a[49] => ram_block3a49.PORTADATAIN +data_a[50] => ram_block3a50.PORTADATAIN +data_a[51] => ram_block3a51.PORTADATAIN +data_a[52] => ram_block3a52.PORTADATAIN +data_a[53] => ram_block3a53.PORTADATAIN +data_a[54] => ram_block3a54.PORTADATAIN +data_a[55] => ram_block3a55.PORTADATAIN +data_a[56] => ram_block3a56.PORTADATAIN +data_a[57] => ram_block3a57.PORTADATAIN +data_a[58] => ram_block3a58.PORTADATAIN +data_a[59] => ram_block3a59.PORTADATAIN +data_a[60] => ram_block3a60.PORTADATAIN +data_a[61] => ram_block3a61.PORTADATAIN +data_a[62] => ram_block3a62.PORTADATAIN +data_a[63] => ram_block3a63.PORTADATAIN +data_a[64] => ram_block3a64.PORTADATAIN +data_a[65] => ram_block3a65.PORTADATAIN +data_a[66] => ram_block3a66.PORTADATAIN +data_a[67] => ram_block3a67.PORTADATAIN +data_a[68] => ram_block3a68.PORTADATAIN +data_a[69] => ram_block3a69.PORTADATAIN +data_a[70] => ram_block3a70.PORTADATAIN +data_a[71] => ram_block3a71.PORTADATAIN +data_a[72] => ram_block3a72.PORTADATAIN +data_a[73] => ram_block3a73.PORTADATAIN +data_a[74] => ram_block3a74.PORTADATAIN +data_a[75] => ram_block3a75.PORTADATAIN +data_a[76] => ram_block3a76.PORTADATAIN +data_a[77] => ram_block3a77.PORTADATAIN +data_a[78] => ram_block3a78.PORTADATAIN +data_a[79] => ram_block3a79.PORTADATAIN +data_a[80] => ram_block3a80.PORTADATAIN +data_a[81] => ram_block3a81.PORTADATAIN +data_a[82] => ram_block3a82.PORTADATAIN +data_a[83] => ram_block3a83.PORTADATAIN +data_a[84] => ram_block3a84.PORTADATAIN +data_a[85] => ram_block3a85.PORTADATAIN +data_a[86] => ram_block3a86.PORTADATAIN +data_a[87] => ram_block3a87.PORTADATAIN +data_a[88] => ram_block3a88.PORTADATAIN +data_a[89] => ram_block3a89.PORTADATAIN +q_b[0] <= ram_block3a0.PORTBDATAOUT +q_b[1] <= ram_block3a1.PORTBDATAOUT +q_b[2] <= ram_block3a2.PORTBDATAOUT +q_b[3] <= ram_block3a3.PORTBDATAOUT +q_b[4] <= ram_block3a4.PORTBDATAOUT +q_b[5] <= ram_block3a5.PORTBDATAOUT +q_b[6] <= ram_block3a6.PORTBDATAOUT +q_b[7] <= ram_block3a7.PORTBDATAOUT +q_b[8] <= ram_block3a8.PORTBDATAOUT +q_b[9] <= ram_block3a9.PORTBDATAOUT +q_b[10] <= ram_block3a10.PORTBDATAOUT +q_b[11] <= ram_block3a11.PORTBDATAOUT +q_b[12] <= ram_block3a12.PORTBDATAOUT +q_b[13] <= ram_block3a13.PORTBDATAOUT +q_b[14] <= ram_block3a14.PORTBDATAOUT +q_b[15] <= ram_block3a15.PORTBDATAOUT +q_b[16] <= ram_block3a16.PORTBDATAOUT +q_b[17] <= ram_block3a17.PORTBDATAOUT +q_b[18] <= ram_block3a18.PORTBDATAOUT +q_b[19] <= ram_block3a19.PORTBDATAOUT +q_b[20] <= ram_block3a20.PORTBDATAOUT +q_b[21] <= ram_block3a21.PORTBDATAOUT +q_b[22] <= ram_block3a22.PORTBDATAOUT +q_b[23] <= ram_block3a23.PORTBDATAOUT +q_b[24] <= ram_block3a24.PORTBDATAOUT +q_b[25] <= ram_block3a25.PORTBDATAOUT +q_b[26] <= ram_block3a26.PORTBDATAOUT +q_b[27] <= ram_block3a27.PORTBDATAOUT +q_b[28] <= ram_block3a28.PORTBDATAOUT +q_b[29] <= ram_block3a29.PORTBDATAOUT +q_b[30] <= ram_block3a30.PORTBDATAOUT +q_b[31] <= ram_block3a31.PORTBDATAOUT +q_b[32] <= ram_block3a32.PORTBDATAOUT +q_b[33] <= ram_block3a33.PORTBDATAOUT +q_b[34] <= ram_block3a34.PORTBDATAOUT +q_b[35] <= ram_block3a35.PORTBDATAOUT +q_b[36] <= ram_block3a36.PORTBDATAOUT +q_b[37] <= ram_block3a37.PORTBDATAOUT +q_b[38] <= ram_block3a38.PORTBDATAOUT +q_b[39] <= ram_block3a39.PORTBDATAOUT +q_b[40] <= ram_block3a40.PORTBDATAOUT +q_b[41] <= ram_block3a41.PORTBDATAOUT +q_b[42] <= ram_block3a42.PORTBDATAOUT +q_b[43] <= ram_block3a43.PORTBDATAOUT +q_b[44] <= ram_block3a44.PORTBDATAOUT +q_b[45] <= ram_block3a45.PORTBDATAOUT +q_b[46] <= ram_block3a46.PORTBDATAOUT +q_b[47] <= ram_block3a47.PORTBDATAOUT +q_b[48] <= ram_block3a48.PORTBDATAOUT +q_b[49] <= ram_block3a49.PORTBDATAOUT +q_b[50] <= ram_block3a50.PORTBDATAOUT +q_b[51] <= ram_block3a51.PORTBDATAOUT +q_b[52] <= ram_block3a52.PORTBDATAOUT +q_b[53] <= ram_block3a53.PORTBDATAOUT +q_b[54] <= ram_block3a54.PORTBDATAOUT +q_b[55] <= ram_block3a55.PORTBDATAOUT +q_b[56] <= ram_block3a56.PORTBDATAOUT +q_b[57] <= ram_block3a57.PORTBDATAOUT +q_b[58] <= ram_block3a58.PORTBDATAOUT +q_b[59] <= ram_block3a59.PORTBDATAOUT +q_b[60] <= ram_block3a60.PORTBDATAOUT +q_b[61] <= ram_block3a61.PORTBDATAOUT +q_b[62] <= ram_block3a62.PORTBDATAOUT +q_b[63] <= ram_block3a63.PORTBDATAOUT +q_b[64] <= ram_block3a64.PORTBDATAOUT +q_b[65] <= ram_block3a65.PORTBDATAOUT +q_b[66] <= ram_block3a66.PORTBDATAOUT +q_b[67] <= ram_block3a67.PORTBDATAOUT +q_b[68] <= ram_block3a68.PORTBDATAOUT +q_b[69] <= ram_block3a69.PORTBDATAOUT +q_b[70] <= ram_block3a70.PORTBDATAOUT +q_b[71] <= ram_block3a71.PORTBDATAOUT +q_b[72] <= ram_block3a72.PORTBDATAOUT +q_b[73] <= ram_block3a73.PORTBDATAOUT +q_b[74] <= ram_block3a74.PORTBDATAOUT +q_b[75] <= ram_block3a75.PORTBDATAOUT +q_b[76] <= ram_block3a76.PORTBDATAOUT +q_b[77] <= ram_block3a77.PORTBDATAOUT +q_b[78] <= ram_block3a78.PORTBDATAOUT +q_b[79] <= ram_block3a79.PORTBDATAOUT +q_b[80] <= ram_block3a80.PORTBDATAOUT +q_b[81] <= ram_block3a81.PORTBDATAOUT +q_b[82] <= ram_block3a82.PORTBDATAOUT +q_b[83] <= ram_block3a83.PORTBDATAOUT +q_b[84] <= ram_block3a84.PORTBDATAOUT +q_b[85] <= ram_block3a85.PORTBDATAOUT +q_b[86] <= ram_block3a86.PORTBDATAOUT +q_b[87] <= ram_block3a87.PORTBDATAOUT +q_b[88] <= ram_block3a88.PORTBDATAOUT +q_b[89] <= ram_block3a89.PORTBDATAOUT +wren_a => ram_block3a0.PORTAWE +wren_a => ram_block3a1.PORTAWE +wren_a => ram_block3a2.PORTAWE +wren_a => ram_block3a3.PORTAWE +wren_a => ram_block3a4.PORTAWE +wren_a => ram_block3a5.PORTAWE +wren_a => ram_block3a6.PORTAWE +wren_a => ram_block3a7.PORTAWE +wren_a => ram_block3a8.PORTAWE +wren_a => ram_block3a9.PORTAWE +wren_a => ram_block3a10.PORTAWE +wren_a => ram_block3a11.PORTAWE +wren_a => ram_block3a12.PORTAWE +wren_a => ram_block3a13.PORTAWE +wren_a => ram_block3a14.PORTAWE +wren_a => ram_block3a15.PORTAWE +wren_a => ram_block3a16.PORTAWE +wren_a => ram_block3a17.PORTAWE +wren_a => ram_block3a18.PORTAWE +wren_a => ram_block3a19.PORTAWE +wren_a => ram_block3a20.PORTAWE +wren_a => ram_block3a21.PORTAWE +wren_a => ram_block3a22.PORTAWE +wren_a => ram_block3a23.PORTAWE +wren_a => ram_block3a24.PORTAWE +wren_a => ram_block3a25.PORTAWE +wren_a => ram_block3a26.PORTAWE +wren_a => ram_block3a27.PORTAWE +wren_a => ram_block3a28.PORTAWE +wren_a => ram_block3a29.PORTAWE +wren_a => ram_block3a30.PORTAWE +wren_a => ram_block3a31.PORTAWE +wren_a => ram_block3a32.PORTAWE +wren_a => ram_block3a33.PORTAWE +wren_a => ram_block3a34.PORTAWE +wren_a => ram_block3a35.PORTAWE +wren_a => ram_block3a36.PORTAWE +wren_a => ram_block3a37.PORTAWE +wren_a => ram_block3a38.PORTAWE +wren_a => ram_block3a39.PORTAWE +wren_a => ram_block3a40.PORTAWE +wren_a => ram_block3a41.PORTAWE +wren_a => ram_block3a42.PORTAWE +wren_a => ram_block3a43.PORTAWE +wren_a => ram_block3a44.PORTAWE +wren_a => ram_block3a45.PORTAWE +wren_a => ram_block3a46.PORTAWE +wren_a => ram_block3a47.PORTAWE +wren_a => ram_block3a48.PORTAWE +wren_a => ram_block3a49.PORTAWE +wren_a => ram_block3a50.PORTAWE +wren_a => ram_block3a51.PORTAWE +wren_a => ram_block3a52.PORTAWE +wren_a => ram_block3a53.PORTAWE +wren_a => ram_block3a54.PORTAWE +wren_a => ram_block3a55.PORTAWE +wren_a => ram_block3a56.PORTAWE +wren_a => ram_block3a57.PORTAWE +wren_a => ram_block3a58.PORTAWE +wren_a => ram_block3a59.PORTAWE +wren_a => ram_block3a60.PORTAWE +wren_a => ram_block3a61.PORTAWE +wren_a => ram_block3a62.PORTAWE +wren_a => ram_block3a63.PORTAWE +wren_a => ram_block3a64.PORTAWE +wren_a => ram_block3a65.PORTAWE +wren_a => ram_block3a66.PORTAWE +wren_a => ram_block3a67.PORTAWE +wren_a => ram_block3a68.PORTAWE +wren_a => ram_block3a69.PORTAWE +wren_a => ram_block3a70.PORTAWE +wren_a => ram_block3a71.PORTAWE +wren_a => ram_block3a72.PORTAWE +wren_a => ram_block3a73.PORTAWE +wren_a => ram_block3a74.PORTAWE +wren_a => ram_block3a75.PORTAWE +wren_a => ram_block3a76.PORTAWE +wren_a => ram_block3a77.PORTAWE +wren_a => ram_block3a78.PORTAWE +wren_a => ram_block3a79.PORTAWE +wren_a => ram_block3a80.PORTAWE +wren_a => ram_block3a81.PORTAWE +wren_a => ram_block3a82.PORTAWE +wren_a => ram_block3a83.PORTAWE +wren_a => ram_block3a84.PORTAWE +wren_a => ram_block3a85.PORTAWE +wren_a => ram_block3a86.PORTAWE +wren_a => ram_block3a87.PORTAWE +wren_a => ram_block3a88.PORTAWE +wren_a => ram_block3a89.PORTAWE + + +|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1 +clk_en => counter_reg_bit[9].IN0 +clock => counter_reg_bit[9].CLK +clock => counter_reg_bit[8].CLK +clock => counter_reg_bit[7].CLK +clock => counter_reg_bit[6].CLK +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= counter_reg_bit[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= counter_reg_bit[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= counter_reg_bit[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= counter_reg_bit[9].DB_MAX_OUTPUT_PORT_TYPE + + +|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1|cmpr_ugc:cmpr4 +aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE +dataa[0] => data_wire[2].IN0 +dataa[1] => data_wire[2].IN0 +dataa[2] => data_wire[3].IN0 +dataa[3] => data_wire[3].IN0 +dataa[4] => data_wire[4].IN0 +dataa[5] => data_wire[4].IN0 +dataa[6] => data_wire[5].IN0 +dataa[7] => data_wire[5].IN0 +dataa[8] => data_wire[6].IN0 +dataa[9] => data_wire[6].IN0 +datab[0] => data_wire[2].IN1 +datab[1] => data_wire[2].IN1 +datab[2] => data_wire[3].IN1 +datab[3] => data_wire[3].IN1 +datab[4] => data_wire[4].IN1 +datab[5] => data_wire[4].IN1 +datab[6] => data_wire[5].IN1 +datab[7] => data_wire[5].IN1 +datab[8] => data_wire[6].IN1 +datab[9] => data_wire[6].IN1 + + |