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Diffstat (limited to 'student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf')
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1 files changed, 587 insertions, 0 deletions
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf new file mode 100644 index 0000000..2195635 --- /dev/null +++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf @@ -0,0 +1,587 @@ +--altsyncram ADDRESS_ACLR_B="CLEAR1" ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone III" LOW_POWER_MODE="AUTO" OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="CLEAR1" OUTDATA_REG_B="CLOCK1" RAM_BLOCK_TYPE="M4K" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=9 WIDTHAD_B=9 aclr1 address_a address_b addressstall_b clock0 clock1 clocken1 data_a q_b wren_a +--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneiii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_de51 +( + aclr1 : input; + address_a[8..0] : input; + address_b[8..0] : input; + addressstall_b : input; + clock0 : input; + clock1 : input; + clocken1 : input; + data_a[15..0] : input; + q_b[15..0] : output; + wren_a : input; +) +VARIABLE + ram_block11a0 : cycloneiii_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "clear1", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "clear1", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block11a1 : cycloneiii_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "clear1", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "clear1", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block11a2 : cycloneiii_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "clear1", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "clear1", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block11a3 : cycloneiii_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "clear1", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "clear1", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block11a4 : cycloneiii_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "clear1", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "clear1", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block11a5 : cycloneiii_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "clear1", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "clear1", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block11a6 : cycloneiii_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "clear1", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "clear1", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block11a7 : cycloneiii_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "clear1", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "clear1", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block11a8 : cycloneiii_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "clear1", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "clear1", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block11a9 : cycloneiii_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "clear1", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "clear1", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block11a10 : cycloneiii_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "clear1", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "clear1", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block11a11 : cycloneiii_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "clear1", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "clear1", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block11a12 : cycloneiii_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "clear1", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "clear1", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 12, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block11a13 : cycloneiii_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "clear1", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "clear1", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 13, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block11a14 : cycloneiii_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "clear1", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "clear1", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 14, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block11a15 : cycloneiii_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "clear1", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "clear1", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 15, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[8..0] : WIRE; + address_b_wire[8..0] : WIRE; + +BEGIN + ram_block11a[15..0].clk0 = clock0; + ram_block11a[15..0].clk1 = clock1; + ram_block11a[15..0].clr1 = aclr1; + ram_block11a[15..0].ena0 = wren_a; + ram_block11a[15..0].ena1 = clocken1; + ram_block11a[15..0].portaaddr[] = ( address_a_wire[8..0]); + ram_block11a[0].portadatain[] = ( data_a[0..0]); + ram_block11a[1].portadatain[] = ( data_a[1..1]); + ram_block11a[2].portadatain[] = ( data_a[2..2]); + ram_block11a[3].portadatain[] = ( data_a[3..3]); + ram_block11a[4].portadatain[] = ( data_a[4..4]); + ram_block11a[5].portadatain[] = ( data_a[5..5]); + ram_block11a[6].portadatain[] = ( data_a[6..6]); + ram_block11a[7].portadatain[] = ( data_a[7..7]); + ram_block11a[8].portadatain[] = ( data_a[8..8]); + ram_block11a[9].portadatain[] = ( data_a[9..9]); + ram_block11a[10].portadatain[] = ( data_a[10..10]); + ram_block11a[11].portadatain[] = ( data_a[11..11]); + ram_block11a[12].portadatain[] = ( data_a[12..12]); + ram_block11a[13].portadatain[] = ( data_a[13..13]); + ram_block11a[14].portadatain[] = ( data_a[14..14]); + ram_block11a[15].portadatain[] = ( data_a[15..15]); + ram_block11a[15..0].portawe = wren_a; + ram_block11a[15..0].portbaddr[] = ( address_b_wire[8..0]); + ram_block11a[15..0].portbaddrstall = addressstall_b; + ram_block11a[15..0].portbre = B"1111111111111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block11a[15..0].portbdataout[0..0]); +END; +--VALID FILE |