blob: 39140c435b8e0f0a49c8075a6707540059c5b494 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
|
-- Catapult University Version: Report
-- ---------------------------- ---------------------------------------------------
-- Version: 2011a.126 Production Release
-- Build Date: Wed Aug 8 00:52:07 PDT 2012
-- Generated by: mg3115@EEWS104A-013
-- Generated date: Tue Mar 08 13:49:35 +0000 2016
Solution Settings: sobel.v1
Current state: schedule
Project: Sobel
Design Input Files Specified
$PROJECT_HOME/sobel.h
$MGC_HOME/shared/include/ac_int.h
$PROJECT_HOME/bmp_io.cpp
$PROJECT_HOME/bmp_io.h
$PROJECT_HOME/tb_blur.cpp
$MGC_HOME/shared/include/mc_testbench.h
$MGC_HOME/shared/include/mc_scverify.h
$MGC_HOME/shared/include/ac_int.h
$PROJECT_HOME/sobel.h
$PROJECT_HOME/bmp_io.h
$PROJECT_HOME/bmp_io.h
$PROJECT_HOME/shift_class.h
$PROJECT_HOME/sobel.cpp
$MGC_HOME/shared/include/ac_fixed.h
$MGC_HOME/shared/include/ac_int.h
$PROJECT_HOME/sobel.h
$PROJECT_HOME/shift_class.h
Processes/Blocks in Design
Process Real Operation(s) count Latency Throughput Reset Length II Comments
------------- ----------------------- ------- ---------- ------------ -- --------
/sobel/core 105 307200 307200 0 1
Design Total: 105 307200 307200 0 0
Clock Information
Clock Signal Edge Period Sharing Alloc (%) Uncertainty Used by Processes/Blocks
------------ ------ ------ ----------------- ----------- ------------------------
clk rising 20.000 20.00 0.000000 /sobel/core
I/O Data Ranges
Port Mode DeclType DeclWidth DeclRange ActType ActWidth ActRange
---------- ---- -------- --------- --------- ------- -------- --------
vin:rsc.z IN Unsigned 90
clk IN Unsigned 1
en IN Unsigned 1
arst_n IN Unsigned 1
vout:rsc.z OUT Unsigned 30
Memory Resources
Resource Name: /sobel/vin:rsc
Memory Component: mgc_in_wire Size: 1 x 90
External: true Packing Mode: sidebyside
Memory Map:
Variable Indices Phys Memory Address
---------- ------- -----------------------
/sobel/vin 0:89 00000000-00000000 (0-0)
Resource Name: /sobel/vout:rsc
Memory Component: mgc_out_stdreg Size: 1 x 30
External: true Packing Mode: sidebyside
Memory Map:
Variable Indices Phys Memory Address
----------- ------- -----------------------
/sobel/vout 0:29 00000000-00000000 (0-0)
Multi-Cycle (Combinational) Component Usage
Instance Component Name Delay
-------- -------------- -----
Loops
Process Loop Iterations C-Steps Total Cycles Duration Unroll Init Comments
----------- ---------------- ---------- ------- ------------- --------- ------ ---- --------
/sobel/core core:rlp Infinite 0 307201 6.14 ms
/sobel/core main Infinite 2 307201 6.14 ms 1
Loop Execution Profile
Process Loop Total Cycles % of Overall Design Cycles Throughput Cycles Comments
----------- ---------------- ------------ -------------------------- ----------------- --------
/sobel/core core:rlp 0 0.00 307200
/sobel/core main 307201 100.00 307200
End of Report
|
