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//------------------------------------------------------------------
// M G C _ I O P O R T _ C O M P S
//------------------------------------------------------------------
//------------------------------------------------------------------
// M O D U L E S
//------------------------------------------------------------------
//------------------------------------------------------------------
//-- INPUT ENTITIES
//------------------------------------------------------------------
module mgc_in_wire (d, z);
parameter integer rscid = 1;
parameter integer width = 8;
output [width-1:0] d;
input [width-1:0] z;
wire [width-1:0] d;
assign d = z;
endmodule
//------------------------------------------------------------------
module mgc_in_wire_en (ld, d, lz, z);
parameter integer rscid = 1;
parameter integer width = 8;
input ld;
output [width-1:0] d;
output lz;
input [width-1:0] z;
wire [width-1:0] d;
wire lz;
assign d = z;
assign lz = ld;
endmodule
//------------------------------------------------------------------
module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
parameter integer rscid = 1;
parameter integer width = 8;
input ld;
output vd;
output [width-1:0] d;
output lz;
input vz;
input [width-1:0] z;
wire vd;
wire [width-1:0] d;
wire lz;
assign d = z;
assign lz = ld;
assign vd = vz;
endmodule
//------------------------------------------------------------------
module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
parameter integer rscid = 1;
parameter integer width = 8;
parameter integer sz_width = 8;
input ld;
output vd;
output [width-1:0] d;
output lz;
input vz;
input [width-1:0] z;
output [sz_width-1:0] size;
input req_size;
input [sz_width-1:0] sizez;
output sizelz;
wire vd;
wire [width-1:0] d;
wire lz;
wire [sz_width-1:0] size;
wire sizelz;
assign d = z;
assign lz = ld;
assign vd = vz;
assign size = sizez;
assign sizelz = req_size;
endmodule
//------------------------------------------------------------------
//-- OUTPUT ENTITIES
//------------------------------------------------------------------
module mgc_out_stdreg (d, z);
parameter integer rscid = 1;
parameter integer width = 8;
input [width-1:0] d;
output [width-1:0] z;
wire [width-1:0] z;
assign z = d;
endmodule
//------------------------------------------------------------------
module mgc_out_stdreg_en (ld, d, lz, z);
parameter integer rscid = 1;
parameter integer width = 8;
input ld;
input [width-1:0] d;
output lz;
output [width-1:0] z;
wire lz;
wire [width-1:0] z;
assign z = d;
assign lz = ld;
endmodule
//------------------------------------------------------------------
module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
parameter integer rscid = 1;
parameter integer width = 8;
input ld;
output vd;
input [width-1:0] d;
output lz;
input vz;
output [width-1:0] z;
wire vd;
wire lz;
wire [width-1:0] z;
assign z = d;
assign lz = ld;
assign vd = vz;
endmodule
//------------------------------------------------------------------
module mgc_out_prereg_en (ld, d, lz, z);
parameter integer rscid = 1;
parameter integer width = 8;
input ld;
input [width-1:0] d;
output lz;
output [width-1:0] z;
wire lz;
wire [width-1:0] z;
assign z = d;
assign lz = ld;
endmodule
//------------------------------------------------------------------
//-- INOUT ENTITIES
//------------------------------------------------------------------
module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
parameter integer rscid = 1;
parameter integer width = 8;
input ldin;
output [width-1:0] din;
input ldout;
input [width-1:0] dout;
output lzin;
output lzout;
inout [width-1:0] z;
wire [width-1:0] din;
wire lzin;
wire lzout;
wire [width-1:0] z;
assign lzin = ldin;
assign din = ldin ? z : {width{1'bz}};
assign lzout = ldout;
assign z = ldout ? dout : {width{1'bz}};
endmodule
//------------------------------------------------------------------
module hid_tribuf( I_SIG, ENABLE, O_SIG);
parameter integer width = 8;
input [width-1:0] I_SIG;
input ENABLE;
inout [width-1:0] O_SIG;
assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
endmodule
//------------------------------------------------------------------
module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
parameter integer rscid = 1;
parameter integer width = 8;
input ldin;
output vdin;
output [width-1:0] din;
input ldout;
output vdout;
input [width-1:0] dout;
output lzin;
input vzin;
output lzout;
input vzout;
inout [width-1:0] z;
wire vdin;
wire [width-1:0] din;
wire vdout;
wire lzin;
wire lzout;
wire [width-1:0] z;
wire ldout_and_vzout;
assign lzin = ldin;
assign vdin = vzin;
assign din = ldin ? z : {width{1'bz}};
assign lzout = ldout;
assign vdout = vzout ;
assign ldout_and_vzout = ldout && vzout ;
hid_tribuf #(width) tb( .I_SIG(dout),
.ENABLE(ldout_and_vzout),
.O_SIG(z) );
endmodule
//------------------------------------------------------------------
module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
parameter integer rscid = 0; // resource ID
parameter integer width = 8; // fifo width
parameter ph_clk = 1'b1; // clock polarity 1=rising edge, 0=falling edge
parameter ph_en = 1'b1; // clock enable polarity
parameter ph_arst = 1'b1; // async reset polarity
parameter ph_srst = 1'b1; // sync reset polarity
input clk;
input en;
input arst;
input srst;
input ldin;
output vdin;
output [width-1:0] din;
input ldout;
output vdout;
input [width-1:0] dout;
output lzin;
input vzin;
output lzout;
input vzout;
inout [width-1:0] z;
wire lzout_buf;
wire vzout_buf;
wire [width-1:0] z_buf;
wire vdin;
wire [width-1:0] din;
wire vdout;
wire lzin;
wire lzout;
wire [width-1:0] z;
assign lzin = ldin;
assign vdin = vzin;
assign din = ldin ? z : {width{1'bz}};
assign lzout = lzout_buf & ~ldin;
assign vzout_buf = vzout & ~ldin;
hid_tribuf #(width) tb( .I_SIG(z_buf),
.ENABLE((lzout_buf && (!ldin) && vzout) ),
.O_SIG(z) );
mgc_out_buf_wait
#(
.rscid (rscid),
.width (width),
.ph_clk (ph_clk),
.ph_en (ph_en),
.ph_arst (ph_arst),
.ph_srst (ph_srst)
)
BUFF
(
.clk (clk),
.en (en),
.arst (arst),
.srst (srst),
.ld (ldout),
.vd (vdout),
.d (dout),
.lz (lzout_buf),
.vz (vzout_buf),
.z (z_buf)
);
endmodule
module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
parameter integer rscid = 0; // resource ID
parameter integer width = 8; // fifo width
parameter integer fifo_sz = 8; // fifo depth
parameter ph_clk = 1'b1; // clock polarity 1=rising edge, 0=falling edge
parameter ph_en = 1'b1; // clock enable polarity
parameter ph_arst = 1'b1; // async reset polarity
parameter ph_srst = 1'b1; // sync reset polarity
parameter integer ph_log2 = 3; // log2(fifo_sz)
parameter integer pwropt = 0; // pwropt
input clk;
input en;
input arst;
input srst;
input ldin;
output vdin;
output [width-1:0] din;
input ldout;
output vdout;
input [width-1:0] dout;
output lzin;
input vzin;
output lzout;
input vzout;
inout [width-1:0] z;
wire lzout_buf;
wire vzout_buf;
wire [width-1:0] z_buf;
wire comb;
wire vdin;
wire [width-1:0] din;
wire vdout;
wire lzin;
wire lzout;
wire [width-1:0] z;
assign lzin = ldin;
assign vdin = vzin;
assign din = ldin ? z : {width{1'bz}};
assign lzout = lzout_buf & ~ldin;
assign vzout_buf = vzout & ~ldin;
assign comb = (lzout_buf && (!ldin) && vzout);
hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z) );
mgc_out_fifo_wait
#(
.rscid (rscid),
.width (width),
.fifo_sz (fifo_sz),
.ph_clk (ph_clk),
.ph_en (ph_en),
.ph_arst (ph_arst),
.ph_srst (ph_srst),
.ph_log2 (ph_log2),
.pwropt (pwropt)
)
FIFO
(
.clk (clk),
.en (en),
.arst (arst),
.srst (srst),
.ld (ldout),
.vd (vdout),
.d (dout),
.lz (lzout_buf),
.vz (vzout_buf),
.z (z_buf)
);
endmodule
//------------------------------------------------------------------
//-- I/O SYNCHRONIZATION ENTITIES
//------------------------------------------------------------------
module mgc_io_sync (ld, lz);
input ld;
output lz;
assign lz = ld;
endmodule
module mgc_bsync_rdy (rd, rz);
parameter integer rscid = 0; // resource ID
parameter ready = 1;
parameter valid = 0;
input rd;
output rz;
wire rz;
assign rz = rd;
endmodule
module mgc_bsync_vld (vd, vz);
parameter integer rscid = 0; // resource ID
parameter ready = 0;
parameter valid = 1;
output vd;
input vz;
wire vd;
assign vd = vz;
endmodule
module mgc_bsync_rv (rd, vd, rz, vz);
parameter integer rscid = 0; // resource ID
parameter ready = 1;
parameter valid = 1;
input rd;
output vd;
output rz;
input vz;
wire vd;
wire rz;
assign rz = rd;
assign vd = vz;
endmodule
//------------------------------------------------------------------
module mgc_sync (ldin, vdin, ldout, vdout);
input ldin;
output vdin;
input ldout;
output vdout;
wire vdin;
wire vdout;
assign vdin = ldout;
assign vdout = ldin;
endmodule
///////////////////////////////////////////////////////////////////////////////
// dummy function used to preserve funccalls for modulario
// it looks like a memory read to the caller
///////////////////////////////////////////////////////////////////////////////
module funccall_inout (d, ad, bd, z, az, bz);
parameter integer ram_id = 1;
parameter integer width = 8;
parameter integer addr_width = 8;
output [width-1:0] d;
input [addr_width-1:0] ad;
input bd;
input [width-1:0] z;
output [addr_width-1:0] az;
output bz;
wire [width-1:0] d;
wire [addr_width-1:0] az;
wire bz;
assign d = z;
assign az = ad;
assign bz = bd;
endmodule
///////////////////////////////////////////////////////////////////////////////
// inlinable modular io not otherwise found in mgc_ioport
///////////////////////////////////////////////////////////////////////////////
module modulario_en_in (vd, d, vz, z);
parameter integer rscid = 1;
parameter integer width = 8;
output vd;
output [width-1:0] d;
input vz;
input [width-1:0] z;
wire [width-1:0] d;
wire vd;
assign d = z;
assign vd = vz;
endmodule
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