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--dffpipe DELAY=1 WIDTH=10 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 13.0 cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = reg 10
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";
SUBDESIGN dffpipe_oe9
(
clock : input;
clrn : input;
d[9..0] : input;
q[9..0] : output;
)
VARIABLE
dffe12a[9..0] : dffe;
ena : NODE;
prn : NODE;
sclr : NODE;
BEGIN
dffe12a[].clk = clock;
dffe12a[].clrn = clrn;
dffe12a[].d = (d[] & (! sclr));
dffe12a[].ena = ena;
dffe12a[].prn = prn;
ena = VCC;
prn = VCC;
q[] = dffe12a[].q;
sclr = GND;
END;
--VALID FILE
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