path: root/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/prev_cmp_DE0_D5M.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1457452784979 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457452784986 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:59:44 2016 " "Processing started: Tue Mar 08 15:59:44 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457452784986 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1457452784986 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M " "Command: quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1457452784986 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1457452789888 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "//icnas3.cc.ic.ac.uk/mg3115/eie1 fpga/sobel filter catapult/sobel/sobel quartus/sobel.v 2 2 " "Found 2 design units, including 2 entities, in source file //icnas3.cc.ic.ac.uk/mg3115/eie1 fpga/sobel filter catapult/sobel/sobel quartus/sobel.v" { { "Info" "ISGN_ENTITY_NAME" "1 sobel_core " "Found entity 1: sobel_core" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790217 ""} { "Info" "ISGN_ENTITY_NAME" "2 sobel " "Found entity 2: sobel" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 876 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790217 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790217 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/ps2.v 1 1 " "Found 1 design units, including 1 entities, in source file v/ps2.v" { { "Info" "ISGN_ENTITY_NAME" "1 ps2 " "Found entity 1: ps2" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790263 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790263 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/command.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/command.v" { { "Info" "ISGN_ENTITY_NAME" "1 command " "Found entity 1: command" {  } { { "Sdram_Control_4Port/command.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790325 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790325 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/control_interface.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/control_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_interface " "Found entity 1: control_interface" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790370 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790370 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 sdr_data_path.v(68) " "Verilog HDL Expression warning at sdr_data_path.v(68): truncated literal to match 1 bits" {  } { { "Sdram_Control_4Port/sdr_data_path.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v" 68 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1457452790412 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/sdr_data_path.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/sdr_data_path.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdr_data_path " "Found entity 1: sdr_data_path" {  } { { "Sdram_Control_4Port/sdr_data_path.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790414 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790414 ""}
{ "Warning" "WVRFX_VERI_IGNORED_ANONYMOUS_PORT" "Sdram_Control_4Port Sdram_Control_4Port.v(90) " "Verilog Module Declaration warning at Sdram_Control_4Port.v(90): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"Sdram_Control_4Port\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 90 0 0 } }  } 0 10238 "Verilog Module Declaration warning at %2!s!: ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452790460 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/sdram_control_4port.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_control_4port.v" { { "Info" "ISGN_ENTITY_NAME" "1 Sdram_Control_4Port " "Found entity 1: Sdram_Control_4Port" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790462 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790462 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/sdram_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 Sdram_FIFO " "Found entity 1: Sdram_FIFO" {  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790494 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790494 ""}
{ "Warning" "WSGN_FILE_IS_MISSING" "V/async_receiver.v " "Can't analyze file -- file V/async_receiver.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1457452790562 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/ccd_capture.v 1 1 " "Found 1 design units, including 1 entities, in source file v/ccd_capture.v" { { "Info" "ISGN_ENTITY_NAME" "1 CCD_Capture " "Found entity 1: CCD_Capture" {  } { { "V/CCD_Capture.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790606 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790606 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/i2c_ccd_config.v 1 1 " "Found 1 design units, including 1 entities, in source file v/i2c_ccd_config.v" { { "Info" "ISGN_ENTITY_NAME" "1 I2C_CCD_Config " "Found entity 1: I2C_CCD_Config" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790639 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790639 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/i2c_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file v/i2c_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 I2C_Controller " "Found entity 1: I2C_Controller" {  } { { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790677 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790677 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/line_buffer.v 1 1 " "Found 1 design units, including 1 entities, in source file v/line_buffer.v" { { "Info" "ISGN_ENTITY_NAME" "1 Line_Buffer " "Found entity 1: Line_Buffer" {  } { { "V/Line_Buffer.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790719 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790719 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/raw2rgb.v 1 1 " "Found 1 design units, including 1 entities, in source file v/raw2rgb.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAW2RGB " "Found entity 1: RAW2RGB" {  } { { "V/RAW2RGB.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790765 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790765 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/reset_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file v/reset_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 Reset_Delay " "Found entity 1: Reset_Delay" {  } { { "V/Reset_Delay.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790803 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790803 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/sdram_pll.v 1 1 " "Found 1 design units, including 1 entities, in source file v/sdram_pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_pll " "Found entity 1: sdram_pll" {  } { { "V/sdram_pll.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790840 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790840 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/seg7_lut.v 1 1 " "Found 1 design units, including 1 entities, in source file v/seg7_lut.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT " "Found entity 1: SEG7_LUT" {  } { { "V/SEG7_LUT.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790881 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790881 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/seg7_lut_8.v 1 1 " "Found 1 design units, including 1 entities, in source file v/seg7_lut_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT_8 " "Found entity 1: SEG7_LUT_8" {  } { { "V/SEG7_LUT_8.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790915 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790915 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/vga_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file v/vga_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 VGA_Controller " "Found entity 1: VGA_Controller" {  } { { "V/VGA_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 13 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790969 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790969 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "de0_d5m.v 1 1 " "Found 1 design units, including 1 entities, in source file de0_d5m.v" { { "Info" "ISGN_ENTITY_NAME" "1 DE0_D5M " "Found entity 1: DE0_D5M" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791035 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452791035 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/top_de0_camera_mouse.bdf 1 1 " "Found 1 design units, including 1 entities, in source file v/top_de0_camera_mouse.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 TOP_DE0_CAMERA_MOUSE " "Found entity 1: TOP_DE0_CAMERA_MOUSE" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791129 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452791129 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_mux.vhd 2 1 " "Found 2 design units, including 1 entities, in source file vga_mux.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vga_mux-SYN " "Found design unit 1: vga_mux-SYN" {  } { { "vga_mux.vhd" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 55 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791878 ""} { "Info" "ISGN_ENTITY_NAME" "1 vga_mux " "Found entity 1: vga_mux" {  } { { "vga_mux.vhd" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791878 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452791878 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "catapult_ip/mouse/rtl_mgc_ioport_v2001.v 7 7 " "Found 7 design units, including 7 entities, in source file catapult_ip/mouse/rtl_mgc_ioport_v2001.v" { { "Info" "ISGN_ENTITY_NAME" "1 mgc_out_reg_pos " "Found entity 1: mgc_out_reg_pos" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791911 ""} { "Info" "ISGN_ENTITY_NAME" "2 mgc_out_reg_neg " "Found entity 2: mgc_out_reg_neg" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 68 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791911 ""} { "Info" "ISGN_ENTITY_NAME" "3 mgc_out_reg " "Found entity 3: mgc_out_reg" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 133 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791911 ""} { "Info" "ISGN_ENTITY_NAME" "4 mgc_out_buf_wait " "Found entity 4: mgc_out_buf_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 210 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791911 ""} { "Info" "ISGN_ENTITY_NAME" "5 mgc_out_fifo_wait " "Found entity 5: mgc_out_fifo_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 296 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791911 ""} { "Info" "ISGN_ENTITY_NAME" "6 mgc_out_fifo_wait_core " "Found entity 6: mgc_out_fifo_wait_core" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 353 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791911 ""} { "Info" "ISGN_ENTITY_NAME" "7 mgc_pipe " "Found entity 7: mgc_pipe" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 644 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791911 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452791911 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "catapult_ip/mouse/rtl_mgc_ioport.v 20 20 " "Found 20 design units, including 20 entities, in source file catapult_ip/mouse/rtl_mgc_ioport.v" { { "Info" "ISGN_ENTITY_NAME" "1 mgc_in_wire " "Found entity 1: mgc_in_wire" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 13 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "2 mgc_in_wire_en " "Found entity 2: mgc_in_wire_en" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 29 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "3 mgc_in_wire_wait " "Found entity 3: mgc_in_wire_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "4 mgc_chan_in " "Found entity 4: mgc_chan_in" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 72 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "5 mgc_out_stdreg " "Found entity 5: mgc_out_stdreg" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 109 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "6 mgc_out_stdreg_en " "Found entity 6: mgc_out_stdreg_en" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 125 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "7 mgc_out_stdreg_wait " "Found entity 7: mgc_out_stdreg_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 145 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "8 mgc_out_prereg_en " "Found entity 8: mgc_out_prereg_en" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 169 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "9 mgc_inout_stdreg_en " "Found entity 9: mgc_inout_stdreg_en" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 191 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "10 hid_tribuf " "Found entity 10: hid_tribuf" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 217 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "11 mgc_inout_stdreg_wait " "Found entity 11: mgc_inout_stdreg_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 229 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "12 mgc_inout_buf_wait " "Found entity 12: mgc_inout_buf_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 269 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "13 mgc_inout_fifo_wait " "Found entity 13: mgc_inout_fifo_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 339 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "14 mgc_io_sync " "Found entity 14: mgc_io_sync" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 419 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "15 mgc_bsync_rdy " "Found entity 15: mgc_bsync_rdy" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 428 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "16 mgc_bsync_vld " "Found entity 16: mgc_bsync_vld" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 443 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "17 mgc_bsync_rv " "Found entity 17: mgc_bsync_rv" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 458 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "18 mgc_sync " "Found entity 18: mgc_sync" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 479 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "19 funccall_inout " "Found entity 19: funccall_inout" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 498 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "20 modulario_en_in " "Found entity 20: modulario_en_in" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 526 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "catapult_ip/mouse/rtl.v 2 2 " "Found 2 design units, including 2 entities, in source file catapult_ip/mouse/rtl.v" { { "Info" "ISGN_ENTITY_NAME" "1 vga_mouse_square_core " "Found entity 1: vga_mouse_square_core" {  } { { "catapult_ip/mouse/rtl.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792483 ""} { "Info" "ISGN_ENTITY_NAME" "2 vga_mouse_square " "Found entity 2: vga_mouse_square" {  } { { "catapult_ip/mouse/rtl.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 110 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792483 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452792483 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "TOP_DE0_CAMERA_MOUSE " "Elaborating entity \"TOP_DE0_CAMERA_MOUSE\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1457452795467 ""}
{ "Warning" "WGDFX_NO_SUPERSET_FOUND" "" "No superset bus at connection" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 912 1008 1120 928 "MOUSE_X\[1..0\]" "" } { 928 1008 1120 944 "MOUSE_Y\[1..0\]" "" } { 928 1008 1008 944 "" "" } { 944 1008 1008 952 "" "" } } } }  } 0 275002 "No superset bus at connection" 0 0 "Quartus II" 0 -1 1457452795479 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DE0_D5M DE0_D5M:inst " "Elaborating entity \"DE0_D5M\" for hierarchy \"DE0_D5M:inst\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "inst" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 64 760 1048 560 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795505 ""}
{ "Critical Warning" "WVRFX_VERI_PORT_DECLARED_WITH_DIFFERENT_RANGE" "VGA_R DE0_D5M.v(118) " "Verilog HDL warning at DE0_D5M.v(118): the port and data declarations for array port \"VGA_R\" do not specify the same range for each dimension" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 118 0 0 } }  } 1 10169 "Verilog HDL warning at %2!s!: the port and data declarations for array port \"%1!s!\" do not specify the same range for each dimension" 0 0 "Quartus II" 0 -1 1457452795520 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
{ "Warning" "WVRFX_HDL_SEE_DECLARATION" "VGA_R DE0_D5M.v(166) " "HDL warning at DE0_D5M.v(166): see declaration for object \"VGA_R\"" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 166 0 0 } }  } 0 10359 "HDL warning at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452795520 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
{ "Critical Warning" "WVRFX_VERI_PORT_DECLARED_WITH_DIFFERENT_RANGE" "VGA_G DE0_D5M.v(119) " "Verilog HDL warning at DE0_D5M.v(119): the port and data declarations for array port \"VGA_G\" do not specify the same range for each dimension" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 119 0 0 } }  } 1 10169 "Verilog HDL warning at %2!s!: the port and data declarations for array port \"%1!s!\" do not specify the same range for each dimension" 0 0 "Quartus II" 0 -1 1457452795520 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
{ "Warning" "WVRFX_HDL_SEE_DECLARATION" "VGA_G DE0_D5M.v(167) " "HDL warning at DE0_D5M.v(167): see declaration for object \"VGA_G\"" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 167 0 0 } }  } 0 10359 "HDL warning at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452795521 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
{ "Critical Warning" "WVRFX_VERI_PORT_DECLARED_WITH_DIFFERENT_RANGE" "VGA_B DE0_D5M.v(120) " "Verilog HDL warning at DE0_D5M.v(120): the port and data declarations for array port \"VGA_B\" do not specify the same range for each dimension" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 120 0 0 } }  } 1 10169 "Verilog HDL warning at %2!s!: the port and data declarations for array port \"%1!s!\" do not specify the same range for each dimension" 0 0 "Quartus II" 0 -1 1457452795521 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
{ "Warning" "WVRFX_HDL_SEE_DECLARATION" "VGA_B DE0_D5M.v(168) " "HDL warning at DE0_D5M.v(168): see declaration for object \"VGA_B\"" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 168 0 0 } }  } 0 10359 "HDL warning at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452795521 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "16 10 DE0_D5M.v(197) " "Verilog HDL assignment warning at DE0_D5M.v(197): truncated value with size 16 to match size of target (10)" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 197 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795521 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 DE0_D5M.v(202) " "Verilog HDL assignment warning at DE0_D5M.v(202): truncated value with size 32 to match size of target (2)" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 202 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795522 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "GPIO_1_CLKOUT\[1\] DE0_D5M.v(128) " "Output port \"GPIO_1_CLKOUT\[1\]\" at DE0_D5M.v(128) has no driver" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 128 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1457452795522 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGA_Controller DE0_D5M:inst\|VGA_Controller:u1 " "Elaborating entity \"VGA_Controller\" for hierarchy \"DE0_D5M:inst\|VGA_Controller:u1\"" {  } { { "DE0_D5M.v" "u1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 253 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795550 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(70) " "Verilog HDL assignment warning at VGA_Controller.v(70): truncated value with size 32 to match size of target (10)" {  } { { "V/VGA_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 70 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795562 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(73) " "Verilog HDL assignment warning at VGA_Controller.v(73): truncated value with size 32 to match size of target (10)" {  } { { "V/VGA_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795564 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(76) " "Verilog HDL assignment warning at VGA_Controller.v(76): truncated value with size 32 to match size of target (10)" {  } { { "V/VGA_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 76 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795564 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 VGA_Controller.v(115) " "Verilog HDL assignment warning at VGA_Controller.v(115): truncated value with size 32 to match size of target (12)" {  } { { "V/VGA_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 115 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795564 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 VGA_Controller.v(146) " "Verilog HDL assignment warning at VGA_Controller.v(146): truncated value with size 32 to match size of target (12)" {  } { { "V/VGA_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 146 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795564 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reset_Delay DE0_D5M:inst\|Reset_Delay:u2 " "Elaborating entity \"Reset_Delay\" for hierarchy \"DE0_D5M:inst\|Reset_Delay:u2\"" {  } { { "DE0_D5M.v" "u2" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 262 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795594 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CCD_Capture DE0_D5M:inst\|CCD_Capture:u3 " "Elaborating entity \"CCD_Capture\" for hierarchy \"DE0_D5M:inst\|CCD_Capture:u3\"" {  } { { "DE0_D5M.v" "u3" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 277 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795627 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ifval_fedge CCD_Capture.v(162) " "Verilog HDL or VHDL warning at CCD_Capture.v(162): object \"ifval_fedge\" assigned a value but never read" {  } { { "V/CCD_Capture.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 162 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1457452795641 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "y_cnt_d CCD_Capture.v(163) " "Verilog HDL or VHDL warning at CCD_Capture.v(163): object \"y_cnt_d\" assigned a value but never read" {  } { { "V/CCD_Capture.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 163 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1457452795642 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 CCD_Capture.v(123) " "Verilog HDL assignment warning at CCD_Capture.v(123): truncated value with size 32 to match size of target (16)" {  } { { "V/CCD_Capture.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 123 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795642 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 CCD_Capture.v(127) " "Verilog HDL assignment warning at CCD_Capture.v(127): truncated value with size 32 to match size of target (16)" {  } { { "V/CCD_Capture.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 127 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795643 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 CCD_Capture.v(183) " "Verilog HDL assignment warning at CCD_Capture.v(183): truncated value with size 32 to match size of target (1)" {  } { { "V/CCD_Capture.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 183 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795643 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAW2RGB DE0_D5M:inst\|RAW2RGB:u4 " "Elaborating entity \"RAW2RGB\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\"" {  } { { "DE0_D5M.v" "u4" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 290 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795668 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Line_Buffer DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0 " "Elaborating entity \"Line_Buffer\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\"" {  } { { "V/RAW2RGB.v" "u0" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v" 83 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795760 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift_taps DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component " "Elaborating entity \"altshift_taps\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\"" {  } { { "V/Line_Buffer.v" "altshift_taps_component" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v" 67 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795938 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component " "Elaborated megafunction instantiation \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\"" {  } { { "V/Line_Buffer.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v" 67 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452795953 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component " "Instantiated megafunction \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altshift_taps " "Parameter \"lpm_type\" = \"altshift_taps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795964 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_taps 2 " "Parameter \"number_of_taps\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795964 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "tap_distance 1280 " "Parameter \"tap_distance\" = \"1280\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795964 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width 12 " "Parameter \"width\" = \"12\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795964 ""}  } { { "V/Line_Buffer.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v" 67 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457452795964 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/shift_taps_rnn.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/shift_taps_rnn.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 shift_taps_rnn " "Found entity 1: shift_taps_rnn" {  } { { "db/shift_taps_rnn.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452796127 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452796127 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_taps_rnn DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated " "Elaborating entity \"shift_taps_rnn\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\"" {  } { { "altshift_taps.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452796143 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_lp81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_lp81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_lp81 " "Found entity 1: altsyncram_lp81" {  } { { "db/altsyncram_lp81.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_lp81.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452796356 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452796356 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_lp81 DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|altsyncram_lp81:altsyncram2 " "Elaborating entity \"altsyncram_lp81\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|altsyncram_lp81:altsyncram2\"" {  } { { "db/shift_taps_rnn.tdf" "altsyncram2" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf" 35 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452796371 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_cuf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_cuf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_cuf " "Found entity 1: cntr_cuf" {  } { { "db/cntr_cuf.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_cuf.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452796527 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452796527 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_cuf DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|cntr_cuf:cntr1 " "Elaborating entity \"cntr_cuf\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|cntr_cuf:cntr1\"" {  } { { "db/shift_taps_rnn.tdf" "cntr1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf" 36 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452796544 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_vgc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_vgc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_vgc " "Found entity 1: cmpr_vgc" {  } { { "db/cmpr_vgc.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_vgc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452796691 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452796691 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_vgc DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|cntr_cuf:cntr1\|cmpr_vgc:cmpr4 " "Elaborating entity \"cmpr_vgc\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|cntr_cuf:cntr1\|cmpr_vgc:cmpr4\"" {  } { { "db/cntr_cuf.tdf" "cmpr4" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_cuf.tdf" 90 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452796707 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT_8 DE0_D5M:inst\|SEG7_LUT_8:u5 " "Elaborating entity \"SEG7_LUT_8\" for hierarchy \"DE0_D5M:inst\|SEG7_LUT_8:u5\"" {  } { { "DE0_D5M.v" "u5" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 302 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452796745 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT DE0_D5M:inst\|SEG7_LUT_8:u5\|SEG7_LUT:u0 " "Elaborating entity \"SEG7_LUT\" for hierarchy \"DE0_D5M:inst\|SEG7_LUT_8:u5\|SEG7_LUT:u0\"" {  } { { "V/SEG7_LUT_8.v" "u0" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v" 47 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452796774 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_pll DE0_D5M:inst\|sdram_pll:u6 " "Elaborating entity \"sdram_pll\" for hierarchy \"DE0_D5M:inst\|sdram_pll:u6\"" {  } { { "DE0_D5M.v" "u6" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 308 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452796986 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\"" {  } { { "V/sdram_pll.v" "altpll_component" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 94 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797174 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component " "Elaborated megafunction instantiation \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\"" {  } { { "V/sdram_pll.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 94 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component " "Instantiated megafunction \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2 " "Parameter \"clk0_divide_by\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 5 " "Parameter \"clk0_multiply_by\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 2 " "Parameter \"clk1_divide_by\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 5 " "Parameter \"clk1_multiply_by\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift -2600 " "Parameter \"clk1_phase_shift\" = \"-2600\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone III " "Parameter \"intended_device_family\" = \"Cyclone III\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""}  } { { "V/sdram_pll.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 94 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457452797193 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altpll_9ee2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altpll_9ee2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll_9ee2 " "Found entity 1: altpll_9ee2" {  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452797369 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452797369 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll_9ee2 DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated " "Elaborating entity \"altpll_9ee2\" for hierarchy \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\"" {  } { { "altpll.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797383 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Sdram_Control_4Port DE0_D5M:inst\|Sdram_Control_4Port:u7 " "Elaborating entity \"Sdram_Control_4Port\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\"" {  } { { "DE0_D5M.v" "u7" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 364 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797430 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 Sdram_Control_4Port.v(385) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(385): truncated value with size 32 to match size of target (10)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 385 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452797454 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(431) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(431): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 431 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452797454 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(432) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(432): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 432 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452797455 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(433) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(433): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 433 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452797456 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(434) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(434): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 434 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452797456 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rWR1_MAX_ADDR Sdram_Control_4Port.v(423) " "Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable \"rWR1_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457452797456 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rWR2_MAX_ADDR Sdram_Control_4Port.v(423) " "Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable \"rWR2_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457452797456 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rRD1_MAX_ADDR Sdram_Control_4Port.v(423) " "Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable \"rRD1_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457452797457 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rRD2_MAX_ADDR Sdram_Control_4Port.v(423) " "Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable \"rRD2_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457452797458 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[0\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797458 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[1\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797458 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[2\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797459 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[3\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797459 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[4\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797459 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[5\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797459 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[6\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797460 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[7\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797460 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[8\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797460 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[9\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797461 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[10\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797461 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[11\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797461 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[12\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797461 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[13\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797462 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[14\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797462 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[15\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797462 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[16\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797463 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[17\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797463 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[18\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797463 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[19\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797463 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[20\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797464 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[21\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797464 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[22\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797464 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[0\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797465 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[1\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797465 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[2\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797465 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[3\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797465 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[4\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797465 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[5\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797467 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[6\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797467 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[7\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797467 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[8\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797467 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[9\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797467 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[10\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797467 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[11\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797468 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[12\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797469 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[13\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797469 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[14\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797469 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[15\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797469 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[16\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797469 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[17\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797470 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[18\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797470 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[19\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797471 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[20\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797471 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[21\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797471 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[22\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797471 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[0\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797471 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[1\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797471 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[2\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797472 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[3\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797473 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[4\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797473 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[5\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797473 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[6\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797473 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[7\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797473 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[8\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797473 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[9\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797474 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[10\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797474 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[11\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797475 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[12\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797475 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[13\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797475 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[14\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797475 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[15\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797475 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[16\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797476 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[17\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797476 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[18\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797477 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[19\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797477 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[20\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797477 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[21\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797477 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[22\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797477 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[0\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797477 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[1\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797478 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[2\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797479 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[3\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797479 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[4\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797479 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[5\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797479 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[6\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797479 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[7\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797479 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[8\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797480 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[9\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797480 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[10\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797481 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[11\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797481 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[12\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797481 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[13\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797481 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[14\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797481 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[15\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797482 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[16\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797482 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[17\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797483 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[18\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797483 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[19\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797483 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[20\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797483 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[21\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797483 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[22\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797483 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_interface DE0_D5M:inst\|Sdram_Control_4Port:u7\|control_interface:control1 " "Elaborating entity \"control_interface\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|control_interface:control1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "control1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 237 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797505 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 control_interface.v(162) " "Verilog HDL assignment warning at control_interface.v(162): truncated value with size 32 to match size of target (16)" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v" 162 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452797522 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 control_interface.v(167) " "Verilog HDL assignment warning at control_interface.v(167): truncated value with size 32 to match size of target (16)" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v" 167 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452797522 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 control_interface.v(192) " "Verilog HDL assignment warning at control_interface.v(192): truncated value with size 32 to match size of target (16)" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v" 192 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452797522 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "command DE0_D5M:inst\|Sdram_Control_4Port:u7\|command:command1 " "Elaborating entity \"command\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|command:command1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "command1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 263 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797544 ""}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "oe_shift command.v(275) " "Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable \"oe_shift\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/command.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v" 275 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457452797555 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "oe1 command.v(275) " "Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable \"oe1\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/command.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v" 275 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457452797555 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "oe2 command.v(275) " "Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable \"oe2\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/command.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v" 275 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457452797557 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdr_data_path DE0_D5M:inst\|Sdram_Control_4Port:u7\|sdr_data_path:data_path1 " "Elaborating entity \"sdr_data_path\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|sdr_data_path:data_path1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "data_path1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 272 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797578 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 sdr_data_path.v(68) " "Verilog HDL assignment warning at sdr_data_path.v(68): truncated value with size 32 to match size of target (2)" {  } { { "Sdram_Control_4Port/sdr_data_path.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v" 68 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452797585 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Sdram_FIFO DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1 " "Elaborating entity \"Sdram_FIFO\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "write_fifo1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 283 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797664 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component " "Elaborating entity \"dcfifo\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\"" {  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "dcfifo_component" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797913 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component " "Elaborated megafunction instantiation \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\"" {  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452797920 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component " "Instantiated megafunction \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register OFF " "Parameter \"add_ram_output_register\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clocks_are_synchronized FALSE " "Parameter \"clocks_are_synchronized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone " "Parameter \"intended_device_family\" = \"Cyclone\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=M4K " "Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=M4K\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 512 " "Parameter \"lpm_numwords\" = \"512\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type dcfifo " "Parameter \"lpm_type\" = \"dcfifo\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 16 " "Parameter \"lpm_width\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 9 " "Parameter \"lpm_widthu\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Parameter \"overflow_checking\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Parameter \"underflow_checking\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""}  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457452797921 ""}
{ "Warning" "WTDFX_ASSERTION" "Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2 " "Assertion warning: Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2" {  } { { "db/dcfifo_v5o1.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 161 2 0 } }  } 0 287001 "Assertion warning: %1!s!" 0 0 "Quartus II" 0 -1 1457452798118 ""}
{ "Warning" "WTDFX_ASSERTION" "Device family Cyclone III does not have M4K blocks -- using available memory blocks " "Assertion warning: Device family Cyclone III does not have M4K blocks -- using available memory blocks" {  } { { "db/dcfifo_v5o1.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 164 2 0 } }  } 0 287001 "Assertion warning: %1!s!" 0 0 "Quartus II" 0 -1 1457452798119 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dcfifo_v5o1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dcfifo_v5o1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dcfifo_v5o1 " "Found entity 1: dcfifo_v5o1" {  } { { "db/dcfifo_v5o1.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 40 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452798124 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452798124 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo_v5o1 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated " "Elaborating entity \"dcfifo_v5o1\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\"" {  } { { "dcfifo.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/dcfifo.tdf" 188 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452798145 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_gray2bin_tgb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_gray2bin_tgb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_gray2bin_tgb " "Found entity 1: a_gray2bin_tgb" {  } { { "db/a_gray2bin_tgb.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_gray2bin_tgb.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452798276 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452798276 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_gray2bin_tgb DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_gray2bin_tgb:rdptr_g_gray2bin " "Elaborating entity \"a_gray2bin_tgb\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_gray2bin_tgb:rdptr_g_gray2bin\"" {  } { { "db/dcfifo_v5o1.tdf" "rdptr_g_gray2bin" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 55 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452798294 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_s57.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_graycounter_s57.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_s57 " "Found entity 1: a_graycounter_s57" {  } { { "db/a_graycounter_s57.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452798508 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452798508 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_graycounter_s57 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_graycounter_s57:rdptr_g1p " "Elaborating entity \"a_graycounter_s57\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_graycounter_s57:rdptr_g1p\"" {  } { { "db/dcfifo_v5o1.tdf" "rdptr_g1p" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 59 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452798523 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_ojc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_graycounter_ojc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_ojc " "Found entity 1: a_graycounter_ojc" {  } { { "db/a_graycounter_ojc.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452798671 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452798671 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_graycounter_ojc DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_graycounter_ojc:wrptr_g1p " "Elaborating entity \"a_graycounter_ojc\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_graycounter_ojc:wrptr_g1p\"" {  } { { "db/dcfifo_v5o1.tdf" "wrptr_g1p" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 60 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452798686 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_de51.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_de51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_de51 " "Found entity 1: altsyncram_de51" {  } { { "db/altsyncram_de51.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452798866 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452798866 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_de51 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram " "Elaborating entity \"altsyncram_de51\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\"" {  } { { "db/dcfifo_v5o1.tdf" "fifo_ram" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 61 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452798884 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_oe9.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_oe9 " "Found entity 1: dffpipe_oe9" {  } { { "db/dffpipe_oe9.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_oe9.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452799021 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452799021 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_oe9 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|dffpipe_oe9:rs_brp " "Elaborating entity \"dffpipe_oe9\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|dffpipe_oe9:rs_brp\"" {  } { { "db/dcfifo_v5o1.tdf" "rs_brp" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 68 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452799043 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_synch_pipe_qld.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_qld.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_synch_pipe_qld " "Found entity 1: alt_synch_pipe_qld" {  } { { "db/alt_synch_pipe_qld.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_qld.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452799171 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452799171 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_synch_pipe_qld DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_qld:rs_dgwp " "Elaborating entity \"alt_synch_pipe_qld\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_qld:rs_dgwp\"" {  } { { "db/dcfifo_v5o1.tdf" "rs_dgwp" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 70 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452799187 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_pe9.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_pe9 " "Found entity 1: dffpipe_pe9" {  } { { "db/dffpipe_pe9.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_pe9.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452799299 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452799299 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_pe9 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_qld:rs_dgwp\|dffpipe_pe9:dffpipe13 " "Elaborating entity \"dffpipe_pe9\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_qld:rs_dgwp\|dffpipe_pe9:dffpipe13\"" {  } { { "db/alt_synch_pipe_qld.tdf" "dffpipe13" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_qld.tdf" 34 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452799324 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_synch_pipe_rld.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_rld.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_synch_pipe_rld " "Found entity 1: alt_synch_pipe_rld" {  } { { "db/alt_synch_pipe_rld.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_rld.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452799499 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452799499 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_synch_pipe_rld DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_rld:ws_dgrp " "Elaborating entity \"alt_synch_pipe_rld\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_rld:ws_dgrp\"" {  } { { "db/dcfifo_v5o1.tdf" "ws_dgrp" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 73 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452799518 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_qe9.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_qe9 " "Found entity 1: dffpipe_qe9" {  } { { "db/dffpipe_qe9.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_qe9.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452799618 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452799618 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_qe9 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_rld:ws_dgrp\|dffpipe_qe9:dffpipe16 " "Elaborating entity \"dffpipe_qe9\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_rld:ws_dgrp\|dffpipe_qe9:dffpipe16\"" {  } { { "db/alt_synch_pipe_rld.tdf" "dffpipe16" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_rld.tdf" 34 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452799635 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_e66.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_e66.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_e66 " "Found entity 1: cmpr_e66" {  } { { "db/cmpr_e66.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_e66.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452799802 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452799802 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_e66 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|cmpr_e66:rdempty_eq_comp " "Elaborating entity \"cmpr_e66\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|cmpr_e66:rdempty_eq_comp\"" {  } { { "db/dcfifo_v5o1.tdf" "rdempty_eq_comp" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 80 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452799822 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I2C_CCD_Config DE0_D5M:inst\|I2C_CCD_Config:u8 " "Elaborating entity \"I2C_CCD_Config\" for hierarchy \"DE0_D5M:inst\|I2C_CCD_Config:u8\"" {  } { { "DE0_D5M.v" "u8" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 377 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452802897 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_CCD_Config.v(126) " "Verilog HDL assignment warning at I2C_CCD_Config.v(126): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 126 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452802922 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_CCD_Config.v(127) " "Verilog HDL assignment warning at I2C_CCD_Config.v(127): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 127 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452802923 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 25 I2C_CCD_Config.v(160) " "Verilog HDL assignment warning at I2C_CCD_Config.v(160): truncated value with size 32 to match size of target (25)" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 160 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452802924 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_CCD_Config.v(165) " "Verilog HDL assignment warning at I2C_CCD_Config.v(165): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 165 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452802924 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 I2C_CCD_Config.v(190) " "Verilog HDL assignment warning at I2C_CCD_Config.v(190): truncated value with size 32 to match size of target (16)" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 190 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452802924 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 I2C_CCD_Config.v(240) " "Verilog HDL assignment warning at I2C_CCD_Config.v(240): truncated value with size 32 to match size of target (6)" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 240 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452802924 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I2C_Controller DE0_D5M:inst\|I2C_CCD_Config:u8\|I2C_Controller:u0 " "Elaborating entity \"I2C_Controller\" for hierarchy \"DE0_D5M:inst\|I2C_CCD_Config:u8\|I2C_Controller:u0\"" {  } { { "V/I2C_CCD_Config.v" "u0" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 207 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452802956 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_Controller.v(70) " "Verilog HDL assignment warning at I2C_Controller.v(70): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 70 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452802973 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_Controller.v(69) " "Verilog HDL assignment warning at I2C_Controller.v(69): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 69 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452802974 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 I2C_Controller.v(82) " "Verilog HDL assignment warning at I2C_Controller.v(82): truncated value with size 32 to match size of target (7)" {  } { { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 82 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452802975 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2 ps2:inst6 " "Elaborating entity \"ps2\" for hierarchy \"ps2:inst6\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "inst6" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 704 760 968 944 "inst6" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803003 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 ps2.v(120) " "Verilog HDL assignment warning at ps2.v(120): truncated value with size 32 to match size of target (9)" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 120 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452803016 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 ps2.v(188) " "Verilog HDL assignment warning at ps2.v(188): truncated value with size 32 to match size of target (8)" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 188 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452803016 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2.v(195) " "Verilog HDL assignment warning at ps2.v(195): truncated value with size 32 to match size of target (1)" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 195 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452803016 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 ps2.v(201) " "Verilog HDL assignment warning at ps2.v(201): truncated value with size 32 to match size of target (6)" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 201 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452803016 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ps2.v(229) " "Verilog HDL assignment warning at ps2.v(229): truncated value with size 32 to match size of target (4)" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 229 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452803017 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ps2.v(245) " "Verilog HDL assignment warning at ps2.v(245): truncated value with size 32 to match size of target (4)" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 245 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452803017 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_mux vga_mux:inst10 " "Elaborating entity \"vga_mux\" for hierarchy \"vga_mux:inst10\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "inst10" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 1056 2304 2448 1168 "inst10" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803124 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_MUX vga_mux:inst10\|LPM_MUX:LPM_MUX_component " "Elaborating entity \"LPM_MUX\" for hierarchy \"vga_mux:inst10\|LPM_MUX:LPM_MUX_component\"" {  } { { "vga_mux.vhd" "LPM_MUX_component" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 193 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803262 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "vga_mux:inst10\|LPM_MUX:LPM_MUX_component " "Elaborated megafunction instantiation \"vga_mux:inst10\|LPM_MUX:LPM_MUX_component\"" {  } { { "vga_mux.vhd" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 193 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452803271 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "vga_mux:inst10\|LPM_MUX:LPM_MUX_component " "Instantiated megafunction \"vga_mux:inst10\|LPM_MUX:LPM_MUX_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 30 " "Parameter \"LPM_WIDTH\" = \"30\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803271 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_SIZE 4 " "Parameter \"LPM_SIZE\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803271 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 2 " "Parameter \"LPM_WIDTHS\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803271 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_PIPELINE 0 " "Parameter \"LPM_PIPELINE\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803271 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_MUX " "Parameter \"LPM_TYPE\" = \"LPM_MUX\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803271 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT UNUSED " "Parameter \"LPM_HINT\" = \"UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803271 ""}  } { { "vga_mux.vhd" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 193 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457452803271 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_u7e.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_u7e.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_u7e " "Found entity 1: mux_u7e" {  } { { "db/mux_u7e.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/mux_u7e.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452803681 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452803681 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_u7e vga_mux:inst10\|LPM_MUX:LPM_MUX_component\|mux_u7e:auto_generated " "Elaborating entity \"mux_u7e\" for hierarchy \"vga_mux:inst10\|LPM_MUX:LPM_MUX_component\|mux_u7e:auto_generated\"" {  } { { "lpm_mux.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mux.tdf" 86 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803700 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_mouse_square vga_mouse_square:vga_mouse_catapult_inst " "Elaborating entity \"vga_mouse_square\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "vga_mouse_catapult_inst" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 848 1672 1960 1024 "vga_mouse_catapult_inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803767 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:vga_xy_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:vga_xy_rsc_mgc_in_wire\"" {  } { { "catapult_ip/mouse/rtl.v" "vga_xy_rsc_mgc_in_wire" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 137 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803833 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:mouse_xy_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:mouse_xy_rsc_mgc_in_wire\"" {  } { { "catapult_ip/mouse/rtl.v" "mouse_xy_rsc_mgc_in_wire" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 142 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803878 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:cursor_size_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:cursor_size_rsc_mgc_in_wire\"" {  } { { "catapult_ip/mouse/rtl.v" "cursor_size_rsc_mgc_in_wire" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 147 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803907 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:video_in_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:video_in_rsc_mgc_in_wire\"" {  } { { "catapult_ip/mouse/rtl.v" "video_in_rsc_mgc_in_wire" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 152 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803950 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_out_stdreg vga_mouse_square:vga_mouse_catapult_inst\|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg " "Elaborating entity \"mgc_out_stdreg\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg\"" {  } { { "catapult_ip/mouse/rtl.v" "video_out_rsc_mgc_out_stdreg" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 157 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803989 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_mouse_square_core vga_mouse_square:vga_mouse_catapult_inst\|vga_mouse_square_core:vga_mouse_square_core_inst " "Elaborating entity \"vga_mouse_square_core\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|vga_mouse_square_core:vga_mouse_square_core_inst\"" {  } { { "catapult_ip/mouse/rtl.v" "vga_mouse_square_core_inst" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 167 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804020 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sobel sobel:inst1 " "Elaborating entity \"sobel\" for hierarchy \"sobel:inst1\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "inst1" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 1080 1704 1944 1192 "inst1" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804062 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire sobel:inst1\|mgc_in_wire:vin_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"sobel:inst1\|mgc_in_wire:vin_rsc_mgc_in_wire\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "vin_rsc_mgc_in_wire" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 896 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804124 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_out_stdreg sobel:inst1\|mgc_out_stdreg:vout_rsc_mgc_out_stdreg " "Elaborating entity \"mgc_out_stdreg\" for hierarchy \"sobel:inst1\|mgc_out_stdreg:vout_rsc_mgc_out_stdreg\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "vout_rsc_mgc_out_stdreg" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 901 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804184 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sobel_core sobel:inst1\|sobel_core:sobel_core_inst " "Elaborating entity \"sobel_core\" for hierarchy \"sobel:inst1\|sobel_core:sobel_core_inst\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "sobel_core_inst" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 908 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804217 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift_taps altshift_taps:fifo_inst2 " "Elaborating entity \"altshift_taps\" for hierarchy \"altshift_taps:fifo_inst2\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "fifo_inst2" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804308 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "altshift_taps:fifo_inst2 " "Elaborated megafunction instantiation \"altshift_taps:fifo_inst2\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452804317 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "altshift_taps:fifo_inst2 " "Instantiated megafunction \"altshift_taps:fifo_inst2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMBER_OF_TAPS 3 " "Parameter \"NUMBER_OF_TAPS\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804317 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "TAP_DISTANCE 800 " "Parameter \"TAP_DISTANCE\" = \"800\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804317 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH 30 " "Parameter \"WIDTH\" = \"30\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804317 ""}  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457452804317 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/shift_taps_jpm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/shift_taps_jpm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 shift_taps_jpm " "Found entity 1: shift_taps_jpm" {  } { { "db/shift_taps_jpm.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_jpm.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452804446 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452804446 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_taps_jpm altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated " "Elaborating entity \"shift_taps_jpm\" for hierarchy \"altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\"" {  } { { "altshift_taps.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804463 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_5n81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_5n81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_5n81 " "Found entity 1: altsyncram_5n81" {  } { { "db/altsyncram_5n81.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_5n81.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452804634 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452804634 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_5n81 altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\|altsyncram_5n81:altsyncram2 " "Elaborating entity \"altsyncram_5n81\" for hierarchy \"altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\|altsyncram_5n81:altsyncram2\"" {  } { { "db/shift_taps_jpm.tdf" "altsyncram2" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_jpm.tdf" 35 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804651 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1tf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_1tf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1tf " "Found entity 1: cntr_1tf" {  } { { "db/cntr_1tf.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452804823 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452804823 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1tf altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\|cntr_1tf:cntr1 " "Elaborating entity \"cntr_1tf\" for hierarchy \"altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\|cntr_1tf:cntr1\"" {  } { { "db/shift_taps_jpm.tdf" "cntr1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_jpm.tdf" 36 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804838 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_ugc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_ugc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_ugc " "Found entity 1: cmpr_ugc" {  } { { "db/cmpr_ugc.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_ugc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452805003 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452805003 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_ugc altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\|cntr_1tf:cntr1\|cmpr_ugc:cmpr4 " "Elaborating entity \"cmpr_ugc\" for hierarchy \"altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\|cntr_1tf:cntr1\|cmpr_ugc:cmpr4\"" {  } { { "db/cntr_1tf.tdf" "cmpr4" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf" 85 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452805020 ""}
{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\|q_b\[15\] " "Synthesized away node \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\|q_b\[15\]\"" {  } { { "db/altsyncram_de51.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf" 521 2 0 } } { "db/dcfifo_v5o1.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 61 2 0 } } { "dcfifo.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/dcfifo.tdf" 188 3 0 } } { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 319 0 0 } } { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 364 0 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 64 760 1048 560 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452806031 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:read_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\|q_b\[15\] " "Synthesized away node \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:read_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\|q_b\[15\]\"" {  } { { "db/altsyncram_de51.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf" 521 2 0 } } { "db/dcfifo_v5o1.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 61 2 0 } } { "dcfifo.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/dcfifo.tdf" 188 3 0 } } { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 308 0 0 } } { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 364 0 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 64 760 1048 560 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452806031 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15"}  } {  } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Quartus II" 0 -1 1457452806031 ""}  } {  } 0 14284 "Synthesized away the following node(s):" 0 0 "Quartus II" 0 -1 1457452806031 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "21 " "Inferred 21 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult17 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult17\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult17" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 423 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult19 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult19\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult19" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 429 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult0\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult0" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 205 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult18 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult18\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult18" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 424 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult20 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult20\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult20" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 430 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult16 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult16\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult16" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 418 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult2 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult2\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult2" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult4 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult4\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult4" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 244 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult6 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult6\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult6" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 255 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult11 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult11\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult11" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 390 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult1\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 228 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult7 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult7\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult7" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 373 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult13 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult13\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult13" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 398 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult3 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult3\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult3" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 239 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult8 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult8\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult8" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 377 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult15 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult15\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult15" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 406 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult5 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult5\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult5" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 250 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult9 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult9\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult9" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 381 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult10 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult10\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult10" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 386 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult12 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult12\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult12" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 394 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult14 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult14\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult14" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 402 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1457452807973 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 423 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17 " "Instantiated megafunction \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 2 " "Parameter \"LPM_WIDTHA\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 9 " "Parameter \"LPM_WIDTHB\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 11 " "Parameter \"LPM_WIDTHP\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 11 " "Parameter \"LPM_WIDTHR\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""}  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 423 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457452808238 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\|multcore:mult_core sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\|multcore:mult_core\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 423 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808454 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\|multcore:mult_core\|mpar_add:padder sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 423 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808584 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\|altshift:external_latency_ffs sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 423 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808703 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 424 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18 " "Instantiated megafunction \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 3 " "Parameter \"LPM_WIDTHA\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 6 " "Parameter \"LPM_WIDTHB\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 9 " "Parameter \"LPM_WIDTHP\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 9 " "Parameter \"LPM_WIDTHR\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""}  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 424 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457452808845 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\|multcore:mult_core sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\|multcore:mult_core\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 424 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808869 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\|multcore:mult_core\|mpar_add:padder sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 424 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808890 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\|altshift:external_latency_ffs sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 424 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808905 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Instantiated megafunction \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 10 " "Parameter \"LPM_WIDTHA\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 2 " "Parameter \"LPM_WIDTHB\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 12 " "Parameter \"LPM_WIDTHP\" = \"12\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 12 " "Parameter \"LPM_WIDTHR\" = \"12\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 6 " "Parameter \"MAXIMIZE_SPEED\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""}  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457452809050 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 322 5 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809071 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mul_lfrg:mul_lfrg_first_mod sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mul_lfrg:mul_lfrg_first_mod\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 298 9 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809239 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 396 9 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809263 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf" 115 9 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809465 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_gfh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_gfh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_gfh " "Found entity 1: add_sub_gfh" {  } { { "db/add_sub_gfh.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/add_sub_gfh.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452809605 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452809605 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mul_lfrg:\$00030 sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mul_lfrg:\$00030\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 958 39 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809652 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mul_lfrg:\$00032 sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mul_lfrg:\$00032\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 970 44 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809673 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|altshift:external_latency_ffs sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809694 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult11 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult11\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 390 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult11 " "Instantiated megafunction \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult11\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 10 " "Parameter \"LPM_WIDTHA\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 2 " "Parameter \"LPM_WIDTHB\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 12 " "Parameter \"LPM_WIDTHP\" = \"12\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 12 " "Parameter \"LPM_WIDTHR\" = \"12\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 6 " "Parameter \"MAXIMIZE_SPEED\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""}  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 390 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457452809955 ""}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "10 " "10 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1457452812672 ""}
{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC_HDR" "" "The following nodes have both tri-state and non-tri-state drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[20\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[20\]\" and its non-tri-state driver." {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "Quartus II" 0 -1 1457452812897 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[14\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[14\]\" and its non-tri-state driver." {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "Quartus II" 0 -1 1457452812897 ""}  } {  } 0 13034 "The following nodes have both tri-state and non-tri-state drivers" 0 0 "Quartus II" 0 -1 1457452812897 ""}
{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "The following bidir pins have no drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""}  } {  } 0 13039 "The following bidir pins have no drivers" 0 0 "Quartus II" 0 -1 1457452812900 ""}
{ "Warning" "WMLS_OPT_REPLACED_VCC_OR_GND_WITH_TRI_HDR" "" "The following tri-state nodes are fed by constants" { { "Warning" "WMLS_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "GPIO_1\[15\] VCC pin " "The pin \"GPIO_1\[15\]\" is fed by VCC" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13033 "The %3!s! \"%1!s!\" is fed by %2!s!" 0 0 "Quartus II" 0 -1 1457452812912 ""}  } {  } 0 13032 "The following tri-state nodes are fed by constants" 0 0 "Quartus II" 0 -1 1457452812912 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "db/a_graycounter_s57.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf" 32 2 0 } } { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 64 -1 0 } } { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 79 -1 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 45 -1 0 } } { "db/a_graycounter_ojc.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf" 32 2 0 } } { "db/a_graycounter_s57.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf" 45 2 0 } } { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 63 -1 0 } } { "db/a_graycounter_ojc.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf" 45 2 0 } } { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 59 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1457452813120 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1457452813134 ""}
{ "Warning" "WMLS_MLS_ENABLED_OE" "" "TRI or OPNDRN buffers permanently enabled" { { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1~synth " "Node \"GPIO_1~synth\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452814126 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1~synth " "Node \"GPIO_1~synth\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452814126 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1~synth " "Node \"GPIO_1~synth\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452814126 ""}  } {  } 0 13009 "TRI or OPNDRN buffers permanently enabled" 0 0 "Quartus II" 0 -1 1457452814126 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CKE VCC " "Pin \"DRAM_CKE\" is stuck at VCC" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 344 1144 1320 360 "DRAM_CKE" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457452814131 "|TOP_DE0_CAMERA_MOUSE|DRAM_CKE"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1_CLKOUT\[1\] GND " "Pin \"GPIO_1_CLKOUT\[1\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 504 1144 1354 520 "GPIO_1_CLKOUT\[1..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457452814131 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKOUT[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[9\] GND " "Pin \"LEDG\[9\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457452814131 "|TOP_DE0_CAMERA_MOUSE|LEDG[9]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[8\] GND " "Pin \"LEDG\[8\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457452814131 "|TOP_DE0_CAMERA_MOUSE|LEDG[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[7\] GND " "Pin \"LEDG\[7\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457452814131 "|TOP_DE0_CAMERA_MOUSE|LEDG[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[6\] GND " "Pin \"LEDG\[6\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457452814131 "|TOP_DE0_CAMERA_MOUSE|LEDG[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[5\] GND " "Pin \"LEDG\[5\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457452814131 "|TOP_DE0_CAMERA_MOUSE|LEDG[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[4\] GND " "Pin \"LEDG\[4\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457452814131 "|TOP_DE0_CAMERA_MOUSE|LEDG[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[3\] GND " "Pin \"LEDG\[3\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457452814131 "|TOP_DE0_CAMERA_MOUSE|LEDG[3]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1457452814131 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1457452814413 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "32 " "32 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1457452815698 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1457452822603 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452822603 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GPIO_1_CLKIN\[1\] " "No output dependent on input pin \"GPIO_1_CLKIN\[1\]\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 136 480 704 152 "GPIO_1_CLKIN" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452824077 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "No output dependent on input pin \"SW\[9\]\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452824077 "|TOP_DE0_CAMERA_MOUSE|SW[9]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "No output dependent on input pin \"SW\[8\]\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452824077 "|TOP_DE0_CAMERA_MOUSE|SW[8]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1457452824077 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "3737 " "Implemented 3737 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "16 " "Implemented 16 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1457452824142 ""} { "Info" "ICUT_CUT_TM_OPINS" "77 " "Implemented 77 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1457452824142 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "50 " "Implemented 50 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1457452824142 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3417 " "Implemented 3417 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1457452824142 ""} { "Info" "ICUT_CUT_TM_RAMS" "176 " "Implemented 176 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1457452824142 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" {  } {  } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1457452824142 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1457452824142 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 113 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 113 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "579 " "Peak virtual memory: 579 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457452824658 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:00:24 2016 " "Processing ended: Tue Mar 08 16:00:24 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457452824658 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:40 " "Elapsed time: 00:00:40" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457452824658 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457452824658 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1457452824658 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1457452833557 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457452833613 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:00:31 2016 " "Processing started: Tue Mar 08 16:00:31 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457452833613 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1457452833613 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M " "Command: quartus_fit --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1457452833632 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1457452833748 ""}
{ "Info" "0" "" "Project  = DE0_D5M" {  } {  } 0 0 "Project  = DE0_D5M" 0 0 "Fitter" 0 0 1457452833749 ""}
{ "Info" "0" "" "Revision = DE0_D5M" {  } {  } 0 0 "Revision = DE0_D5M" 0 0 "Fitter" 0 0 1457452833749 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1457452835242 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "DE0_D5M EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"DE0_D5M\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1457452835729 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1457452835823 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1457452835823 ""}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|pll1 Cyclone III PLL " "Implemented PLL \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|pll1\" as Cyclone III PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[0\] 5 2 0 0 " "Implementing clock multiplication of 5, clock division of 2, and phase shift of 0 degrees (0 ps) for DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[0\] port" {  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 27 2 0 } } { "" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2979 9224 9983 0}  }  } }  } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1457452835882 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[1\] 5 2 -117 -2600 " "Implementing clock multiplication of 5, clock division of 2, and phase shift of -117 degrees (-2600 ps) for DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[1\] port" {  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 27 2 0 } } { "" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2980 9224 9983 0}  }  } }  } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1457452835882 ""}  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 27 2 0 } } { "" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2979 9224 9983 0}  }  } }  } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1457452835882 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1457452836002 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1457452836276 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1457452836276 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1457452836276 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1457452836276 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "4 " "Fitter converted 4 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12522 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457452836290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12524 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457452836290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12526 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457452836290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12528 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457452836290 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1457452836290 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1457452836300 ""}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1457452836314 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 143 " "No exact pin location assignment(s) for 1 pins of 143 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "VGA_CLK " "Pin VGA_CLK not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { VGA_CLK } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 1272 736 912 1288 "VGA_CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { VGA_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 310 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457452837164 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1457452837164 ""}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "dcfifo_v5o1 " "Entity dcfifo_v5o1" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_qe9:dffpipe16\|dffe17a*  " "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_qe9:dffpipe16\|dffe17a* " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1457452840334 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_pe9:dffpipe13\|dffe14a*  " "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_pe9:dffpipe13\|dffe14a* " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1457452840334 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1457452840334 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1457452840334 ""}
{ "Info" "ISTA_SDC_FOUND" "DE0_D5M.sdc " "Reading SDC File: 'DE0_D5M.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1457452840358 ""}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1457452840368 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1457452840368 ""}  } {  } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1457452840368 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|clk_div\[8\] " "Node: ps2:inst6\|clk_div\[8\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1457452840381 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|clk_div[8]"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|ps2_clk_in " "Node: ps2:inst6\|ps2_clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1457452840381 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|ps2_clk_in"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|rClk\[0\] " "Node: DE0_D5M:inst\|rClk\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1457452840381 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|rClk[0]"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_1_CLKIN\[0\] " "Node: GPIO_1_CLKIN\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1457452840381 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[0]"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Node: DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1457452840382 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK"}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) CLOCK_50 (Rise) setup and hold " "From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452840456 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From CLOCK_50 (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452840456 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452840456 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1457452840456 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1457452840475 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 3 clocks " "Found 3 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1457452840491 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1457452840491 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000     CLOCK_50 " "  20.000     CLOCK_50" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1457452840491 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   8.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " "   8.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1457452840491 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   8.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\] " "   8.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1457452840491 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1457452840491 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN G21 (CLK4, DIFFCLK_2p)) " "Automatically promoted node CLOCK_50~input (placed in PIN G21 (CLK4, DIFFCLK_2p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G7 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840734 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|rClk\[0\] " "Destination node DE0_D5M:inst\|rClk\[0\]" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 202 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|rClk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 3322 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840734 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2:inst6\|clk_div\[8\] " "Destination node ps2:inst6\|clk_div\[8\]" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 97 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|clk_div[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2278 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840734 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Destination node DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 69 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2450 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840734 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457452840734 ""}  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 88 424 592 104 "CLOCK_50" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12506 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840734 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[0\] (placed in counter C0 of PLL_2) " "Automatically promoted node DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[0\] (placed in counter C0 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G8 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840744 ""}  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 31 2 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2979 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840744 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[1\] (placed in counter C1 of PLL_2) " "Automatically promoted node DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[1\] (placed in counter C1 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G9 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840744 ""}  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 31 2 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2979 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840744 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "GPIO_1_CLKIN\[0\]~input (placed in PIN AB11 (CLK14, DIFFCLK_6n)) " "Automatically promoted node GPIO_1_CLKIN\[0\]~input (placed in PIN AB11 (CLK14, DIFFCLK_6n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840745 ""}  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 136 480 704 152 "GPIO_1_CLKIN" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1_CLKIN[0]~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12515 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840745 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|rClk\[0\]  " "Automatically promoted node DE0_D5M:inst\|rClk\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840746 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|rClk\[0\]~0 " "Destination node DE0_D5M:inst\|rClk\[0\]~0" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 202 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|rClk[0]~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 8151 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840746 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1_CLKOUT\[0\]~output " "Destination node GPIO_1_CLKOUT\[0\]~output" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 504 1144 1354 520 "GPIO_1_CLKOUT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1_CLKOUT[0]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12403 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840746 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "VGA_CLK~output " "Destination node VGA_CLK~output" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 1272 736 912 1288 "VGA_CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { VGA_CLK~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12387 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840746 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457452840746 ""}  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 202 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|rClk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 3322 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840746 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK  " "Automatically promoted node DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840747 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|I2C_CCD_Config:u8\|I2C_Controller:u0\|I2C_SCLK~1 " "Destination node DE0_D5M:inst\|I2C_CCD_Config:u8\|I2C_Controller:u0\|I2C_SCLK~1" {  } { { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 58 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|I2C_SCLK~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 6031 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840747 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK~0 " "Destination node DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK~0" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 69 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7084 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840747 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457452840747 ""}  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 69 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2450 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840747 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ps2:inst6\|ps2_clk_in  " "Automatically promoted node ps2:inst6\|ps2_clk_in " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840751 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2:inst6\|Equal2~0 " "Destination node ps2:inst6\|Equal2~0" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 186 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|Equal2~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5034 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840751 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457452840751 ""}  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 101 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|ps2_clk_in } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2301 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840751 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ps2:inst6\|clk_div\[8\]  " "Automatically promoted node ps2:inst6\|clk_div\[8\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840751 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2:inst6\|clk_div\[8\]~22 " "Destination node ps2:inst6\|clk_div\[8\]~22" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 97 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|clk_div[8]~22 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5028 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840751 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2:inst6\|ps2_clk_in " "Destination node ps2:inst6\|ps2_clk_in" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 101 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|ps2_clk_in } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2301 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840751 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457452840751 ""}  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 97 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|clk_div[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2278 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840751 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|Reset_Delay:u2\|oRST_0  " "Automatically promoted node DE0_D5M:inst\|Reset_Delay:u2\|oRST_0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|mRD~5 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|mRD~5" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 166 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|mRD~5 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5390 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR1_ADDR\[22\]~43 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR1_ADDR\[22\]~43" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22]~43 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7590 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR1_ADDR\[22\]~46 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR1_ADDR\[22\]~46" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22]~46 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7595 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD2_ADDR\[15\]~46 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD2_ADDR\[15\]~46" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15]~46 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7628 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD2_ADDR\[15\]~47 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD2_ADDR\[15\]~47" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15]~47 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7629 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR2_ADDR\[17\]~45 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR2_ADDR\[17\]~45" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~45 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7662 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR2_ADDR\[17\]~46 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR2_ADDR\[17\]~46" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~46 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7663 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD1_ADDR\[19\]~43 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD1_ADDR\[19\]~43" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19]~43 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7692 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD1_ADDR\[19\]~46 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD1_ADDR\[19\]~46" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19]~46 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7697 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Reset_Delay:u2\|oRST_0~2 " "Destination node DE0_D5M:inst\|Reset_Delay:u2\|oRST_0~2" {  } { { "V/Reset_Delay.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 46 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Reset_Delay:u2|oRST_0~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 8072 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457452840753 ""}  } { { "V/Reset_Delay.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 46 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Reset_Delay:u2|oRST_0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 3246 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840753 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|Reset_Delay:u2\|oRST_1  " "Automatically promoted node DE0_D5M:inst\|Reset_Delay:u2\|oRST_1 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840763 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[14\]~output " "Destination node GPIO_1\[14\]~output" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 8196 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840763 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Reset_Delay:u2\|oRST_1~1 " "Destination node DE0_D5M:inst\|Reset_Delay:u2\|oRST_1~1" {  } { { "V/Reset_Delay.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 47 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Reset_Delay:u2|oRST_1~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7119 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840763 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457452840763 ""}  } { { "V/Reset_Delay.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 47 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Reset_Delay:u2|oRST_1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 3247 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840763 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ps2:inst6\|Equal3~2  " "Automatically promoted node ps2:inst6\|Equal3~2 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840763 ""}  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 195 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|Equal3~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5050 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840763 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1457452844088 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1457452844100 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1457452844106 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1457452844120 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1457452844137 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1457452844148 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1457452844152 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1457452844164 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1457452847854 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1457452847871 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1457452847871 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1457452847913 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1457452847913 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1457452847913 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 27 6 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used --  6 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457452847924 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457452847924 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 16 30 " "I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 16 total pin(s) used --  30 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457452847924 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.3V 20 21 " "I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used --  21 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457452847924 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 3.3V 2 44 " "I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 2 total pin(s) used --  44 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457452847924 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.3V 15 28 " "I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used --  28 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457452847924 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 3.3V 28 19 " "I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 28 total pin(s) used --  19 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457452847924 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 3.3V 38 5 " "I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  5 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457452847924 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1457452847924 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1457452847924 ""}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|pll1 clk\[1\] DRAM_CLK~output " "PLL \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|pll1\" output port clk\[1\] feeds output pin \"DRAM_CLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 27 2 0 } } { "altpll.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "V/sdram_pll.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 94 0 0 } } { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 308 0 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 64 760 1048 560 "inst" "" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 328 1144 1320 344 "DRAM_CLK" "" } } } }  } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "Fitter" 0 -1 1457452848005 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCDAT " "Ignored I/O standard assignment to node \"AUD_ADCDAT\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCLRCK " "Ignored I/O standard assignment to node \"AUD_ADCLRCK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_BCLK " "Ignored I/O standard assignment to node \"AUD_BCLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACDAT " "Ignored I/O standard assignment to node \"AUD_DACDAT\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACLRCK " "Ignored I/O standard assignment to node \"AUD_DACLRCK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_XCK " "Ignored I/O standard assignment to node \"AUD_XCK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "BUTTON\[0\] " "Ignored I/O standard assignment to node \"BUTTON\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "BUTTON\[1\] " "Ignored I/O standard assignment to node \"BUTTON\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "BUTTON\[2\] " "Ignored I/O standard assignment to node \"BUTTON\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_50_2 " "Ignored I/O standard assignment to node \"CLOCK_50_2\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50_2" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[12\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[0\] " "Ignored I/O standard assignment to node \"FL_ADDR\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[10\] " "Ignored I/O standard assignment to node \"FL_ADDR\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[11\] " "Ignored I/O standard assignment to node \"FL_ADDR\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[12\] " "Ignored I/O standard assignment to node \"FL_ADDR\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[13\] " "Ignored I/O standard assignment to node \"FL_ADDR\[13\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[14\] " "Ignored I/O standard assignment to node \"FL_ADDR\[14\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[15\] " "Ignored I/O standard assignment to node \"FL_ADDR\[15\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[16\] " "Ignored I/O standard assignment to node \"FL_ADDR\[16\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[17\] " "Ignored I/O standard assignment to node \"FL_ADDR\[17\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[18\] " "Ignored I/O standard assignment to node \"FL_ADDR\[18\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[19\] " "Ignored I/O standard assignment to node \"FL_ADDR\[19\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[1\] " "Ignored I/O standard assignment to node \"FL_ADDR\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[20\] " "Ignored I/O standard assignment to node \"FL_ADDR\[20\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[21\] " "Ignored I/O standard assignment to node \"FL_ADDR\[21\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[2\] " "Ignored I/O standard assignment to node \"FL_ADDR\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[3\] " "Ignored I/O standard assignment to node \"FL_ADDR\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[4\] " "Ignored I/O standard assignment to node \"FL_ADDR\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[5\] " "Ignored I/O standard assignment to node \"FL_ADDR\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[6\] " "Ignored I/O standard assignment to node \"FL_ADDR\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[7\] " "Ignored I/O standard assignment to node \"FL_ADDR\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[8\] " "Ignored I/O standard assignment to node \"FL_ADDR\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[9\] " "Ignored I/O standard assignment to node \"FL_ADDR\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_BYTE_N " "Ignored I/O standard assignment to node \"FL_BYTE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_BYTE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_CE_N " "Ignored I/O standard assignment to node \"FL_CE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ15_AM1 " "Ignored I/O standard assignment to node \"FL_DQ15_AM1\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ15_AM1" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[0\] " "Ignored I/O standard assignment to node \"FL_DQ\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[10\] " "Ignored I/O standard assignment to node \"FL_DQ\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[11\] " "Ignored I/O standard assignment to node \"FL_DQ\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[12\] " "Ignored I/O standard assignment to node \"FL_DQ\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[13\] " "Ignored I/O standard assignment to node \"FL_DQ\[13\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[13\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[14\] " "Ignored I/O standard assignment to node \"FL_DQ\[14\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[14\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[1\] " "Ignored I/O standard assignment to node \"FL_DQ\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[2\] " "Ignored I/O standard assignment to node \"FL_DQ\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[3\] " "Ignored I/O standard assignment to node \"FL_DQ\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[4\] " "Ignored I/O standard assignment to node \"FL_DQ\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[5\] " "Ignored I/O standard assignment to node \"FL_DQ\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[6\] " "Ignored I/O standard assignment to node \"FL_DQ\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[7\] " "Ignored I/O standard assignment to node \"FL_DQ\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[8\] " "Ignored I/O standard assignment to node \"FL_DQ\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[9\] " "Ignored I/O standard assignment to node \"FL_DQ\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_OE_N " "Ignored I/O standard assignment to node \"FL_OE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RST_N " "Ignored I/O standard assignment to node \"FL_RST_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RY " "Ignored I/O standard assignment to node \"FL_RY\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WE_N " "Ignored I/O standard assignment to node \"FL_WE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WP_N " "Ignored I/O standard assignment to node \"FL_WP_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKIN\[0\] " "Ignored I/O standard assignment to node \"GPIO0_CLKIN\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKIN\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKIN\[1\] " "Ignored I/O standard assignment to node \"GPIO0_CLKIN\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKIN\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKOUT\[0\] " "Ignored I/O standard assignment to node \"GPIO0_CLKOUT\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKOUT\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKOUT\[1\] " "Ignored I/O standard assignment to node \"GPIO0_CLKOUT\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKOUT\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKIN\[0\] " "Ignored I/O standard assignment to node \"GPIO1_CLKIN\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKIN\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKIN\[1\] " "Ignored I/O standard assignment to node \"GPIO1_CLKIN\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKIN\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKOUT\[0\] " "Ignored I/O standard assignment to node \"GPIO1_CLKOUT\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKOUT\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKOUT\[1\] " "Ignored I/O standard assignment to node \"GPIO1_CLKOUT\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKOUT\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_1\[32\] " "Ignored I/O standard assignment to node \"GPIO_1\[32\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_1\[33\] " "Ignored I/O standard assignment to node \"GPIO_1\[33\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_1\[34\] " "Ignored I/O standard assignment to node \"GPIO_1\[34\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_1\[35\] " "Ignored I/O standard assignment to node \"GPIO_1\[35\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_DP " "Ignored I/O standard assignment to node \"HEX0_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[0\] " "Ignored I/O standard assignment to node \"HEX0_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[1\] " "Ignored I/O standard assignment to node \"HEX0_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[2\] " "Ignored I/O standard assignment to node \"HEX0_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[3\] " "Ignored I/O standard assignment to node \"HEX0_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[4\] " "Ignored I/O standard assignment to node \"HEX0_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[5\] " "Ignored I/O standard assignment to node \"HEX0_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[6\] " "Ignored I/O standard assignment to node \"HEX0_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_DP " "Ignored I/O standard assignment to node \"HEX1_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[0\] " "Ignored I/O standard assignment to node \"HEX1_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[1\] " "Ignored I/O standard assignment to node \"HEX1_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[2\] " "Ignored I/O standard assignment to node \"HEX1_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[3\] " "Ignored I/O standard assignment to node \"HEX1_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[4\] " "Ignored I/O standard assignment to node \"HEX1_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[5\] " "Ignored I/O standard assignment to node \"HEX1_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[6\] " "Ignored I/O standard assignment to node \"HEX1_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_DP " "Ignored I/O standard assignment to node \"HEX2_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[0\] " "Ignored I/O standard assignment to node \"HEX2_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[1\] " "Ignored I/O standard assignment to node \"HEX2_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[2\] " "Ignored I/O standard assignment to node \"HEX2_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[3\] " "Ignored I/O standard assignment to node \"HEX2_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[4\] " "Ignored I/O standard assignment to node \"HEX2_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[5\] " "Ignored I/O standard assignment to node \"HEX2_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[6\] " "Ignored I/O standard assignment to node \"HEX2_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_DP " "Ignored I/O standard assignment to node \"HEX3_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[0\] " "Ignored I/O standard assignment to node \"HEX3_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[1\] " "Ignored I/O standard assignment to node \"HEX3_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[2\] " "Ignored I/O standard assignment to node \"HEX3_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[3\] " "Ignored I/O standard assignment to node \"HEX3_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[4\] " "Ignored I/O standard assignment to node \"HEX3_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[5\] " "Ignored I/O standard assignment to node \"HEX3_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[6\] " "Ignored I/O standard assignment to node \"HEX3_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SCLK " "Ignored I/O standard assignment to node \"I2C_SCLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SDAT " "Ignored I/O standard assignment to node \"I2C_SDAT\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "KEY\[3\] " "Ignored I/O standard assignment to node \"KEY\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_BLON " "Ignored I/O standard assignment to node \"LCD_BLON\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[0\] " "Ignored I/O standard assignment to node \"LCD_DATA\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[1\] " "Ignored I/O standard assignment to node \"LCD_DATA\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[2\] " "Ignored I/O standard assignment to node \"LCD_DATA\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[3\] " "Ignored I/O standard assignment to node \"LCD_DATA\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[4\] " "Ignored I/O standard assignment to node \"LCD_DATA\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[5\] " "Ignored I/O standard assignment to node \"LCD_DATA\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[6\] " "Ignored I/O standard assignment to node \"LCD_DATA\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[7\] " "Ignored I/O standard assignment to node \"LCD_DATA\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_EN " "Ignored I/O standard assignment to node \"LCD_EN\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_RS " "Ignored I/O standard assignment to node \"LCD_RS\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_RW " "Ignored I/O standard assignment to node \"LCD_RW\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_KBCLK " "Ignored I/O standard assignment to node \"PS2_KBCLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_KBCLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_KBDAT " "Ignored I/O standard assignment to node \"PS2_KBDAT\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_KBDAT" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CLK " "Ignored I/O standard assignment to node \"SD_CLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CMD " "Ignored I/O standard assignment to node \"SD_CMD\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT0 " "Ignored I/O standard assignment to node \"SD_DAT0\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT0" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT3 " "Ignored I/O standard assignment to node \"SD_DAT3\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT3" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_WP_N " "Ignored I/O standard assignment to node \"SD_WP_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_CTS " "Ignored I/O standard assignment to node \"UART_CTS\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RTS " "Ignored I/O standard assignment to node \"UART_RTS\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RXD " "Ignored I/O standard assignment to node \"UART_RXD\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_TXD " "Ignored I/O standard assignment to node \"UART_TXD\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""}  } {  } 0 15709 "Ignored I/O standard assignments to the following nodes" 0 0 "Fitter" 0 -1 1457452848109 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50_2 " "Node \"CLOCK_50_2\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50_2" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1457452848129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1457452848129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0_DP " "Node \"HEX0_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1457452848129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_DP " "Node \"HEX1_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1457452848129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_DP " "Node \"HEX2_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1457452848129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_DP " "Node \"HEX3_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1457452848129 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1457452848129 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:12 " "Fitter preparation operations ending: elapsed time is 00:00:12" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457452848135 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1457452852244 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457452853030 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1457452853068 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1457452855776 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457452855788 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1457452860237 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 " "Router estimated average interconnect usage is 5% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X10_Y10 X20_Y19 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X10_Y10 to location X20_Y19" {  } { { "loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X10_Y10 to location X20_Y19"} { { 11 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X10_Y10 to location X20_Y19"} 10 10 11 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1457452863163 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1457452863163 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:05 " "Fitter routing operations ending: elapsed time is 00:00:05" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457452865158 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1457452865194 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1457452865194 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "2.70 " "Total time spent on timing analysis during the Fitter is 2.70 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1457452865332 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1457452865487 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1457452867721 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1457452867864 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1457452869538 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:08 " "Fitter post-fit operations ending: elapsed time is 00:00:08" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457452873441 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1457452874187 ""}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "66 Cyclone III " "66 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1_CLKIN\[1\] 3.3-V LVTTL AA11 " "Pin GPIO_1_CLKIN\[1\] uses I/O standard 3.3-V LVTTL at AA11" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1_CLKIN[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_CLKIN\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 136 480 704 152 "GPIO_1_CLKIN" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1_CLKIN[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 220 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[9\] 3.3-V LVTTL D2 " "Pin SW\[9\] uses I/O standard 3.3-V LVTTL at D2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 225 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[8\] 3.3-V LVTTL E4 " "Pin SW\[8\] uses I/O standard 3.3-V LVTTL at E4" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 226 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[15\] 3.3-V LVTTL F10 " "Pin DRAM_DQ\[15\] uses I/O standard 3.3-V LVTTL at F10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[15] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 172 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[14\] 3.3-V LVTTL E10 " "Pin DRAM_DQ\[14\] uses I/O standard 3.3-V LVTTL at E10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[14] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 173 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[13\] 3.3-V LVTTL A10 " "Pin DRAM_DQ\[13\] uses I/O standard 3.3-V LVTTL at A10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[13] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 174 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[12\] 3.3-V LVTTL B10 " "Pin DRAM_DQ\[12\] uses I/O standard 3.3-V LVTTL at B10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[12] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 175 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[11\] 3.3-V LVTTL C10 " "Pin DRAM_DQ\[11\] uses I/O standard 3.3-V LVTTL at C10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[11] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 176 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[10\] 3.3-V LVTTL A9 " "Pin DRAM_DQ\[10\] uses I/O standard 3.3-V LVTTL at A9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[10] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 177 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[9\] 3.3-V LVTTL B9 " "Pin DRAM_DQ\[9\] uses I/O standard 3.3-V LVTTL at B9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 178 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[8\] 3.3-V LVTTL A8 " "Pin DRAM_DQ\[8\] uses I/O standard 3.3-V LVTTL at A8" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 179 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[7\] 3.3-V LVTTL F8 " "Pin DRAM_DQ\[7\] uses I/O standard 3.3-V LVTTL at F8" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 180 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[6\] 3.3-V LVTTL H9 " "Pin DRAM_DQ\[6\] uses I/O standard 3.3-V LVTTL at H9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 181 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[5\] 3.3-V LVTTL G9 " "Pin DRAM_DQ\[5\] uses I/O standard 3.3-V LVTTL at G9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 182 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[4\] 3.3-V LVTTL F9 " "Pin DRAM_DQ\[4\] uses I/O standard 3.3-V LVTTL at F9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 183 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[3\] 3.3-V LVTTL E9 " "Pin DRAM_DQ\[3\] uses I/O standard 3.3-V LVTTL at E9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 184 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[2\] 3.3-V LVTTL H10 " "Pin DRAM_DQ\[2\] uses I/O standard 3.3-V LVTTL at H10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 185 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[1\] 3.3-V LVTTL G10 " "Pin DRAM_DQ\[1\] uses I/O standard 3.3-V LVTTL at G10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 186 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[0\] 3.3-V LVTTL D10 " "Pin DRAM_DQ\[0\] uses I/O standard 3.3-V LVTTL at D10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 187 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[31\] 3.3-V LVTTL V7 " "Pin GPIO_1\[31\] uses I/O standard 3.3-V LVTTL at V7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 188 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[30\] 3.3-V LVTTL V6 " "Pin GPIO_1\[30\] uses I/O standard 3.3-V LVTTL at V6" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 189 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[29\] 3.3-V LVTTL U8 " "Pin GPIO_1\[29\] uses I/O standard 3.3-V LVTTL at U8" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 190 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[28\] 3.3-V LVTTL Y7 " "Pin GPIO_1\[28\] uses I/O standard 3.3-V LVTTL at Y7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 191 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[27\] 3.3-V LVTTL T9 " "Pin GPIO_1\[27\] uses I/O standard 3.3-V LVTTL at T9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 192 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[26\] 3.3-V LVTTL U9 " "Pin GPIO_1\[26\] uses I/O standard 3.3-V LVTTL at U9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 193 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[25\] 3.3-V LVTTL T10 " "Pin GPIO_1\[25\] uses I/O standard 3.3-V LVTTL at T10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 194 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[24\] 3.3-V LVTTL U10 " "Pin GPIO_1\[24\] uses I/O standard 3.3-V LVTTL at U10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 195 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[23\] 3.3-V LVTTL R12 " "Pin GPIO_1\[23\] uses I/O standard 3.3-V LVTTL at R12" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 196 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[22\] 3.3-V LVTTL R11 " "Pin GPIO_1\[22\] uses I/O standard 3.3-V LVTTL at R11" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 197 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[21\] 3.3-V LVTTL T12 " "Pin GPIO_1\[21\] uses I/O standard 3.3-V LVTTL at T12" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 198 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[20\] 3.3-V LVTTL U12 " "Pin GPIO_1\[20\] uses I/O standard 3.3-V LVTTL at U12" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 199 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[19\] 3.3-V LVTTL R14 " "Pin GPIO_1\[19\] uses I/O standard 3.3-V LVTTL at R14" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[19] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 200 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[18\] 3.3-V LVTTL T14 " "Pin GPIO_1\[18\] uses I/O standard 3.3-V LVTTL at T14" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 201 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[17\] 3.3-V LVTTL AB7 " "Pin GPIO_1\[17\] uses I/O standard 3.3-V LVTTL at AB7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 202 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[16\] 3.3-V LVTTL AA7 " "Pin GPIO_1\[16\] uses I/O standard 3.3-V LVTTL at AA7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 203 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[15\] 3.3-V LVTTL AA9 " "Pin GPIO_1\[15\] uses I/O standard 3.3-V LVTTL at AA9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 204 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[14\] 3.3-V LVTTL AB9 " "Pin GPIO_1\[14\] uses I/O standard 3.3-V LVTTL at AB9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 205 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[13\] 3.3-V LVTTL V15 " "Pin GPIO_1\[13\] uses I/O standard 3.3-V LVTTL at V15" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 206 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[12\] 3.3-V LVTTL W15 " "Pin GPIO_1\[12\] uses I/O standard 3.3-V LVTTL at W15" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 207 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[11\] 3.3-V LVTTL T15 " "Pin GPIO_1\[11\] uses I/O standard 3.3-V LVTTL at T15" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 208 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[10\] 3.3-V LVTTL U15 " "Pin GPIO_1\[10\] uses I/O standard 3.3-V LVTTL at U15" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 209 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[9\] 3.3-V LVTTL W17 " "Pin GPIO_1\[9\] uses I/O standard 3.3-V LVTTL at W17" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 210 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[8\] 3.3-V LVTTL Y17 " "Pin GPIO_1\[8\] uses I/O standard 3.3-V LVTTL at Y17" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 211 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[7\] 3.3-V LVTTL AB17 " "Pin GPIO_1\[7\] uses I/O standard 3.3-V LVTTL at AB17" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 212 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[6\] 3.3-V LVTTL AA17 " "Pin GPIO_1\[6\] uses I/O standard 3.3-V LVTTL at AA17" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 213 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[5\] 3.3-V LVTTL AA18 " "Pin GPIO_1\[5\] uses I/O standard 3.3-V LVTTL at AA18" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 214 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[4\] 3.3-V LVTTL AB18 " "Pin GPIO_1\[4\] uses I/O standard 3.3-V LVTTL at AB18" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 215 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[3\] 3.3-V LVTTL AB19 " "Pin GPIO_1\[3\] uses I/O standard 3.3-V LVTTL at AB19" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 216 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[2\] 3.3-V LVTTL AA19 " "Pin GPIO_1\[2\] uses I/O standard 3.3-V LVTTL at AA19" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 217 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[1\] 3.3-V LVTTL AB20 " "Pin GPIO_1\[1\] uses I/O standard 3.3-V LVTTL at AB20" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 218 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[0\] 3.3-V LVTTL AA20 " "Pin GPIO_1\[0\] uses I/O standard 3.3-V LVTTL at AA20" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 219 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_DAT 3.3-V LVTTL P21 " "Pin PS2_DAT uses I/O standard 3.3-V LVTTL at P21" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PS2_DAT } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 576 376 552 592 "PS2_DAT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 313 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_CLK 3.3-V LVTTL P22 " "Pin PS2_CLK uses I/O standard 3.3-V LVTTL at P22" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PS2_CLK } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 600 376 552 616 "PS2_CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 314 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[4\] 3.3-V LVTTL G5 " "Pin SW\[4\] uses I/O standard 3.3-V LVTTL at G5" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 230 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[5\] 3.3-V LVTTL J7 " "Pin SW\[5\] uses I/O standard 3.3-V LVTTL at J7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 229 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL G21 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at G21" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 88 424 592 104 "CLOCK_50" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 300 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[0\] 3.3-V LVTTL H2 " "Pin KEY\[0\] uses I/O standard 3.3-V LVTTL at H2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { KEY[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 104 424 592 120 "KEY" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 224 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[7\] 3.3-V LVTTL E3 " "Pin SW\[7\] uses I/O standard 3.3-V LVTTL at E3" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 227 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[6\] 3.3-V LVTTL H7 " "Pin SW\[6\] uses I/O standard 3.3-V LVTTL at H7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 228 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL G4 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at G4" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 231 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL H6 " "Pin SW\[2\] uses I/O standard 3.3-V LVTTL at H6" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 232 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL H5 " "Pin SW\[1\] uses I/O standard 3.3-V LVTTL at H5" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 233 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL J6 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at J6" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 234 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[1\] 3.3-V LVTTL G3 " "Pin KEY\[1\] uses I/O standard 3.3-V LVTTL at G3" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { KEY[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 104 424 592 120 "KEY" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 223 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1_CLKIN\[0\] 3.3-V LVTTL AB11 " "Pin GPIO_1_CLKIN\[0\] uses I/O standard 3.3-V LVTTL at AB11" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1_CLKIN[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_CLKIN\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 136 480 704 152 "GPIO_1_CLKIN" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1_CLKIN[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 221 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[2\] 3.3-V LVTTL F1 " "Pin KEY\[2\] uses I/O standard 3.3-V LVTTL at F1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { KEY[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 104 424 592 120 "KEY" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { KEY[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 222 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""}  } {  } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1457452874250 ""}
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "31 " "Following 31 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Pin GPIO_1\[31\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 188 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Pin GPIO_1\[30\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 189 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Pin GPIO_1\[29\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 190 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Pin GPIO_1\[28\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 191 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Pin GPIO_1\[27\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 192 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Pin GPIO_1\[26\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 193 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Pin GPIO_1\[25\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 194 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Pin GPIO_1\[24\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 195 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Pin GPIO_1\[23\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 196 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Pin GPIO_1\[22\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 197 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Pin GPIO_1\[21\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 198 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently enabled " "Pin GPIO_1\[20\] has a permanently enabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 199 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Pin GPIO_1\[18\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 201 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Pin GPIO_1\[17\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 202 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Pin GPIO_1\[16\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 203 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently enabled " "Pin GPIO_1\[15\] has a permanently enabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 204 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently enabled " "Pin GPIO_1\[14\] has a permanently enabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 205 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Pin GPIO_1\[13\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 206 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Pin GPIO_1\[12\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 207 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Pin GPIO_1\[11\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 208 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Pin GPIO_1\[10\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 209 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Pin GPIO_1\[9\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 210 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Pin GPIO_1\[8\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 211 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Pin GPIO_1\[7\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 212 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Pin GPIO_1\[6\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 213 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Pin GPIO_1\[5\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 214 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Pin GPIO_1\[4\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 215 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Pin GPIO_1\[3\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 216 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Pin GPIO_1\[2\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 217 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Pin GPIO_1\[1\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 218 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently disabled " "Pin GPIO_1\[0\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 219 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""}  } {  } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "Fitter" 0 -1 1457452874281 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg " "Generated suppressed messages file //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1457452874858 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 149 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 149 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1254 " "Peak virtual memory: 1254 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457452878848 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:01:18 2016 " "Processing ended: Tue Mar 08 16:01:18 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457452878848 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:47 " "Elapsed time: 00:00:47" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457452878848 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:29 " "Total CPU time (on all processors): 00:00:29" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457452878848 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1457452878848 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1457452888644 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457452888653 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:01:28 2016 " "Processing started: Tue Mar 08 16:01:28 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457452888653 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1457452888653 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M " "Command: quartus_asm --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1457452888653 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1457452891195 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1457452891257 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "443 " "Peak virtual memory: 443 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457452893678 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:01:33 2016 " "Processing ended: Tue Mar 08 16:01:33 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457452893678 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457452893678 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457452893678 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1457452893678 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1457452894726 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1457452896576 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457452896601 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:01:34 2016 " "Processing started: Tue Mar 08 16:01:34 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457452896601 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1457452896601 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta DE0_D5M -c DE0_D5M " "Command: quartus_sta DE0_D5M -c DE0_D5M" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1457452896608 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1457452896694 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1457452898141 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1457452898237 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1457452898237 ""}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "dcfifo_v5o1 " "Entity dcfifo_v5o1" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_qe9:dffpipe16\|dffe17a*  " "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_qe9:dffpipe16\|dffe17a* " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1457452900596 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_pe9:dffpipe13\|dffe14a*  " "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_pe9:dffpipe13\|dffe14a* " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1457452900596 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1457452900596 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Quartus II" 0 -1 1457452900596 ""}
{ "Info" "ISTA_SDC_FOUND" "DE0_D5M.sdc " "Reading SDC File: 'DE0_D5M.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1457452900620 ""}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1457452900633 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1457452900633 ""}  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1457452900633 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|clk_div\[8\] " "Node: ps2:inst6\|clk_div\[8\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452900674 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|clk_div[8]"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|ps2_clk_in " "Node: ps2:inst6\|ps2_clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452900675 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|ps2_clk_in"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|rClk\[0\] " "Node: DE0_D5M:inst\|rClk\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452900675 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|rClk[0]"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_1_CLKIN\[0\] " "Node: GPIO_1_CLKIN\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452900675 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[0]"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Node: DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452900675 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK"}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) CLOCK_50 (Rise) setup and hold " "From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452900813 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From CLOCK_50 (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452900813 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452900813 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1457452900813 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1457452900846 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1457452900928 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1457452900988 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1457452900988 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.785 " "Worst-case setup slack is -0.785" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.785       -35.115 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "   -0.785       -35.115 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.205         0.000 CLOCK_50  " "   15.205         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901016 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452901016 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.266 " "Worst-case hold slack is 0.266" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.266         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.266         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.358         0.000 CLOCK_50  " "    0.358         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901039 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452901039 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -1.394 " "Worst-case recovery slack is -1.394" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.394      -307.981 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "   -1.394      -307.981 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   14.003         0.000 CLOCK_50  " "   14.003         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901070 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452901070 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.646 " "Worst-case removal slack is 1.646" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.646         0.000 CLOCK_50  " "    1.646         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.046         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    4.046         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901098 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452901098 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 3.734 " "Worst-case minimum pulse width slack is 3.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901122 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901122 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.734         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    3.734         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901122 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.580         0.000 CLOCK_50  " "    9.580         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901122 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452901122 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 40 synchronizer chains. " "Report Metastability: Found 40 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. " "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 40 " "Number of Synchronizer Chains Found: 40" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 11.151 ns " "Worst Case Available Settling Time: 11.151 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. " "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 " "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 " "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""}  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1457452901756 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1457452901810 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1457452903384 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|clk_div\[8\] " "Node: ps2:inst6\|clk_div\[8\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452903808 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|clk_div[8]"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|ps2_clk_in " "Node: ps2:inst6\|ps2_clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452903808 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|ps2_clk_in"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|rClk\[0\] " "Node: DE0_D5M:inst\|rClk\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452903808 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|rClk[0]"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_1_CLKIN\[0\] " "Node: GPIO_1_CLKIN\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452903808 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[0]"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Node: DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452903808 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK"}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) CLOCK_50 (Rise) setup and hold " "From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452903815 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From CLOCK_50 (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452903815 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452903815 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1457452903815 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1457452903849 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1457452903849 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.224 " "Worst-case setup slack is -0.224" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903872 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903872 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.224        -1.977 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "   -0.224        -1.977 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903872 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.655         0.000 CLOCK_50  " "   15.655         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903872 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452903872 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.261 " "Worst-case hold slack is 0.261" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903900 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903900 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.261         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.261         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903900 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.312         0.000 CLOCK_50  " "    0.312         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903900 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452903900 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -0.757 " "Worst-case recovery slack is -0.757" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903927 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903927 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.757      -122.138 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "   -0.757      -122.138 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903927 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   14.662         0.000 CLOCK_50  " "   14.662         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903927 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452903927 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.505 " "Worst-case removal slack is 1.505" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.505         0.000 CLOCK_50  " "    1.505         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.557         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    3.557         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903960 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452903960 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 3.739 " "Worst-case minimum pulse width slack is 3.739" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903988 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903988 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.739         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    3.739         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903988 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.562         0.000 CLOCK_50  " "    9.562         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903988 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452903988 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 40 synchronizer chains. " "Report Metastability: Found 40 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. " "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 40 " "Number of Synchronizer Chains Found: 40" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 11.652 ns " "Worst Case Available Settling Time: 11.652 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. " "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 " "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 " "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""}  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1457452904510 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|clk_div\[8\] " "Node: ps2:inst6\|clk_div\[8\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452905905 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|clk_div[8]"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|ps2_clk_in " "Node: ps2:inst6\|ps2_clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452905905 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|ps2_clk_in"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|rClk\[0\] " "Node: DE0_D5M:inst\|rClk\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452905905 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|rClk[0]"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_1_CLKIN\[0\] " "Node: GPIO_1_CLKIN\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452905905 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[0]"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Node: DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452905905 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK"}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) CLOCK_50 (Rise) setup and hold " "From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452905912 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From CLOCK_50 (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452905912 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452905912 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1457452905912 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 1.245 " "Worst-case setup slack is 1.245" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452905944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452905944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.245         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    1.245         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452905944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.284         0.000 CLOCK_50  " "   17.284         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452905944 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452905944 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.117 " "Worst-case hold slack is 0.117" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452905976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452905976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.117         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.117         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452905976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.187         0.000 CLOCK_50  " "    0.187         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452905976 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452905976 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 0.848 " "Worst-case recovery slack is 0.848" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.848         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.848         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.451         0.000 CLOCK_50  " "   16.451         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906009 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452906009 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.927 " "Worst-case removal slack is 0.927" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906042 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906042 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.927         0.000 CLOCK_50  " "    0.927         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906042 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.361         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    2.361         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906042 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452906042 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 3.746 " "Worst-case minimum pulse width slack is 3.746" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906073 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906073 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.746         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    3.746         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906073 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.266         0.000 CLOCK_50  " "    9.266         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906073 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452906073 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 40 synchronizer chains. " "Report Metastability: Found 40 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. " "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 40 " "Number of Synchronizer Chains Found: 40" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 13.268 ns " "Worst Case Available Settling Time: 13.268 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. " "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 " "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 " "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""}  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1457452907507 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1457452907513 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 29 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 29 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "539 " "Peak virtual memory: 539 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457452909301 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:01:49 2016 " "Processing ended: Tue Mar 08 16:01:49 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457452909301 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457452909301 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457452909301 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1457452909301 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 291 s " "Quartus II Full Compilation was successful. 0 errors, 291 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1457452931357 ""}