making tester

10 files changed, 1036 insertions, 432 deletions

diff --git a/src/ymh15/b_test_mips.cpp b/src/ymh15/b_test_mips.cpp
new file mode 100644
index 0000000..75afaa8
--- /dev/null
+++ b/src/ymh15/b_test_mips.cpp
@@ -0,0 +1,482 @@
+#include "../../include/mips.h"
+#include "test_mips_ymh15.hpp"
+
+#include <iostream>
+
+using namespace std;
+
+int main(int argc, char** argv) {
+    mips_mem_h ram = mips_mem_create_ram(4096);
+    mips_cpu_h cpu = mips_cpu_create(ram);
+
+    srand(time(NULL));
+
+    if(argc == 2) {
+        mips_cpu_set_debug_level(cpu, argv[1][0]-'0', stdout);
+    } else {
+        mips_cpu_set_debug_level(cpu, 0, NULL);
+    }
+
+    mips_test_begin_suite();
+    
+    int testId = mips_test_begin_test("ADD");
+    mips_test_end_test(testId, test_add(ram, cpu, ADD, 0x3fffffff, 0, 10), "Testing the adder without overflow");
+
+    testId = mips_test_begin_test("ADD");
+    mips_test_end_test(testId, !test_add(ram, cpu, ADD, 0x7fffffff, 1, 1), "Testing the adder with overflow");
+
+    testId = mips_test_begin_test("ADDU");
+    mips_test_end_test(testId, test_add(ram, cpu, ADDU, 0x3fffffff, 0, 10), "testing without overflow");
+
+    testId = mips_test_begin_test("ADDU");
+    mips_test_end_test(testId, test_add(ram, cpu, ADDU, 0x7fffffff, 1, 1), "Testing the adder with overflow");
+
+    testId = mips_test_begin_test("SUB");
+    mips_test_end_test(testId, test_add(ram, cpu, SUB, 0x3fffffff, 0, 10), "Testing the adder without overflow");
+
+    testId = mips_test_begin_test("SUB");
+    mips_test_end_test(testId, !test_add(ram, cpu, SUB, 0x7fffffff, 1, 1), "Testing the adder with overflow");
+
+    testId = mips_test_begin_test("SUBU");
+    mips_test_end_test(testId, test_add(ram, cpu, SUBU, 0x3fffffff, 0, 10), "Testing the adder without overflow");
+
+    testId = mips_test_begin_test("SUBU");
+    mips_test_end_test(testId, test_add(ram, cpu, SUBU, 0x7fffffff, 1, 1), "Testing the adder with overflow");
+
+    testId = mips_test_begin_test("AND");
+    mips_test_end_test(testId, test_bitwise(ram, cpu, AND), "Testing bitwise and");
+
+    testId = mips_test_begin_test("OR");
+    mips_test_end_test(testId, test_bitwise(ram, cpu, OR), "Testing bitwise or");
+
+    testId = mips_test_begin_test("XOR");
+    mips_test_end_test(testId, test_bitwise(ram, cpu, XOR), "Testing bitwise xor");
+
+    testId = mips_test_begin_test("ADDI");
+    mips_test_end_test(testId, test_I(ram, cpu, ADDI, 20, 10), "Testing addi");
+    
+    testId = mips_test_begin_test("ADDIU");
+    mips_test_end_test(testId, test_I(ram, cpu, ADDIU, 20, 10), "Testing addiu");
+    
+    testId = mips_test_begin_test("ANDI");
+    mips_test_end_test(testId, test_I(ram, cpu, ANDI, 20, 10), "Testing addi");
+    
+    testId = mips_test_begin_test("ORI");
+    mips_test_end_test(testId, test_I(ram, cpu, ORI, 20, 10), "Testing addi");
+    
+    testId = mips_test_begin_test("XORI");
+    mips_test_end_test(testId, test_I(ram, cpu, XORI, 20, 10), "Testing addi");
+
+    testId = mips_test_begin_test("BEQ");
+    mips_test_end_test(testId, test_branch(ram, cpu, 4, 4, 0, 9, 4), "Testing BEQ");
+
+    testId = mips_test_begin_test("BNE");
+    mips_test_end_test(testId, test_branch(ram, cpu, 5, 4, 0, 9, 10), "Testing BNE");
+
+    testId = mips_test_begin_test("BGEZ");
+    mips_test_end_test(testId, test_branch(ram, cpu, 1, 4, 0, 1, 20), "Testing BGEZ");
+    
+    testId = mips_test_begin_test("BLEZ");
+    mips_test_end_test(testId, test_branch(ram, cpu, 6, -1, 0, 0, 20), "Testing BGEZ");
+    
+    testId = mips_test_begin_test("BGTZ");
+    mips_test_end_test(testId, test_branch(ram, cpu, 7, 4, 0, 0, 20), "Testing BGEZ");
+
+    testId = mips_test_begin_test("BGEZAL");
+    mips_test_end_test(testId, test_branch(ram, cpu, 1, 4, 1, 17, 20), "Testing BGEZ");
+    
+    testId = mips_test_begin_test("BLTZAL");
+    mips_test_end_test(testId, test_branch(ram, cpu, 1, -1, 1, 16, 20), "Testing BGEZ");
+    
+    testId = mips_test_begin_test("BLTZ");
+    mips_test_end_test(testId, test_branch(ram, cpu, 1, -1, 0, 16, 20), "Testing BGEZ");
+    
+    testId = mips_test_begin_test("J");
+    mips_test_end_test(testId, test_jump(ram, cpu, J), "Testing J");
+    
+    testId = mips_test_begin_test("JAL");
+    mips_test_end_test(testId, test_jump(ram, cpu, JAL), "Testing JAL");
+    
+    testId = mips_test_begin_test("JALR");
+    mips_test_end_test(testId, test_jump(ram, cpu, JALR), "Testing JALR");
+    
+    testId = mips_test_begin_test("JR");
+    mips_test_end_test(testId, test_jump(ram, cpu, JR), "Testing JR");
+    
+    testId = mips_test_begin_test("LB");
+    mips_test_end_test(testId, test_load(ram, cpu, LB, 0xf7), "Testing LB");
+    
+    testId = mips_test_begin_test("LBU");
+    mips_test_end_test(testId, test_load(ram, cpu, LBU, 0xf7), "Testing LBU");
+    
+    testId = mips_test_begin_test("LH");
+    mips_test_end_test(testId, test_load(ram, cpu, LH, 0xff7f), "Testing LH");
+    
+    testId = mips_test_begin_test("LHU");
+    mips_test_end_test(testId, test_load(ram, cpu, LHU, 0xff7f), "Testing LHU");
+    
+    testId = mips_test_begin_test("LW");
+    mips_test_end_test(testId, test_load(ram, cpu, LW, 0xffffff7f), "Testing LW");
+    
+    testId = mips_test_begin_test("LUI");
+    mips_test_end_test(testId, test_load(ram, cpu, LUI, 0xff7f), "Testing LUI");
+    
+    testId = mips_test_begin_test("LWL");
+    mips_test_end_test(testId, test_load(ram, cpu, LWL, 0xff6fff7f), "Testing LWL");
+    
+    testId = mips_test_begin_test("LWR");
+    mips_test_end_test(testId, test_load(ram, cpu, LWR, 0xff6fff7f), "Testing LWR");
+    
+    testId = mips_test_begin_test("MULT");
+    mips_test_end_test(testId, test_mult_div(ram, cpu, MULT, 5, -4), "Testing LWR");
+    
+    testId = mips_test_begin_test("MULTU");
+    mips_test_end_test(testId, test_mult_div(ram, cpu, MULTU, 5, -4), "Testing LWR");
+    
+    testId = mips_test_begin_test("DIV");
+    mips_test_end_test(testId, test_mult_div(ram, cpu, DIV, 5, -4), "Testing LWR");
+
+    testId = mips_test_begin_test("DIVU");
+    mips_test_end_test(testId, test_mult_div(ram, cpu, DIVU, 5, -4), "Testing LWR");
+    
+    mips_test_end_suite();
+    return 0;
+}
+
+// R Type
+uint32_t gen_instruction(uint32_t src1, uint32_t src2, uint32_t dest,
+                     uint32_t shift, uint32_t function) {
+    uint32_t inst = 0;
+    inst = inst | src1 << 21 | src2 << 16 | dest << 11 | shift << 6 |
+        function;
+    return inst;
+}
+
+// I Type
+uint32_t gen_instruction(uint32_t opcode, uint32_t src, uint32_t dest,
+                     uint32_t Astart) {
+    uint32_t inst = 0;
+    inst = inst | opcode << 26 | src << 21 | dest << 16 | Astart;
+    return inst;
+}
+
+// J Type
+uint32_t gen_instruction(uint32_t opcode, uint32_t memory) {
+    uint32_t inst = 0;
+    inst = inst | opcode << 26 | memory;
+    return inst;
+}
+
+uint32_t change_endianness(uint32_t inst) {
+    inst = (inst << 24 | ((inst << 8)&0xff0000) |
+            ((inst >> 8)&0xff00) |inst >> 24);
+    return inst;
+}
+
+int test_add(mips_mem_h ram, mips_cpu_h cpu, uint32_t type, uint32_t max, uint8_t value, unsigned i_t) {
+    
+    uint32_t inst, ans, a, b;
+
+    for(unsigned i = 0; i < i_t; ++i) {
+        mips_error mips_err;
+        mips_cpu_reset(cpu);
+        inst = change_endianness(gen_instruction(9, 10, 8, 0, type));
+        if(value) {
+            a = max;
+            if(type > 0x21) {
+                b = -max;
+            } else {
+                b = max;
+            }
+        } else {
+            a = rand() % max;
+            b = rand() % max;
+        }
+        
+        mips_mem_write(ram, 0, 4, (uint8_t*)&inst);
+        
+        mips_cpu_set_register(cpu, 9, a);
+        mips_cpu_set_register(cpu, 10, b);
+    
+        mips_err = mips_cpu_step(cpu);
+    
+        mips_cpu_get_register(cpu, 8, &ans);
+
+        if(type < 0x22) {
+            //printf("%#10x + %#10x = %#10x\t%#10x\n", a, b, ans, mips_err);
+            if(mips_err == mips_ExceptionArithmeticOverflow || a+b!=ans) {
+                return 0;
+            }
+        } else {
+            //printf("%#10x - %#10x = %#10x\t%#10x\n", a, b, ans, mips_err);
+            if(mips_err == mips_ExceptionArithmeticOverflow || a-b!=ans) {
+                return 0;
+            }
+        }
+    }
+
+    return 1;
+}
+
+int test_bitwise(mips_mem_h ram, mips_cpu_h cpu, uint8_t op) {
+    uint32_t a, b, ans, inst;
+    int passed;
+    for(unsigned i = 0; i < 10; ++i) {
+        passed = 0;
+        mips_cpu_reset(cpu);
+        inst = change_endianness(gen_instruction(8, 9, 7, 0, op));
+
+        a = rand() % 0xffffffff;
+        b = rand() % 0xffffffff;
+
+        mips_mem_write(ram, 0, 4, (uint8_t*)&inst);
+
+        mips_cpu_set_register(cpu, 8, a);
+        mips_cpu_set_register(cpu, 9, b);
+
+        mips_error mips_err = mips_cpu_step(cpu);
+
+        mips_cpu_get_register(cpu, 7, &ans);
+
+        if(op == AND) {
+            //printf("%#10x & %#10x = %#10x\t%#10x\n", a, b, ans, mips_err);
+            if((a & b) == ans) {
+                passed = 1;
+            }
+        } else if(op == OR) {
+            //printf("%#10x | %#10x = %#10x\t%#10x\n", a, b, ans, mips_err);
+            if((a | b) == ans) {
+                passed = 1;
+            }
+        } else {
+            //printf("%#10x ^ %#10x = %#10x\t%#10x\n", a, b, ans, mips_err);
+            if((a ^ b) == ans) {
+                passed = 1;
+            }
+        }
+
+        
+        if(mips_err != mips_Success || !passed) {
+            return 0;
+        }
+    }
+    return 1;
+}
+
+int test_I(mips_mem_h ram, mips_cpu_h cpu, uint32_t type,
+             uint32_t num1, uint32_t num2) {
+    int passed = 0;
+    uint32_t result, inst;
+
+    mips_cpu_reset(cpu);
+    inst = change_endianness(gen_instruction(type, 8, 7, num1));
+
+    mips_mem_write(ram, 0, 4, (uint8_t*)&inst);
+    mips_cpu_set_register(cpu, 8, num2);
+
+    mips_cpu_step(cpu);
+
+    mips_cpu_get_register(cpu, 7, &result);
+
+    switch(type) {
+    case 8:
+        if(result == num1 + num2) {
+            passed = 1;
+        }
+    case 9:
+        if(result == num1 + num2) {
+            passed = 1;
+        }
+    case 12:
+        if(result == (num1 & num2)) {
+            passed = 1;
+        }
+    case 13:
+        if(result == (num1 | num2)) {
+            passed = 1;
+        }
+    case 14:
+        if(result == (num1 ^ num2)) {
+            passed = 1;
+        }
+    default:;
+    }
+
+    return passed;
+}
+
+int test_branch(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode, uint32_t a, uint8_t l, uint32_t opc2, uint32_t b) {
+    int passed = 0;
+    int pass = 0;
+    uint32_t reg10, reg11, reg31, pc_set;
+    pc_set = 32;
+    mips_cpu_reset(cpu);
+    mips_cpu_set_pc(cpu, pc_set);
+
+    uint32_t inst = change_endianness(gen_instruction(opcode, 8, opc2, 3));
+    mips_mem_write(ram, pc_set, 4, (uint8_t*)&inst);
+    inst = change_endianness(gen_instruction(8, 9, 10, 0, ADDU));
+    mips_mem_write(ram, pc_set+4, 4, (uint8_t*)&inst);
+    inst = change_endianness(gen_instruction(8, 12, 11, 0, ADDU));
+    mips_mem_write(ram, pc_set+16, 4, (uint8_t*)&inst);
+    inst = change_endianness(gen_instruction(8, 13, 10, 0, ADDU));
+    mips_mem_write(ram, pc_set+8, 4, (uint8_t*)&inst);
+
+    mips_cpu_set_register(cpu, 8, a);
+    mips_cpu_set_register(cpu, 9, b);
+    mips_cpu_set_register(cpu, 12, 30);
+    mips_cpu_set_register(cpu, 13, 100);
+
+    mips_cpu_step(cpu);
+    mips_cpu_step(cpu);
+    mips_cpu_step(cpu);
+
+    mips_cpu_get_register(cpu, 10, &reg10);
+    mips_cpu_get_register(cpu, 11, &reg11);
+
+    if(l == 1) {
+        mips_cpu_get_register(cpu, 31, &reg31);
+        if(reg31 == pc_set+8) {
+            pass = 1;
+        }
+    } else {
+        pass = 1;
+    }
+
+    if(reg10 == a+b && reg11 == a+30 && pass) {
+        passed = 1;
+    } else {
+        passed = 0;
+    }
+    
+    return passed;
+}
+
+int test_jump(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode) {
+    int passed = 0;
+    uint32_t inst, reg10, reg13, reg16, reg31;
+
+    mips_cpu_reset(cpu);
+
+    if(opcode == 2 || opcode == 3) {
+        inst = change_endianness(gen_instruction(opcode, 0x20));
+    } else if(opcode == 8 || opcode == 9) {
+        inst = change_endianness(gen_instruction(25, 0, 31, 0, opcode));
+    }
+
+    mips_mem_write(ram, 0, 4, (uint8_t*)&inst);
+
+    inst = change_endianness(gen_instruction(8, 9, 10, 0, ADDU));
+    mips_mem_write(ram, 4, 4, (uint8_t*)&inst);
+    inst = change_endianness(gen_instruction(11, 12, 13, 0, ADDU));
+    mips_mem_write(ram, 8, 4, (uint8_t*)&inst);
+    inst = change_endianness(gen_instruction(14, 15, 16, 0, ADDU));
+    mips_mem_write(ram, 0x20<<2, 4, (uint8_t*)&inst);
+
+    mips_cpu_set_register(cpu, 8, 8);
+    mips_cpu_set_register(cpu, 9, 9);
+    mips_cpu_set_register(cpu, 10, 10);
+    mips_cpu_set_register(cpu, 11, 11);
+    mips_cpu_set_register(cpu, 12, 12);
+    mips_cpu_set_register(cpu, 13, 13);
+    mips_cpu_set_register(cpu, 14, 14);
+    mips_cpu_set_register(cpu, 15, 15);
+    mips_cpu_set_register(cpu, 16, 16);
+    mips_cpu_set_register(cpu, 25, 0x20<<2);
+
+    mips_cpu_step(cpu);
+    mips_cpu_step(cpu);
+    mips_cpu_step(cpu);
+
+    mips_cpu_get_register(cpu, 10, &reg10);
+    mips_cpu_get_register(cpu, 13, &reg13);
+    mips_cpu_get_register(cpu, 16, &reg16);
+    mips_cpu_get_register(cpu, 31, &reg31);
+
+    if(reg10 == 9+8 && reg13 == 13 && reg16 == 14+15) {
+        passed = 1;
+    }
+    
+    if((opcode == 3 || opcode == 9) && reg31 != 8) {
+        passed = 0;
+    }
+
+    return passed;
+}
+
+int test_load(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode, uint32_t word) {
+    int passed = 0;
+    uint16_t half_word;
+    uint8_t byte;
+    uint32_t res;
+
+    half_word = (uint16_t)word;
+    byte = (uint8_t)word;
+
+    mips_cpu_reset(cpu);
+
+    uint32_t inst = change_endianness(gen_instruction(opcode, 8, 9, 4));
+
+    mips_mem_write(ram, 0, 4, (uint8_t*)&inst);
+    
+    if(opcode == LB || opcode == LBU) {
+        mips_mem_write(ram, 0x30, 1, &byte);
+    } else if(opcode == LH || opcode == LHU) {
+        uint16_t tmp = (half_word<<8) | (half_word>>8);
+        mips_mem_write(ram, 0x30, 2, (uint8_t*)&tmp);
+    } else {
+        uint32_t tmp = change_endianness(word);
+        mips_mem_write(ram, 0x30, 4, (uint8_t*)&tmp);
+    }
+
+    mips_cpu_set_register(cpu, 8, 0x2c);
+    if(opcode == LWR) {
+        mips_cpu_set_register(cpu, 8, 0x2f);
+    }
+    mips_cpu_set_register(cpu, 9, 0xbabacdcd);
+
+    mips_cpu_step(cpu);
+    
+    mips_cpu_get_register(cpu, 9, &res);
+
+    if((res == (uint32_t)(int8_t)byte && opcode == LB) || (res == (uint32_t)byte && opcode == LBU) || (res == (uint32_t)(int16_t)half_word && opcode == LH) || (res == (uint32_t)half_word && opcode == LHU) || (res == word && opcode == LW) || (res == 4<<16 && opcode == LUI) || (res == ((word&0xffff)|(0xbaba0000)) && (opcode == LWR)) || (res == ((word&0xffff0000)|(0xcdcd)))) {
+        passed = 1;
+    }
+
+    return passed;
+}
+
+int test_mult_div(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode, uint32_t num1, uint32_t num2) {
+    int passed = 0;
+    uint64_t result;
+    uint32_t hi, lo;
+
+    mips_cpu_reset(cpu);
+    
+    uint32_t inst = change_endianness(gen_instruction(8, 9, 0, 0, opcode));
+    mips_mem_write(ram, 0, 4, (uint8_t*)&inst);
+    inst = change_endianness(gen_instruction(0, 0, 10, 0, MFHI));
+    mips_mem_write(ram, 4, 4, (uint8_t*)&inst);
+    inst = change_endianness(gen_instruction(0, 0, 11, 0, MFLO));
+    mips_mem_write(ram, 8, 4, (uint8_t*)&inst);
+
+    mips_cpu_set_register(cpu, 8, num1);
+    mips_cpu_set_register(cpu, 9, num2);
+    mips_cpu_set_register(cpu, 10, 0xabcde);
+    mips_cpu_set_register(cpu, 11, 0xf193b);
+
+    mips_cpu_step(cpu);
+    mips_cpu_step(cpu);
+    mips_cpu_step(cpu);
+
+    mips_cpu_get_register(cpu, 10, &hi);
+    mips_cpu_get_register(cpu, 11, &lo);
+
+    result = (((uint64_t)hi)<<32) | ((uint64_t)lo);
+
+    if((opcode == MULT && result == (uint64_t)((int64_t)(int32_t)num1*(int64_t)(int32_t)num2)) || (opcode == MULTU && result == (uint64_t)((uint32_t)num1)*(uint32_t)num2) || (opcode == DIV && lo == (uint32_t)((int32_t)num1/(int32_t)num2) && hi == (uint32_t)((int32_t)num1%(int32_t)num2)) || (opcode == DIVU && lo == num1/num2 && hi == num1%num2)) {
+        passed = 1;
+    }
+
+    return passed;
+}
diff --git a/src/ymh15/b_test_mips_ymh15.hpp b/src/ymh15/b_test_mips_ymh15.hpp
new file mode 100644
index 0000000..ca9f9fe
--- /dev/null
+++ b/src/ymh15/b_test_mips_ymh15.hpp
@@ -0,0 +1,83 @@
+#ifndef TEST_MIPS_YMH15_H
+#define TEST_MIPS_YMH15_H
+
+#include "../../include/mips.h"
+#include <cstdlib>
+#include <ctime>
+
+// Functions
+#define NOOP 0x0
+#define SLL 0x0
+#define SRL 0x2
+#define SRA 0x3
+#define SLLV 0x4
+#define SRLV 0x6
+#define SRAV 0x7
+#define JR 0x8
+#define JALR 0x9
+#define MFHI 0x10
+#define MTHI 0x11
+#define MFLO 0x12
+#define MTLO 0x13
+#define MULT 0x18
+#define MULTU 0x19
+#define DIV 0x1a
+#define DIVU 0x1b
+#define ADD 0x20
+#define ADDU 0x21
+#define SUB 0x22
+#define SUBU 0x23
+#define AND 0x24
+#define OR 0x25
+#define XOR 0x26
+#define SLT 0x2a
+#define SLTU 0x2b
+
+// OPcodes
+#define BGEZ 0x1
+#define BGEZAL 0x1
+#define BLTZ 0x1
+#define BLTZAL 0x1
+#define J 0x2
+#define JAL 0x3
+#define BEQ 0x4
+#define BNE 0x5
+#define BLEZ 0x6
+#define BGTZ 0x7
+#define ADDI 0x8
+#define ADDIU 0x9
+#define SLTI 0xa
+#define SLTIU 0xb
+#define ANDI 0xc
+#define ORI 0xd
+#define XORI 0xe
+#define LUI 0xf
+#define LB 0x20
+#define LH 0x21
+#define LWL 0x22
+#define LW 0x23
+#define LBU 0x24
+#define LHU 0x25
+#define LWR 0x26
+#define SB 0x28
+#define SH 0x29
+#define SW 0x2b
+
+uint32_t gen_instruction(uint32_t src1, uint32_t src2, uint32_t dest,
+                         uint32_t shift, uint32_t function);
+uint32_t gen_instruction(uint32_t opcode, uint32_t src, uint32_t dest,
+                         uint32_t Astart);
+uint32_t gen_instruction(uint32_t opcode, uint32_t memory);
+uint32_t change_endianness(uint32_t inst);
+
+int test_add(mips_mem_h ram, mips_cpu_h cpu, uint32_t type, uint32_t max,
+             uint8_t value, unsigned i_t);
+int test_bitwise(mips_mem_h ram, mips_cpu_h cpu, uint8_t op);
+int test_I(mips_mem_h ram, mips_cpu_h cpu, uint32_t type, uint32_t num1,
+              uint32_t num2);
+int test_branch(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode, uint32_t a, uint8_t l, uint32_t opc2, uint32_t b);
+int test_jump(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode);
+int test_load(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode, uint32_t word);
+int test_mult_div(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode, uint32_t num1, uint32_t num2);
+
+#endif // TEST_MIPS_YMH15_H
diff --git a/src/ymh15/mips_cpu.cpp b/src/ymh15/mips_cpu.cpp
index 06dd683..67ad8e2 100644
--- a/src/ymh15/mips_cpu.cpp
+++ b/src/ymh15/mips_cpu.cpp
@@ -114,15 +114,15 @@ mips_error mips_cpu_step(mips_cpu_h state) {
         }
         fprintf(state->debug_type, "\n\n");
     }
-    
-    if(state->debug_level > 0) {
-        fprintf(state->debug_type, "pc: %d\tpc_next: %d\tinst: %#10x\tdelay_slot: %d\n", state->pc, state->next_pc, inst, state->delay_slot);
-    }
 
     // it then executes the instruction by decoding it first and returns
     // the state of the instruction
     err = exec_instruction(state, inst);
     if(err != mips_Success) return err;
+    
+    if(state->debug_level > 0) {
+        fprintf(state->debug_type, "inst: %#10x\tpc: %d\tpc_next: %d\tdelay_slot: %d\n", inst, state->pc, state->next_pc, state->delay_slot);
+    }
 
     if(state->debug_level > 1) {
         fprintf(state->debug_type, "\nCPU register state after:\n");
@@ -189,6 +189,7 @@ mips_error exec_instruction(mips_cpu_h state, uint32_t inst) {
         var[REG_D] = (inst >> 11)&0x1f;
         var[SHIFT] = (inst >> 6)&0x1f;
         var[FUNC] = inst&0x3f;
+ 
         // execute R instruction to perform operation
         return exec_R(state, var);
         
@@ -211,7 +212,7 @@ mips_error exec_R(mips_cpu_h state, uint32_t var[8]) {
     // or subtraction
     if((var[FUNC]&0xf0) == ADD && (var[FUNC]&0xf) < 4) {
         // calls add with -1 if it is a subtractin and 1 if it is addition
-        return add_sub(state, var, ((int32_t)-(var[FUNC]&0xf)/2)*2+1, 0);
+                return add_sub(state, var, ((int32_t)-(var[FUNC]&0xf)/2)*2+1, 0);
         
     } else if((var[FUNC]&0xf0) == 0x20 && (var[FUNC]&0xf) < 7) {
         // else if the number is between 0x23 and 0x27 which means it
diff --git a/src/ymh15/mips_cpu.o b/src/ymh15/mips_cpu.o
index 25b3aa8..0455d62 100644
--- a/src/ymh15/mips_cpu.o
+++ b/src/ymh15/mips_cpu.o
diff --git a/src/ymh15/test_mips b/src/ymh15/test_mips
index d160c2a..31eb229 100755
--- a/src/ymh15/test_mips
+++ b/src/ymh15/test_mips
diff --git a/src/ymh15/test_mips.cpp b/src/ymh15/test_mips.cpp
index 75afaa8..6584882 100644
--- a/src/ymh15/test_mips.cpp
+++ b/src/ymh15/test_mips.cpp
@@ -1,482 +1,421 @@
-#include "../../include/mips.h"
 #include "test_mips_ymh15.hpp"
 
-#include <iostream>
-
-using namespace std;
-
 int main(int argc, char** argv) {
-    mips_mem_h ram = mips_mem_create_ram(4096);
-    mips_cpu_h cpu = mips_cpu_create(ram);
+    mips_mem_h test_ram = mips_mem_create_ram(0x20000000);
+    mips_cpu_h test_cpu = mips_cpu_create(test_ram);
+    int testId;
+    mips_error err;
 
     srand(time(NULL));
 
     if(argc == 2) {
-        mips_cpu_set_debug_level(cpu, argv[1][0]-'0', stdout);
+        mips_cpu_set_debug_level(test_cpu, argv[1][0]-'0', stdout);
     } else {
-        mips_cpu_set_debug_level(cpu, 0, NULL);
+        mips_cpu_set_debug_level(test_cpu, 0, NULL);
     }
 
     mips_test_begin_suite();
-    
-    int testId = mips_test_begin_test("ADD");
-    mips_test_end_test(testId, test_add(ram, cpu, ADD, 0x3fffffff, 0, 10), "Testing the adder without overflow");
 
+    testId = mips_test_begin_test("<INTERNAL>");
+    mips_cpu_set_register(test_cpu, 0, 0xf28ba9);
+    mips_test_end_test(testId, check_reg(test_cpu, 0, 0), "Testing if reg 0 = 0");
+
+    testId = mips_test_begin_test("<INTERNAL>");
+    mips_cpu_set_register(test_cpu, 27, 0xf28ba9);
+    mips_test_end_test(testId, check_reg(test_cpu, 27, 0xf28ba9), "Check if set register is actually set");
+
+    testId = mips_test_begin_test("<INTERNAL>");
+    mips_cpu_set_pc(test_cpu, 0x20);
+    mips_test_end_test(testId, check_reg(test_cpu, 255, 0x20), "Check if pc can be set and read");
+
+    testId = mips_test_begin_test("ADD");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, ADD);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0xfb29ce8);
+    mips_cpu_set_register(test_cpu, 10, 0x873bef);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0x1039d8d7), "Check basic add functionality");
+    
+    testId = mips_test_begin_test("ADD");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, ADD);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x7fffffff);
+    mips_cpu_set_register(test_cpu, 10, 0x7fffffff);
+    err = mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_error(err, mips_ExceptionArithmeticOverflow), "Checking if add handles overflow correctly by setting exception");
+    
     testId = mips_test_begin_test("ADD");
-    mips_test_end_test(testId, !test_add(ram, cpu, ADD, 0x7fffffff, 1, 1), "Testing the adder with overflow");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, ADD);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 8, 0xfa139c);
+    mips_cpu_set_register(test_cpu, 9, 0x7fffffff);
+    mips_cpu_set_register(test_cpu, 10, 0x7fffffff);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xfa139c), "Checking if add handles overflow correctly by not setting register");
+    
+    testId = mips_test_begin_test("ADDI");
+    set_instruction(test_ram, test_cpu, 0, ADDI, 9, 8, 0x29f2);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x194a2b);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0x19741d), "testing basic functionality of ADDI");
+    
+    testId = mips_test_begin_test("ADDI");
+    set_instruction(test_ram, test_cpu, 0, ADDI, 9, 8, 0xf293);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x193);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xfffff426), "Check if immediates are handled correctly by ADDI");
+
+    testId = mips_test_begin_test("ADDIU");
+    set_instruction(test_ram, test_cpu, 0, ADDIU, 9, 8, 0x2f9e);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x3f9e72b);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0x3fa16c9), "check basic functionality off ADDIU");
 
     testId = mips_test_begin_test("ADDU");
-    mips_test_end_test(testId, test_add(ram, cpu, ADDU, 0x3fffffff, 0, 10), "testing without overflow");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, ADDU);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0xeb2931);
+    mips_cpu_set_register(test_cpu, 10, 0x983be2);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0x1836513), "Checking basic functionality of ADDU");
 
     testId = mips_test_begin_test("ADDU");
-    mips_test_end_test(testId, test_add(ram, cpu, ADDU, 0x7fffffff, 1, 1), "Testing the adder with overflow");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, ADDU);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x7fffffff);
+    mips_cpu_set_register(test_cpu, 10, 0x7fffffff);
+    err = mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_error(err, mips_Success), "Checking if ADDU handles overflow correctly by not setting exception");
+    
+    testId = mips_test_begin_test("ADDU");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, ADDU);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x7fffffff);
+    mips_cpu_set_register(test_cpu, 10, 0x7fffffff);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xFFFFFFFE), "Checking if ADDU handles overflow correctly by setting register");
 
-    testId = mips_test_begin_test("SUB");
-    mips_test_end_test(testId, test_add(ram, cpu, SUB, 0x3fffffff, 0, 10), "Testing the adder without overflow");
+    testId = mips_test_begin_test("AND");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, AND);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0xf1e8ba2c);
+    mips_cpu_set_register(test_cpu, 10, 0xff8cf2e9);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xF188B228), "Testing functionality of AND");
 
-    testId = mips_test_begin_test("SUB");
-    mips_test_end_test(testId, !test_add(ram, cpu, SUB, 0x7fffffff, 1, 1), "Testing the adder with overflow");
+    testId = mips_test_begin_test("ANDI");
+    set_instruction(test_ram, test_cpu, 0, ANDI, 9, 8, 0xf293);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0xff928228);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0x8200), "Testing functionality of ANDI");
 
-    testId = mips_test_begin_test("SUBU");
-    mips_test_end_test(testId, test_add(ram, cpu, SUBU, 0x3fffffff, 0, 10), "Testing the adder without overflow");
+    testId = mips_test_begin_test("BEQ");
+    set_instruction(test_ram, test_cpu, 0, BEQ, 9, 8, 0x1f94);
+    set_instruction(test_ram, test_cpu, 4, 9, 8, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 8, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0x7e54, 10, 9, 10, 0, ADDU);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 8, 2);
+    mips_cpu_set_register(test_cpu, 9, 2);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 10, 6), "Testing basic functionality of BEQ");
 
-    testId = mips_test_begin_test("SUBU");
-    mips_test_end_test(testId, test_add(ram, cpu, SUBU, 0x7fffffff, 1, 1), "Testing the adder with overflow");
+    testId = mips_test_begin_test("BGEZ");
+    set_instruction(test_ram, test_cpu, 0, BGEZ, 8, 1, 0x1f94);
+    set_instruction(test_ram, test_cpu, 4, 9, 8, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 8, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0x7e54, 10, 9, 10, 0, ADDU);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 8, 2);
+    mips_cpu_set_register(test_cpu, 9, 2);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 10, 6), "Testing basic functionality of BGEZ");
 
-    testId = mips_test_begin_test("AND");
-    mips_test_end_test(testId, test_bitwise(ram, cpu, AND), "Testing bitwise and");
+    testId = mips_test_begin_test("BGEZAL");
+    set_instruction(test_ram, test_cpu, 0, BGEZAL, 8, 0x11, 0x1f94);
+    set_instruction(test_ram, test_cpu, 4, 9, 8, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 8, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0x7e54, 10, 9, 10, 0, ADDU);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 8, 2);
+    mips_cpu_set_register(test_cpu, 9, 2);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 31, 8), "check if the link works on BGEZAL");
 
-    testId = mips_test_begin_test("OR");
-    mips_test_end_test(testId, test_bitwise(ram, cpu, OR), "Testing bitwise or");
+    testId = mips_test_begin_test("BGTZ");
+    set_instruction(test_ram, test_cpu, 0, BGTZ, 8, 0, 0x1f94);
+    set_instruction(test_ram, test_cpu, 4, 9, 8, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 8, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0x7e54, 10, 9, 10, 0, ADDU);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 8, 2);
+    mips_cpu_set_register(test_cpu, 9, 2);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 10, 6), "Testing basic functionality of BGTZ");
 
-    testId = mips_test_begin_test("XOR");
-    mips_test_end_test(testId, test_bitwise(ram, cpu, XOR), "Testing bitwise xor");
+    testId = mips_test_begin_test("BLEZ");
+    set_instruction(test_ram, test_cpu, 0, BLEZ, 8, 0, 0x1f94);
+    set_instruction(test_ram, test_cpu, 4, 9, 8, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 8, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0x7e54, 10, 8, 10, 0, ADDU);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 8, 0);
+    mips_cpu_set_register(test_cpu, 9, 2);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 10, 2), "Testing functionality of BLEZ");
 
-    testId = mips_test_begin_test("ADDI");
-    mips_test_end_test(testId, test_I(ram, cpu, ADDI, 20, 10), "Testing addi");
-    
-    testId = mips_test_begin_test("ADDIU");
-    mips_test_end_test(testId, test_I(ram, cpu, ADDIU, 20, 10), "Testing addiu");
-    
-    testId = mips_test_begin_test("ANDI");
-    mips_test_end_test(testId, test_I(ram, cpu, ANDI, 20, 10), "Testing addi");
-    
-    testId = mips_test_begin_test("ORI");
-    mips_test_end_test(testId, test_I(ram, cpu, ORI, 20, 10), "Testing addi");
-    
-    testId = mips_test_begin_test("XORI");
-    mips_test_end_test(testId, test_I(ram, cpu, XORI, 20, 10), "Testing addi");
+    testId = mips_test_begin_test("BLTZ");
+    set_instruction(test_ram, test_cpu, 0, BLTZ, 7, 0, 0x1f94);
+    set_instruction(test_ram, test_cpu, 4, 9, 8, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 8, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0x7e54, 10, 9, 10, 0, ADDU);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 7, 0xffffffff);
+    mips_cpu_set_register(test_cpu, 8, 2);
+    mips_cpu_set_register(test_cpu, 9, 2);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 10, 6), "Testing functionality of BLTZ");
 
-    testId = mips_test_begin_test("BEQ");
-    mips_test_end_test(testId, test_branch(ram, cpu, 4, 4, 0, 9, 4), "Testing BEQ");
+    testId = mips_test_begin_test("BLTZAL");
+    set_instruction(test_ram, test_cpu, 0, BLTZAL, 7, 0x10, 0x1f94);
+    set_instruction(test_ram, test_cpu, 4, 9, 8, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 8, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0x7e54, 10, 9, 10, 0, ADDU);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 7, 0xffffffff);
+    mips_cpu_set_register(test_cpu, 8, 2);
+    mips_cpu_set_register(test_cpu, 9, 2);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 31, 8), "Testing if BLTZAL links");
 
     testId = mips_test_begin_test("BNE");
-    mips_test_end_test(testId, test_branch(ram, cpu, 5, 4, 0, 9, 10), "Testing BNE");
+    set_instruction(test_ram, test_cpu, 0, BNE, 9, 7, 0x1f94);
+    set_instruction(test_ram, test_cpu, 4, 9, 8, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 8, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0x7e54, 10, 9, 10, 0, ADDU);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 7, 3);
+    mips_cpu_set_register(test_cpu, 8, 2);
+    mips_cpu_set_register(test_cpu, 9, 2);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 10, 6), "Testing BNE");
 
-    testId = mips_test_begin_test("BGEZ");
-    mips_test_end_test(testId, test_branch(ram, cpu, 1, 4, 0, 1, 20), "Testing BGEZ");
-    
-    testId = mips_test_begin_test("BLEZ");
-    mips_test_end_test(testId, test_branch(ram, cpu, 6, -1, 0, 0, 20), "Testing BGEZ");
+    testId = mips_test_begin_test("DIV");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 0, 0, DIV);
+    set_instruction(test_ram, test_cpu, 4, 0, 0, 8, 0, MFLO);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, -39);
+    mips_cpu_set_register(test_cpu, 10, 4);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, -9), "Test DIV Quotient");
     
-    testId = mips_test_begin_test("BGTZ");
-    mips_test_end_test(testId, test_branch(ram, cpu, 7, 4, 0, 0, 20), "Testing BGEZ");
+    testId = mips_test_begin_test("DIV");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 0, 0, DIV);
+    set_instruction(test_ram, test_cpu, 4, 0, 0, 8, 0, MFHI);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, -39);
+    mips_cpu_set_register(test_cpu, 10, 4);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, -3), "Test DIV remainder");
+
+    testId = mips_test_begin_test("DIVU");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 0, 0, DIVU);
+    set_instruction(test_ram, test_cpu, 4, 0, 0, 8, 0, MFLO);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, -39);
+    mips_cpu_set_register(test_cpu, 10, 4);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0x3FFFFFF6), "Test DIVU Quotient");
+
+    testId = mips_test_begin_test("DIVU");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 0, 0, DIVU);
+    set_instruction(test_ram, test_cpu, 4, 0, 0, 8, 0, MFHI);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, -39);
+    mips_cpu_set_register(test_cpu, 10, 4);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 1), "Test DIVU remainder");
 
-    testId = mips_test_begin_test("BGEZAL");
-    mips_test_end_test(testId, test_branch(ram, cpu, 1, 4, 1, 17, 20), "Testing BGEZ");
-    
-    testId = mips_test_begin_test("BLTZAL");
-    mips_test_end_test(testId, test_branch(ram, cpu, 1, -1, 1, 16, 20), "Testing BGEZ");
-    
-    testId = mips_test_begin_test("BLTZ");
-    mips_test_end_test(testId, test_branch(ram, cpu, 1, -1, 0, 16, 20), "Testing BGEZ");
-    
     testId = mips_test_begin_test("J");
-    mips_test_end_test(testId, test_jump(ram, cpu, J), "Testing J");
-    
+    mips_cpu_reset(test_cpu);
+    set_instruction(test_ram, test_cpu, 0, J, 0x298c2);
+    set_instruction(test_ram, test_cpu, 4, 9, 8, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 8, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0xa6308, 10, 8, 10, 0, ADDU);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 8, 2);
+    mips_cpu_set_register(test_cpu, 9, 2);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 10, 6), "Checking basic jump");
+
     testId = mips_test_begin_test("JAL");
-    mips_test_end_test(testId, test_jump(ram, cpu, JAL), "Testing JAL");
-    
+    mips_cpu_reset(test_cpu);
+    set_instruction(test_ram, test_cpu, 4, JAL, 0x298c2);
+    set_instruction(test_ram, test_cpu, 8, 9, 8, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0xc, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0xa6308, 10, 8, 10, 0, ADDU);
+    mips_cpu_set_pc(test_cpu, 4);
+    mips_cpu_set_register(test_cpu, 8, 2);
+    mips_cpu_set_register(test_cpu, 9, 2);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 31, 0xc), "checking if J links correctly");
+
     testId = mips_test_begin_test("JALR");
-    mips_test_end_test(testId, test_jump(ram, cpu, JALR), "Testing JALR");
-    
+    set_instruction(test_ram, test_cpu, 4, 7, 0, 31, 0, JALR);
+    set_instruction(test_ram, test_cpu, 8, 9, 8, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0xc, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0xa6308, 10, 8, 10, 0, ADDU);
+    mips_cpu_set_pc(test_cpu, 4);
+    mips_cpu_set_register(test_cpu, 7, 0xa6308);
+    mips_cpu_set_register(test_cpu, 8, 2);
+    mips_cpu_set_register(test_cpu, 9, 2);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 31, 0xc), "Checking if JALR links correctly");
+
     testId = mips_test_begin_test("JR");
-    mips_test_end_test(testId, test_jump(ram, cpu, JR), "Testing JR");
-    
-    testId = mips_test_begin_test("LB");
-    mips_test_end_test(testId, test_load(ram, cpu, LB, 0xf7), "Testing LB");
-    
-    testId = mips_test_begin_test("LBU");
-    mips_test_end_test(testId, test_load(ram, cpu, LBU, 0xf7), "Testing LBU");
-    
-    testId = mips_test_begin_test("LH");
-    mips_test_end_test(testId, test_load(ram, cpu, LH, 0xff7f), "Testing LH");
-    
-    testId = mips_test_begin_test("LHU");
-    mips_test_end_test(testId, test_load(ram, cpu, LHU, 0xff7f), "Testing LHU");
-    
-    testId = mips_test_begin_test("LW");
-    mips_test_end_test(testId, test_load(ram, cpu, LW, 0xffffff7f), "Testing LW");
-    
-    testId = mips_test_begin_test("LUI");
-    mips_test_end_test(testId, test_load(ram, cpu, LUI, 0xff7f), "Testing LUI");
-    
-    testId = mips_test_begin_test("LWL");
-    mips_test_end_test(testId, test_load(ram, cpu, LWL, 0xff6fff7f), "Testing LWL");
-    
-    testId = mips_test_begin_test("LWR");
-    mips_test_end_test(testId, test_load(ram, cpu, LWR, 0xff6fff7f), "Testing LWR");
-    
-    testId = mips_test_begin_test("MULT");
-    mips_test_end_test(testId, test_mult_div(ram, cpu, MULT, 5, -4), "Testing LWR");
-    
-    testId = mips_test_begin_test("MULTU");
-    mips_test_end_test(testId, test_mult_div(ram, cpu, MULTU, 5, -4), "Testing LWR");
-    
-    testId = mips_test_begin_test("DIV");
-    mips_test_end_test(testId, test_mult_div(ram, cpu, DIV, 5, -4), "Testing LWR");
+    set_instruction(test_ram, test_cpu, 4, 7, 0, 0, 0, JR);
+    set_instruction(test_ram, test_cpu, 8, 9, 8, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0xc, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0xa6308, 10, 8, 10, 0, ADDU);
+    mips_cpu_set_pc(test_cpu, 4);
+    mips_cpu_set_register(test_cpu, 7, 0xa6308);
+    mips_cpu_set_register(test_cpu, 8, 2);
+    mips_cpu_set_register(test_cpu, 9, 2);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 10, 6), "Checking if JR jumps correctly");
 
-    testId = mips_test_begin_test("DIVU");
-    mips_test_end_test(testId, test_mult_div(ram, cpu, DIVU, 5, -4), "Testing LWR");
-    
-    mips_test_end_suite();
-    return 0;
-}
+    testId = mips_test_begin_test("LB");
+    mips_test_end_test(testId, 0, "");
 
-// R Type
-uint32_t gen_instruction(uint32_t src1, uint32_t src2, uint32_t dest,
-                     uint32_t shift, uint32_t function) {
-    uint32_t inst = 0;
-    inst = inst | src1 << 21 | src2 << 16 | dest << 11 | shift << 6 |
-        function;
-    return inst;
-}
+    testId = mips_test_begin_test("LBU");
+    mips_test_end_test(testId, 0, "");
 
-// I Type
-uint32_t gen_instruction(uint32_t opcode, uint32_t src, uint32_t dest,
-                     uint32_t Astart) {
-    uint32_t inst = 0;
-    inst = inst | opcode << 26 | src << 21 | dest << 16 | Astart;
-    return inst;
-}
+    testId = mips_test_begin_test("LH");
+    mips_test_end_test(testId, 0, "");
 
-// J Type
-uint32_t gen_instruction(uint32_t opcode, uint32_t memory) {
-    uint32_t inst = 0;
-    inst = inst | opcode << 26 | memory;
-    return inst;
-}
+    testId = mips_test_begin_test("LHU");
+    mips_test_end_test(testId, 0, "");
 
-uint32_t change_endianness(uint32_t inst) {
-    inst = (inst << 24 | ((inst << 8)&0xff0000) |
-            ((inst >> 8)&0xff00) |inst >> 24);
-    return inst;
-}
+    testId = mips_test_begin_test("LUI");
+    mips_test_end_test(testId, 0, "");
 
-int test_add(mips_mem_h ram, mips_cpu_h cpu, uint32_t type, uint32_t max, uint8_t value, unsigned i_t) {
-    
-    uint32_t inst, ans, a, b;
-
-    for(unsigned i = 0; i < i_t; ++i) {
-        mips_error mips_err;
-        mips_cpu_reset(cpu);
-        inst = change_endianness(gen_instruction(9, 10, 8, 0, type));
-        if(value) {
-            a = max;
-            if(type > 0x21) {
-                b = -max;
-            } else {
-                b = max;
-            }
-        } else {
-            a = rand() % max;
-            b = rand() % max;
-        }
-        
-        mips_mem_write(ram, 0, 4, (uint8_t*)&inst);
-        
-        mips_cpu_set_register(cpu, 9, a);
-        mips_cpu_set_register(cpu, 10, b);
-    
-        mips_err = mips_cpu_step(cpu);
-    
-        mips_cpu_get_register(cpu, 8, &ans);
-
-        if(type < 0x22) {
-            //printf("%#10x + %#10x = %#10x\t%#10x\n", a, b, ans, mips_err);
-            if(mips_err == mips_ExceptionArithmeticOverflow || a+b!=ans) {
-                return 0;
-            }
-        } else {
-            //printf("%#10x - %#10x = %#10x\t%#10x\n", a, b, ans, mips_err);
-            if(mips_err == mips_ExceptionArithmeticOverflow || a-b!=ans) {
-                return 0;
-            }
-        }
-    }
+    testId = mips_test_begin_test("LW");
+    mips_test_end_test(testId, 0, "");
 
-    return 1;
-}
+    testId = mips_test_begin_test("LWL");
+    mips_test_end_test(testId, 0, "");
 
-int test_bitwise(mips_mem_h ram, mips_cpu_h cpu, uint8_t op) {
-    uint32_t a, b, ans, inst;
-    int passed;
-    for(unsigned i = 0; i < 10; ++i) {
-        passed = 0;
-        mips_cpu_reset(cpu);
-        inst = change_endianness(gen_instruction(8, 9, 7, 0, op));
-
-        a = rand() % 0xffffffff;
-        b = rand() % 0xffffffff;
-
-        mips_mem_write(ram, 0, 4, (uint8_t*)&inst);
-
-        mips_cpu_set_register(cpu, 8, a);
-        mips_cpu_set_register(cpu, 9, b);
-
-        mips_error mips_err = mips_cpu_step(cpu);
-
-        mips_cpu_get_register(cpu, 7, &ans);
-
-        if(op == AND) {
-            //printf("%#10x & %#10x = %#10x\t%#10x\n", a, b, ans, mips_err);
-            if((a & b) == ans) {
-                passed = 1;
-            }
-        } else if(op == OR) {
-            //printf("%#10x | %#10x = %#10x\t%#10x\n", a, b, ans, mips_err);
-            if((a | b) == ans) {
-                passed = 1;
-            }
-        } else {
-            //printf("%#10x ^ %#10x = %#10x\t%#10x\n", a, b, ans, mips_err);
-            if((a ^ b) == ans) {
-                passed = 1;
-            }
-        }
-
-        
-        if(mips_err != mips_Success || !passed) {
-            return 0;
-        }
-    }
-    return 1;
-}
+    testId = mips_test_begin_test("LWR");
+    mips_test_end_test(testId, 0, "");
 
-int test_I(mips_mem_h ram, mips_cpu_h cpu, uint32_t type,
-             uint32_t num1, uint32_t num2) {
-    int passed = 0;
-    uint32_t result, inst;
-
-    mips_cpu_reset(cpu);
-    inst = change_endianness(gen_instruction(type, 8, 7, num1));
-
-    mips_mem_write(ram, 0, 4, (uint8_t*)&inst);
-    mips_cpu_set_register(cpu, 8, num2);
-
-    mips_cpu_step(cpu);
-
-    mips_cpu_get_register(cpu, 7, &result);
-
-    switch(type) {
-    case 8:
-        if(result == num1 + num2) {
-            passed = 1;
-        }
-    case 9:
-        if(result == num1 + num2) {
-            passed = 1;
-        }
-    case 12:
-        if(result == (num1 & num2)) {
-            passed = 1;
-        }
-    case 13:
-        if(result == (num1 | num2)) {
-            passed = 1;
-        }
-    case 14:
-        if(result == (num1 ^ num2)) {
-            passed = 1;
-        }
-    default:;
-    }
+    testId = mips_test_begin_test("MFHI");
+    mips_test_end_test(testId, 0, "");
 
-    return passed;
-}
+    testId = mips_test_begin_test("MFLO");
+    mips_test_end_test(testId, 0, "");
 
-int test_branch(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode, uint32_t a, uint8_t l, uint32_t opc2, uint32_t b) {
-    int passed = 0;
-    int pass = 0;
-    uint32_t reg10, reg11, reg31, pc_set;
-    pc_set = 32;
-    mips_cpu_reset(cpu);
-    mips_cpu_set_pc(cpu, pc_set);
-
-    uint32_t inst = change_endianness(gen_instruction(opcode, 8, opc2, 3));
-    mips_mem_write(ram, pc_set, 4, (uint8_t*)&inst);
-    inst = change_endianness(gen_instruction(8, 9, 10, 0, ADDU));
-    mips_mem_write(ram, pc_set+4, 4, (uint8_t*)&inst);
-    inst = change_endianness(gen_instruction(8, 12, 11, 0, ADDU));
-    mips_mem_write(ram, pc_set+16, 4, (uint8_t*)&inst);
-    inst = change_endianness(gen_instruction(8, 13, 10, 0, ADDU));
-    mips_mem_write(ram, pc_set+8, 4, (uint8_t*)&inst);
-
-    mips_cpu_set_register(cpu, 8, a);
-    mips_cpu_set_register(cpu, 9, b);
-    mips_cpu_set_register(cpu, 12, 30);
-    mips_cpu_set_register(cpu, 13, 100);
-
-    mips_cpu_step(cpu);
-    mips_cpu_step(cpu);
-    mips_cpu_step(cpu);
-
-    mips_cpu_get_register(cpu, 10, &reg10);
-    mips_cpu_get_register(cpu, 11, &reg11);
-
-    if(l == 1) {
-        mips_cpu_get_register(cpu, 31, &reg31);
-        if(reg31 == pc_set+8) {
-            pass = 1;
-        }
-    } else {
-        pass = 1;
-    }
+    testId = mips_test_begin_test("MTHI");
+    mips_test_end_test(testId, 0, "");
 
-    if(reg10 == a+b && reg11 == a+30 && pass) {
-        passed = 1;
-    } else {
-        passed = 0;
-    }
-    
-    return passed;
-}
+    testId = mips_test_begin_test("MTLO");
+    mips_test_end_test(testId, 0, "");
 
-int test_jump(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode) {
-    int passed = 0;
-    uint32_t inst, reg10, reg13, reg16, reg31;
+    testId = mips_test_begin_test("MULT");
+    mips_test_end_test(testId, 0, "");
 
-    mips_cpu_reset(cpu);
+    testId = mips_test_begin_test("MULTU");
+    mips_test_end_test(testId, 0, "");
 
-    if(opcode == 2 || opcode == 3) {
-        inst = change_endianness(gen_instruction(opcode, 0x20));
-    } else if(opcode == 8 || opcode == 9) {
-        inst = change_endianness(gen_instruction(25, 0, 31, 0, opcode));
-    }
+    testId = mips_test_begin_test("OR");
+    mips_test_end_test(testId, 0, "");
 
-    mips_mem_write(ram, 0, 4, (uint8_t*)&inst);
-
-    inst = change_endianness(gen_instruction(8, 9, 10, 0, ADDU));
-    mips_mem_write(ram, 4, 4, (uint8_t*)&inst);
-    inst = change_endianness(gen_instruction(11, 12, 13, 0, ADDU));
-    mips_mem_write(ram, 8, 4, (uint8_t*)&inst);
-    inst = change_endianness(gen_instruction(14, 15, 16, 0, ADDU));
-    mips_mem_write(ram, 0x20<<2, 4, (uint8_t*)&inst);
-
-    mips_cpu_set_register(cpu, 8, 8);
-    mips_cpu_set_register(cpu, 9, 9);
-    mips_cpu_set_register(cpu, 10, 10);
-    mips_cpu_set_register(cpu, 11, 11);
-    mips_cpu_set_register(cpu, 12, 12);
-    mips_cpu_set_register(cpu, 13, 13);
-    mips_cpu_set_register(cpu, 14, 14);
-    mips_cpu_set_register(cpu, 15, 15);
-    mips_cpu_set_register(cpu, 16, 16);
-    mips_cpu_set_register(cpu, 25, 0x20<<2);
-
-    mips_cpu_step(cpu);
-    mips_cpu_step(cpu);
-    mips_cpu_step(cpu);
-
-    mips_cpu_get_register(cpu, 10, &reg10);
-    mips_cpu_get_register(cpu, 13, &reg13);
-    mips_cpu_get_register(cpu, 16, &reg16);
-    mips_cpu_get_register(cpu, 31, &reg31);
-
-    if(reg10 == 9+8 && reg13 == 13 && reg16 == 14+15) {
-        passed = 1;
-    }
-    
-    if((opcode == 3 || opcode == 9) && reg31 != 8) {
-        passed = 0;
-    }
+    testId = mips_test_begin_test("ORI");
+    mips_test_end_test(testId, 0, "");
 
-    return passed;
-}
+    testId = mips_test_begin_test("SB");
+    mips_test_end_test(testId, 0, "");
 
-int test_load(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode, uint32_t word) {
-    int passed = 0;
-    uint16_t half_word;
-    uint8_t byte;
-    uint32_t res;
+    testId = mips_test_begin_test("SH");
+    mips_test_end_test(testId, 0, "");
 
-    half_word = (uint16_t)word;
-    byte = (uint8_t)word;
+    testId = mips_test_begin_test("SLL");
+    mips_test_end_test(testId, 0, "");
 
-    mips_cpu_reset(cpu);
+    testId = mips_test_begin_test("SLLV");
+    mips_test_end_test(testId, 0, "");
 
-    uint32_t inst = change_endianness(gen_instruction(opcode, 8, 9, 4));
+    testId = mips_test_begin_test("SLT");
+    mips_test_end_test(testId, 0, "");
 
-    mips_mem_write(ram, 0, 4, (uint8_t*)&inst);
-    
-    if(opcode == LB || opcode == LBU) {
-        mips_mem_write(ram, 0x30, 1, &byte);
-    } else if(opcode == LH || opcode == LHU) {
-        uint16_t tmp = (half_word<<8) | (half_word>>8);
-        mips_mem_write(ram, 0x30, 2, (uint8_t*)&tmp);
-    } else {
-        uint32_t tmp = change_endianness(word);
-        mips_mem_write(ram, 0x30, 4, (uint8_t*)&tmp);
-    }
+    testId = mips_test_begin_test("SLTI");
+    mips_test_end_test(testId, 0, "");
 
-    mips_cpu_set_register(cpu, 8, 0x2c);
-    if(opcode == LWR) {
-        mips_cpu_set_register(cpu, 8, 0x2f);
-    }
-    mips_cpu_set_register(cpu, 9, 0xbabacdcd);
+    testId = mips_test_begin_test("SLTIU");
+    mips_test_end_test(testId, 0, "");
 
-    mips_cpu_step(cpu);
-    
-    mips_cpu_get_register(cpu, 9, &res);
+    testId = mips_test_begin_test("SLTU");
+    mips_test_end_test(testId, 0, "");
 
-    if((res == (uint32_t)(int8_t)byte && opcode == LB) || (res == (uint32_t)byte && opcode == LBU) || (res == (uint32_t)(int16_t)half_word && opcode == LH) || (res == (uint32_t)half_word && opcode == LHU) || (res == word && opcode == LW) || (res == 4<<16 && opcode == LUI) || (res == ((word&0xffff)|(0xbaba0000)) && (opcode == LWR)) || (res == ((word&0xffff0000)|(0xcdcd)))) {
-        passed = 1;
-    }
+    testId = mips_test_begin_test("SRA");
+    mips_test_end_test(testId, 0, "");
 
-    return passed;
-}
+    testId = mips_test_begin_test("SRAV");
+    mips_test_end_test(testId, 0, "");
 
-int test_mult_div(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode, uint32_t num1, uint32_t num2) {
-    int passed = 0;
-    uint64_t result;
-    uint32_t hi, lo;
+    testId = mips_test_begin_test("SRL");
+    mips_test_end_test(testId, 0, "");
 
-    mips_cpu_reset(cpu);
-    
-    uint32_t inst = change_endianness(gen_instruction(8, 9, 0, 0, opcode));
-    mips_mem_write(ram, 0, 4, (uint8_t*)&inst);
-    inst = change_endianness(gen_instruction(0, 0, 10, 0, MFHI));
-    mips_mem_write(ram, 4, 4, (uint8_t*)&inst);
-    inst = change_endianness(gen_instruction(0, 0, 11, 0, MFLO));
-    mips_mem_write(ram, 8, 4, (uint8_t*)&inst);
+    testId = mips_test_begin_test("SRLV");
+    mips_test_end_test(testId, 0, "");
 
-    mips_cpu_set_register(cpu, 8, num1);
-    mips_cpu_set_register(cpu, 9, num2);
-    mips_cpu_set_register(cpu, 10, 0xabcde);
-    mips_cpu_set_register(cpu, 11, 0xf193b);
+    testId = mips_test_begin_test("SUB");
+    mips_test_end_test(testId, 0, "");
 
-    mips_cpu_step(cpu);
-    mips_cpu_step(cpu);
-    mips_cpu_step(cpu);
+    testId = mips_test_begin_test("SUBU");
+    mips_test_end_test(testId, 0, "");
 
-    mips_cpu_get_register(cpu, 10, &hi);
-    mips_cpu_get_register(cpu, 11, &lo);
+    testId = mips_test_begin_test("SW");
+    mips_test_end_test(testId, 0, "");
 
-    result = (((uint64_t)hi)<<32) | ((uint64_t)lo);
+    testId = mips_test_begin_test("XOR");
+    mips_test_end_test(testId, 0, "");
 
-    if((opcode == MULT && result == (uint64_t)((int64_t)(int32_t)num1*(int64_t)(int32_t)num2)) || (opcode == MULTU && result == (uint64_t)((uint32_t)num1)*(uint32_t)num2) || (opcode == DIV && lo == (uint32_t)((int32_t)num1/(int32_t)num2) && hi == (uint32_t)((int32_t)num1%(int32_t)num2)) || (opcode == DIVU && lo == num1/num2 && hi == num1%num2)) {
-        passed = 1;
-    }
+    testId = mips_test_begin_test("XORI");
+    mips_test_end_test(testId, 0, "");
 
-    return passed;
+    mips_test_end_suite();
+    
+    return 0;
 }
diff --git a/src/ymh15/test_mips.o b/src/ymh15/test_mips.o
index 32a3fd1..df436de 100644
--- a/src/ymh15/test_mips.o
+++ b/src/ymh15/test_mips.o
diff --git a/src/ymh15/test_mips_ymh15.cpp b/src/ymh15/test_mips_ymh15.cpp
new file mode 100644
index 0000000..c2fb588
--- /dev/null
+++ b/src/ymh15/test_mips_ymh15.cpp
@@ -0,0 +1,101 @@
+#include "test_mips_ymh15.hpp"
+
+// R Type
+uint32_t gen_instruction(uint32_t src1, uint32_t src2, uint32_t dest,
+                     uint32_t shift, uint32_t function) {
+    uint32_t inst = 0;
+    inst = inst | src1 << 21 | src2 << 16 | dest << 11 | shift << 6 |
+        function;
+    return inst;
+}
+
+// I Type
+uint32_t gen_instruction(uint32_t opcode, uint32_t src, uint32_t dest,
+                     uint32_t Astart) {
+    uint32_t inst = 0;
+    inst = inst | opcode << 26 | src << 21 | dest << 16 | Astart;
+    return inst;
+}
+
+// J Type
+uint32_t gen_instruction(uint32_t opcode, uint32_t memory) {
+    uint32_t inst = 0;
+    inst = inst | opcode << 26 | memory;
+    return inst;
+}
+
+void change_endianness(uint32_t &inst) {
+    inst = (inst << 24 | ((inst << 8)&0xff0000) |
+            ((inst >> 8)&0xff00) |inst >> 24);
+}
+
+int check_reg(mips_cpu_h state, uint8_t reg_addr, uint32_t check_value) {
+    uint32_t reg;
+
+    if(reg_addr != 255)
+        mips_cpu_get_register(state, reg_addr, &reg);
+    else
+        mips_cpu_get_pc(state, &reg);
+
+    if(reg == check_value)
+        return 1;
+
+    printf("Value of reg%d: %#10x\tExpected value: %#10x\n", reg_addr, reg, check_value);
+    return 0;
+}
+
+int check_error(mips_error err, mips_error expected_err) {
+    if(err == expected_err) {
+        return 1;
+    }
+
+    printf("Received error: %#6x\tExpected error: %#6x\n", err, expected_err);
+    return 0;
+}
+
+mips_error set_instruction(mips_mem_h mem, mips_cpu_h state, uint32_t mem_location, uint32_t src1, uint32_t src2, uint32_t dest, uint32_t shift, uint32_t function) {
+    uint32_t inst;
+    mips_error err;
+
+    rand_reg(state);
+    inst = gen_instruction(src1, src2, dest, shift, function);
+    change_endianness(inst);
+    err = mips_mem_write(mem, mem_location, 4, (uint8_t*)&inst);
+    return err;
+}
+
+mips_error set_instruction(mips_mem_h mem, mips_cpu_h state, uint32_t mem_location, uint32_t opcode, uint32_t src, uint32_t dest, uint32_t Astart) {
+    uint32_t inst;
+    mips_error err;
+
+    rand_reg(state);
+    inst = gen_instruction(opcode, src, dest, Astart);
+    change_endianness(inst);
+    err = mips_mem_write(mem, mem_location, 4, (uint8_t*)&inst);
+    if(err != mips_Success) {
+        printf("couln't write...\n");
+    }
+    return err;
+}
+
+mips_error set_instruction(mips_mem_h mem, mips_cpu_h state, uint32_t mem_location, uint32_t opcode, uint32_t memory) {
+    uint32_t inst;
+    mips_error err;
+
+    rand_reg(state);
+    inst = gen_instruction(opcode, memory);
+    change_endianness(inst);
+    err = mips_mem_write(mem, mem_location, 4, (uint8_t*)&inst);
+    return err;
+
+}
+
+mips_error rand_reg(mips_cpu_h state) {
+    mips_error err;
+    for(unsigned i = 1; i < 32; ++i) {
+        err = mips_cpu_set_register(state, i, rand()%0xffffffff);
+        if(err != mips_Success)
+            return err;
+    }
+    return mips_Success;
+}
diff --git a/src/ymh15/test_mips_ymh15.hpp b/src/ymh15/test_mips_ymh15.hpp
index ca9f9fe..bd360f1 100644
--- a/src/ymh15/test_mips_ymh15.hpp
+++ b/src/ymh15/test_mips_ymh15.hpp
@@ -63,21 +63,19 @@
 #define SH 0x29
 #define SW 0x2b
 
-uint32_t gen_instruction(uint32_t src1, uint32_t src2, uint32_t dest,
-                         uint32_t shift, uint32_t function);
-uint32_t gen_instruction(uint32_t opcode, uint32_t src, uint32_t dest,
-                         uint32_t Astart);
+uint32_t gen_instruction(uint32_t src1, uint32_t src2, uint32_t dest, uint32_t shift, uint32_t function);
+uint32_t gen_instruction(uint32_t opcode, uint32_t src, uint32_t dest, uint32_t Astart);
 uint32_t gen_instruction(uint32_t opcode, uint32_t memory);
-uint32_t change_endianness(uint32_t inst);
 
-int test_add(mips_mem_h ram, mips_cpu_h cpu, uint32_t type, uint32_t max,
-             uint8_t value, unsigned i_t);
-int test_bitwise(mips_mem_h ram, mips_cpu_h cpu, uint8_t op);
-int test_I(mips_mem_h ram, mips_cpu_h cpu, uint32_t type, uint32_t num1,
-              uint32_t num2);
-int test_branch(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode, uint32_t a, uint8_t l, uint32_t opc2, uint32_t b);
-int test_jump(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode);
-int test_load(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode, uint32_t word);
-int test_mult_div(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode, uint32_t num1, uint32_t num2);
+void change_endianness(uint32_t &inst);
 
-#endif // TEST_MIPS_YMH15_H
+int check_reg(mips_cpu_h state, uint8_t reg_addr, uint32_t check_value);
+int check_error(mips_error err, mips_error expected_err);
+
+mips_error set_instruction(mips_mem_h mem, mips_cpu_h state, uint32_t mem_location, uint32_t src1, uint32_t src2, uint32_t dest, uint32_t shift, uint32_t function);
+mips_error set_instruction(mips_mem_h mem, mips_cpu_h state, uint32_t mem_location, uint32_t opcode, uint32_t src, uint32_t dest, uint32_t Astart);
+mips_error set_instruction(mips_mem_h mem, mips_cpu_h state, uint32_t mem_location, uint32_t opcode, uint32_t memory);
+
+mips_error rand_reg(mips_cpu_h state);
+
+#endif
diff --git a/src/ymh15/test_mips_ymh15.o b/src/ymh15/test_mips_ymh15.o
new file mode 100644
index 0000000..c10aac7
--- /dev/null
+++ b/src/ymh15/test_mips_ymh15.o