finished cpu and tester

8 files changed, 431 insertions, 34 deletions

diff --git a/src/ymh15/test_mips b/src/ymh15/test_mips
index 31eb229..36c0938 100755
--- a/src/ymh15/test_mips
+++ b/src/ymh15/test_mips
diff --git a/src/ymh15/test_mips.cpp b/src/ymh15/test_mips.cpp
index 6584882..716e874 100644
--- a/src/ymh15/test_mips.cpp
+++ b/src/ymh15/test_mips.cpp
@@ -5,6 +5,9 @@ int main(int argc, char** argv) {
     mips_cpu_h test_cpu = mips_cpu_create(test_ram);
     int testId;
     mips_error err;
+    uint8_t byte;
+    uint16_t halfword;
+    uint32_t word;
 
     srand(time(NULL));
 
@@ -126,6 +129,19 @@ int main(int argc, char** argv) {
     mips_cpu_step(test_cpu);
     mips_test_end_test(testId, check_reg(test_cpu, 10, 6), "Testing basic functionality of BEQ");
 
+    testId = mips_test_begin_test("BEQ");
+    set_instruction(test_ram, test_cpu, 0x200, BEQ, 9, 8, 0xff94);
+    set_instruction(test_ram, test_cpu, 0x204, 9, 8, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0x208, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0x54, 10, 9, 10, 0, ADDU);
+    mips_cpu_set_pc(test_cpu, 0x200);
+    mips_cpu_set_register(test_cpu, 8, 2);
+    mips_cpu_set_register(test_cpu, 9, 2);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 10, 6), "Testing negative branch with BEQ");
+
     testId = mips_test_begin_test("BGEZ");
     set_instruction(test_ram, test_cpu, 0, BGEZ, 8, 1, 0x1f94);
     set_instruction(test_ram, test_cpu, 4, 9, 8, 10, 0, ADDU);
@@ -229,7 +245,8 @@ int main(int argc, char** argv) {
     mips_cpu_step(test_cpu);
     mips_cpu_step(test_cpu);
     mips_test_end_test(testId, check_reg(test_cpu, 8, -9), "Test DIV Quotient");
-    
+
+    // DIV
     testId = mips_test_begin_test("DIV");
     set_instruction(test_ram, test_cpu, 0, 9, 10, 0, 0, DIV);
     set_instruction(test_ram, test_cpu, 4, 0, 0, 8, 0, MFHI);
@@ -240,6 +257,7 @@ int main(int argc, char** argv) {
     mips_cpu_step(test_cpu);
     mips_test_end_test(testId, check_reg(test_cpu, 8, -3), "Test DIV remainder");
 
+    // DIVU
     testId = mips_test_begin_test("DIVU");
     set_instruction(test_ram, test_cpu, 0, 9, 10, 0, 0, DIVU);
     set_instruction(test_ram, test_cpu, 4, 0, 0, 8, 0, MFLO);
@@ -260,6 +278,7 @@ int main(int argc, char** argv) {
     mips_cpu_step(test_cpu);
     mips_test_end_test(testId, check_reg(test_cpu, 8, 1), "Test DIVU remainder");
 
+    // J
     testId = mips_test_begin_test("J");
     mips_cpu_reset(test_cpu);
     set_instruction(test_ram, test_cpu, 0, J, 0x298c2);
@@ -274,6 +293,21 @@ int main(int argc, char** argv) {
     mips_cpu_step(test_cpu);
     mips_test_end_test(testId, check_reg(test_cpu, 10, 6), "Checking basic jump");
 
+    testId = mips_test_begin_test("J");
+    mips_cpu_reset(test_cpu);
+    set_instruction(test_ram, test_cpu, 0x10000000, J, 0x24);
+    set_instruction(test_ram, test_cpu, 0x10000004, 9, 8, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0x10000008, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0x10000090, 10, 8, 10, 0, ADDU);
+    mips_cpu_set_pc(test_cpu, 0x10000000);
+    mips_cpu_set_register(test_cpu, 8, 2);
+    mips_cpu_set_register(test_cpu, 9, 2);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 10, 6), "Test if upper 4 bits of the pc stay the same");
+
+    // JAL
     testId = mips_test_begin_test("JAL");
     mips_cpu_reset(test_cpu);
     set_instruction(test_ram, test_cpu, 4, JAL, 0x298c2);
@@ -288,6 +322,7 @@ int main(int argc, char** argv) {
     mips_cpu_step(test_cpu);
     mips_test_end_test(testId, check_reg(test_cpu, 31, 0xc), "checking if J links correctly");
 
+    // JALR
     testId = mips_test_begin_test("JALR");
     set_instruction(test_ram, test_cpu, 4, 7, 0, 31, 0, JALR);
     set_instruction(test_ram, test_cpu, 8, 9, 8, 10, 0, ADDU);
@@ -302,6 +337,7 @@ int main(int argc, char** argv) {
     mips_cpu_step(test_cpu);
     mips_test_end_test(testId, check_reg(test_cpu, 31, 0xc), "Checking if JALR links correctly");
 
+    // JR
     testId = mips_test_begin_test("JR");
     set_instruction(test_ram, test_cpu, 4, 7, 0, 0, 0, JR);
     set_instruction(test_ram, test_cpu, 8, 9, 8, 10, 0, ADDU);
@@ -316,106 +352,453 @@ int main(int argc, char** argv) {
     mips_cpu_step(test_cpu);
     mips_test_end_test(testId, check_reg(test_cpu, 10, 6), "Checking if JR jumps correctly");
 
+    // LB
     testId = mips_test_begin_test("LB");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, LB, 9, 8, 0xffff);
+    byte = 0xf9;
+    mips_mem_write(test_ram, 0x30000, 1, &byte);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x30001);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xfffffff9), "Checking basic functionality of LB");
 
+    // LBU
     testId = mips_test_begin_test("LBU");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, LBU, 9, 8, 0x1);
+    byte = 0xf9;
+    mips_mem_write(test_ram, 0x2ffff, 1, &byte);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x2fffe);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xf9), "Checking basic functionality of LBU");
 
+    // LH
     testId = mips_test_begin_test("LH");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, LH, 9, 8, 0xffff);
+    halfword = 0xf9ff;
+    mips_mem_write(test_ram, 0x30000, 2, (uint8_t*)&halfword);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x30001);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xfffffff9), "Testing basic LH");
 
+    // LHU
     testId = mips_test_begin_test("LHU");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, LHU, 9, 8, 0xffff);
+    halfword = 0xf9ff;
+    mips_mem_write(test_ram, 0x30000, 2, (uint8_t*)&halfword);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x30001);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xfff9), "Testing basic LHU");
 
+    // LUI
     testId = mips_test_begin_test("LUI");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, LUI, 0, 8, 0xf9f2);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xf9f20000), "Testing basic LUI");
 
+    // LW
     testId = mips_test_begin_test("LW");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, LW, 9, 8, 0xffff);
+    word = 0xf82e9b2f;
+    change_endianness(word);
+    mips_mem_write(test_ram, 0x30000, 4, (uint8_t*)&word);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x30001);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xf82e9b2f), "Testing basic LW");
+
+    testId = mips_test_begin_test("LW");
+    set_instruction(test_ram, test_cpu, 0, LW, 9, 8, 0xffff);
+    word = 0xf82e9b2f;
+    change_endianness(word);
+    mips_mem_write(test_ram, 0x30000, 4, (uint8_t*)&word);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x30002);
+    err = mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_error(err, mips_ExceptionInvalidAlignment), "Testing basic LW");
+    
+    // LWL
+    testId = mips_test_begin_test("LWL");
+    set_instruction(test_ram, test_cpu, 0, LWL, 9, 8, 0xffff);
+    word = 0xf82e9b2f;
+    change_endianness(word);
+    mips_mem_write(test_ram, 0x30000, 4, (uint8_t*)&word);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 8, 0xa8b234e2);
+    mips_cpu_set_register(test_cpu, 9, 0x30002);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0x2e9b2fe2), "Checking basic LWL");
 
     testId = mips_test_begin_test("LWL");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, LWL, 9, 8, 0xffff);
+    word = 0xf82e9b2f;
+    change_endianness(word);
+    mips_mem_write(test_ram, 0x30000, 4, (uint8_t*)&word);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 8, 0xa8b234e2);
+    mips_cpu_set_register(test_cpu, 9, 0x30003);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0x9b2f34e2), "Checking other LWL");
 
+    // LWR
     testId = mips_test_begin_test("LWR");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, LWR, 9, 8, 0x1);
+    word = 0xf82e9b2f;
+    change_endianness(word);
+    mips_mem_write(test_ram, 0x30000, 4, (uint8_t*)&word);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 8, 0xa8b234e2);
+    mips_cpu_set_register(test_cpu, 9, 0x30000);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xa8b2f82e), "Testing basic LWR");
+
+    testId = mips_test_begin_test("LWR");
+    set_instruction(test_ram, test_cpu, 0, LWR, 9, 8, 2);
+    word = 0xf82e9b2f;
+    change_endianness(word);
+    mips_mem_write(test_ram, 0x30000, 4, (uint8_t*)&word);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 8, 0xa8b234e2);
+    mips_cpu_set_register(test_cpu, 9, 0x30000);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xa8f82e9b), "Testing LWR with different offset");
 
+    // MFHI
     testId = mips_test_begin_test("MFHI");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, 9, 0, 0, 0, MTHI);
+    set_instruction(test_ram, test_cpu, 4, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 8, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0xc, 0, 0, 8, 0, MFHI);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x20);
+    mips_cpu_set_register(test_cpu, 10, 2);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0x20), "Checking basics of MTHI and MFHI");
 
+    // MFLO
     testId = mips_test_begin_test("MFLO");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, 9, 0, 0, 0, MTLO);
+    set_instruction(test_ram, test_cpu, 4, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 8, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0xc, 0, 0, 8, 0, MFLO);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x20);
+    mips_cpu_set_register(test_cpu, 10, 2);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0x20), "Checking basics of MTLO and MFLO");
 
+    // MTHI
     testId = mips_test_begin_test("MTHI");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, 9, 0, 0, 0, MTHI);
+    set_instruction(test_ram, test_cpu, 4, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 8, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0xc, 0, 0, 8, 0, MFHI);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x20);
+    mips_cpu_set_register(test_cpu, 10, 2);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0x20), "Checking basics of MTHI and MFHI");
 
+    // MTLO
     testId = mips_test_begin_test("MTLO");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, 9, 0, 0, 0, MTLO);
+    set_instruction(test_ram, test_cpu, 4, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 8, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0xc, 0, 0, 8, 0, MFLO);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x20);
+    mips_cpu_set_register(test_cpu, 10, 2);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0x20), "Checking basics of MTLO AND MFLO");
 
+    // MULT
     testId = mips_test_begin_test("MULT");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 0, 0, MULT);
+    set_instruction(test_ram, test_cpu, 4, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 8, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0xc, 0, 0, 8, 0, MFLO);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, -139);
+    mips_cpu_set_register(test_cpu, 10, 4);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, -556), "Checking basics of MULT, LO");
+    
+    testId = mips_test_begin_test("MULT");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 0, 0, MULT);
+    set_instruction(test_ram, test_cpu, 4, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 8, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0xc, 0, 0, 8, 0, MFHI);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, -139);
+    mips_cpu_set_register(test_cpu, 10, 4);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, -1), "Checking basics of MULT, HI");
+
+    // MULTU
+    testId = mips_test_begin_test("MULTU");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 0, 0, MULTU);
+    set_instruction(test_ram, test_cpu, 4, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 8, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0xc, 0, 0, 8, 0, MFLO);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, -139);
+    mips_cpu_set_register(test_cpu, 10, 4);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xFFFFFDD4), "Checking basics of MULTU, LO");
 
     testId = mips_test_begin_test("MULTU");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 0, 0, MULTU);
+    set_instruction(test_ram, test_cpu, 4, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 8, 10, 10, 10, 0, ADDU);
+    set_instruction(test_ram, test_cpu, 0xc, 0, 0, 8, 0, MFHI);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, -139);
+    mips_cpu_set_register(test_cpu, 10, 4);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0x3), "Checking basics of MULTU, HI");
 
+    // OR
     testId = mips_test_begin_test("OR");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, OR);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0xf1e8ba2c);
+    mips_cpu_set_register(test_cpu, 10, 0xff8cf2e9);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xFFECFAED), "Testing basic OR");
 
+    // ORI
     testId = mips_test_begin_test("ORI");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, ORI, 9, 8, 0x2293);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0xff928228);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xff92a2bb), "Testing basic ORI");
 
+    // SB
     testId = mips_test_begin_test("SB");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, SB, 9, 8, 0xffff);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 8, 0xff92822f);
+    mips_cpu_set_register(test_cpu, 9, 0x30001);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_mem(test_ram, 0x30000, 1, 0x2f), "Testing basic SB");
 
+    // SH
     testId = mips_test_begin_test("SH");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, SH, 9, 8, 1);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 8, 0xff92822f);
+    mips_cpu_set_register(test_cpu, 9, 0x30001);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_mem(test_ram, 0x30002, 2, 0x822f), "Test basic SH");
 
+    testId = mips_test_begin_test("SH");
+    set_instruction(test_ram, test_cpu, 0, SH, 9, 8, 1);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 8, 0xff92822f);
+    mips_cpu_set_register(test_cpu, 9, 0x30000);
+    err = mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_error(err, mips_ExceptionInvalidAlignment), "Test alignment of SH");
+
+    // SLL
     testId = mips_test_begin_test("SLL");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, 0, 9, 8, 4, SLL);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0xf293feb1);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0x293FEB10), "Testing basic SLL");
 
+    // SLLV
     testId = mips_test_begin_test("SLLV");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, SLLV);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 4);
+    mips_cpu_set_register(test_cpu, 10, 0xf293feb1);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0x293FEB10), "Testing basic SLL");
 
+    // SLT
     testId = mips_test_begin_test("SLT");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, SLT);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, -3);
+    mips_cpu_set_register(test_cpu, 10, 4);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 1), "Testing SLT with signed");
 
+    // SLTI
     testId = mips_test_begin_test("SLTI");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, SLTI, 9, 8, 0xf953);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0xfffff800);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 1), "Testing SLTI with negatives");
 
+    // SLTUI
     testId = mips_test_begin_test("SLTIU");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, SLTIU, 9, 8, 0x11);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0xffffffff);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0), "Testing SLTIU with a negative and positive which should give 0 in reg8");
 
+    // SLTU
     testId = mips_test_begin_test("SLTU");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, SLTU);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 3);
+    mips_cpu_set_register(test_cpu, 10, 4);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 1), "Testing basic SLTU");
 
+    // SRA
     testId = mips_test_begin_test("SRA");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, 0, 9, 8, 4, SRA);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0xf293feb1);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xff293feb), "Testing basic SRA");
 
+    // SRAV
     testId = mips_test_begin_test("SRAV");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, SRAV);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 4);
+    mips_cpu_set_register(test_cpu, 10, 0xf293feb1);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xff293feb), "Testing basic SRAV");
 
+    // SRL
     testId = mips_test_begin_test("SRL");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, 0, 9, 8, 4, SRL);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0xf293feb1);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xf293feb), "Testing basic SRL");
 
+    // SRLV
     testId = mips_test_begin_test("SRLV");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, SRLV);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 4);
+    mips_cpu_set_register(test_cpu, 10, 0xf293feb1);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xf293feb), "Testing basic SRLV");
+
+    // SUB
+    testId = mips_test_begin_test("SUB");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, SUB);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0xfb29ce8);
+    mips_cpu_set_register(test_cpu, 10, 0x873bef);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xF2B60F9), "Testing basic SUB");
 
     testId = mips_test_begin_test("SUB");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, SUB);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x7fffffff);
+    mips_cpu_set_register(test_cpu, 10, 0xa0000000);
+    err = mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_error(err, mips_ExceptionArithmeticOverflow), "Testing basic SUB");
 
+    testId = mips_test_begin_test("SUB");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, SUB);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x7fffffff);
+    mips_cpu_set_register(test_cpu, 10, 0xa0000000);
+    mips_cpu_get_register(test_cpu, 8, &word);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, word), "Testing if reg doesnt change when overflow happens");
+    
+    // SUBU
     testId = mips_test_begin_test("SUBU");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, SUBU);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x7fffffff);
+    mips_cpu_set_register(test_cpu, 10, 0xa0000000);
+    err = mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_error(err, mips_Success), "Testing if SUBU gives overflow");
+
+    testId = mips_test_begin_test("SUBU");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, SUBU);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0x7fffffff);
+    mips_cpu_set_register(test_cpu, 10, 0xa0000000);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xdfffffff), "Testing if SUBU gives overflow");
+
+    testId = mips_test_begin_test("SUBU");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, SUBU);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0xfb29ce8);
+    mips_cpu_set_register(test_cpu, 10, 0x873bef);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xF2B60F9), "Testing if SUBU gives overflow");
+
+    // SW
+    testId = mips_test_begin_test("SW");
+    set_instruction(test_ram, test_cpu, 0, SW, 9, 8, 0xffff);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 8, 0xff92822f);
+    mips_cpu_set_register(test_cpu, 9, 0x30001);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_mem(test_ram, 0x30000, 4, 0xff92822f), "Testing basic SW");
 
     testId = mips_test_begin_test("SW");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, SW, 9, 8, 0xffff);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 8, 0xff92822f);
+    mips_cpu_set_register(test_cpu, 9, 0x30002);
+    err = mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_error(err, mips_ExceptionInvalidAlignment), "Check alignment exception on SW");
 
+    // XOR
     testId = mips_test_begin_test("XOR");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, 9, 10, 8, 0, XOR);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0xf1e8ba2c);
+    mips_cpu_set_register(test_cpu, 10, 0xff8cf2e9);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xE6448C5), "Testing basic XOR");
 
+    // XORI
     testId = mips_test_begin_test("XORI");
-    mips_test_end_test(testId, 0, "");
+    set_instruction(test_ram, test_cpu, 0, XORI, 9, 8, 0x2293);
+    mips_cpu_set_pc(test_cpu, 0);
+    mips_cpu_set_register(test_cpu, 9, 0xff928228);
+    mips_cpu_step(test_cpu);
+    mips_test_end_test(testId, check_reg(test_cpu, 8, 0xff92a0bb), "Testing basic XORI");
 
     mips_test_end_suite();
     
     return 0;
 }
+
diff --git a/src/ymh15/b_test_mips.cpp b/src/ymh15/test_mips.cpp.v1
index 75afaa8..75afaa8 100644
--- a/src/ymh15/b_test_mips.cpp
+++ b/src/ymh15/test_mips.cpp.v1
diff --git a/src/ymh15/test_mips.o b/src/ymh15/test_mips.o
index df436de..16392a8 100644
--- a/src/ymh15/test_mips.o
+++ b/src/ymh15/test_mips.o
diff --git a/src/ymh15/test_mips_ymh15.cpp b/src/ymh15/test_mips_ymh15.cpp
index c2fb588..99be82d 100644
--- a/src/ymh15/test_mips_ymh15.cpp
+++ b/src/ymh15/test_mips_ymh15.cpp
@@ -53,6 +53,19 @@ int check_error(mips_error err, mips_error expected_err) {
     return 0;
 }
 
+int check_mem(mips_mem_h mem, uint32_t addr, uint32_t length,  uint32_t check_value) {
+    uint32_t mem_value = 0;
+    mips_mem_read(mem, addr, length, (uint8_t*)&mem_value);
+    if(length == 2)
+        mem_value = ((mem_value<<8)&0xff00) | mem_value>>8;
+    else if(length == 4)
+        change_endianness(mem_value);
+    if(mem_value == check_value)
+        return 1;
+    printf("At mem[%#10x]: %#10x\tExpected value: %#10x\n", addr, mem_value, check_value);
+    return 0;
+}
+
 mips_error set_instruction(mips_mem_h mem, mips_cpu_h state, uint32_t mem_location, uint32_t src1, uint32_t src2, uint32_t dest, uint32_t shift, uint32_t function) {
     uint32_t inst;
     mips_error err;
diff --git a/src/ymh15/test_mips_ymh15.hpp b/src/ymh15/test_mips_ymh15.hpp
index bd360f1..86eaacf 100644
--- a/src/ymh15/test_mips_ymh15.hpp
+++ b/src/ymh15/test_mips_ymh15.hpp
@@ -71,6 +71,7 @@ void change_endianness(uint32_t &inst);
 
 int check_reg(mips_cpu_h state, uint8_t reg_addr, uint32_t check_value);
 int check_error(mips_error err, mips_error expected_err);
+int check_mem(mips_mem_h mem, uint32_t addr, uint32_t length, uint32_t check_value);
 
 mips_error set_instruction(mips_mem_h mem, mips_cpu_h state, uint32_t mem_location, uint32_t src1, uint32_t src2, uint32_t dest, uint32_t shift, uint32_t function);
 mips_error set_instruction(mips_mem_h mem, mips_cpu_h state, uint32_t mem_location, uint32_t opcode, uint32_t src, uint32_t dest, uint32_t Astart);
diff --git a/src/ymh15/b_test_mips_ymh15.hpp b/src/ymh15/test_mips_ymh15.hpp.v1
index ca9f9fe..ca9f9fe 100644
--- a/src/ymh15/b_test_mips_ymh15.hpp
+++ b/src/ymh15/test_mips_ymh15.hpp.v1
diff --git a/src/ymh15/test_mips_ymh15.o b/src/ymh15/test_mips_ymh15.o
index c10aac7..284904a 100644
--- a/src/ymh15/test_mips_ymh15.o
+++ b/src/ymh15/test_mips_ymh15.o