improvement in html doc (not finished yet)

1 files changed, 145 insertions, 22 deletions

diff --git a/doc/index-verimag.html b/doc/index-verimag.html
index 242fa1cd..1eb857d9 100644
--- a/doc/index-verimag.html
+++ b/doc/index-verimag.html
@@ -26,7 +26,7 @@ a:active {color : Red; text-decoration : underline; }
 <H2 align="center">Commented Coq development</H2>
 <H3 align="center">Version 3.9, 2021-05-10</H3>
 </font>
-<H3 align="center">VERIMAG fork version 2021-29-10</H3>
+<H3 align="center"><a href="https://www-verimag.imag.fr">VERIMAG</a> fork version 2021-29-10</H3>
 
 <H2>The CompCert Verimag's fork</H2>
 <p>This web page is a patched version of the table of contents of the official CompCert sources documentation, as given on <A HREF="http://compcert.org/doc/index.html">the CompCert Web site</A>.
@@ -34,18 +34,37 @@ a:active {color : Red; text-decoration : underline; }
   <br>
   <br>
   A high-level view of this CompCert backend is provided by the following documents:
+
+  <ul>
+    <li><a href="https://gricad-gitlab.univ-grenoble-alpes.fr/certicompil/compcert-kvx">The Git repo README.md</a>.</li>
+    <li><a href="http://www-verimag.imag.fr/~boulme/videos/poster-oopsla20.mp4">A 5-minutes video</a> by C. Six, presenting the postpass scheduling and the KVX backend
+    (also on <a href="https://www.youtube.com/watch?v=RAzMDS9OVSw">YouTube if you need subtitles</a>).</li>
+    <li><a href="https://hal.archives-ouvertes.fr/hal-02185883">Certified and Efficient Instruction Scheduling</a>, an OOPSLA'20 paper, by Six, Boulm&eacute; and Monniaux.</li>
+    <li><a href="https://hal.archives-ouvertes.fr/hal-03200774">Formally Verified Superblock Scheduling</a>, a CPP'22 paper, by Six, Gourdin, Boulm&eacute;, Monniaux, Fasse and Nardino.</li>
+    <li><a href="https://hal.archives-ouvertes.fr/tel-03326923">Optimized and formally-verified compilation for a VLIW processor</a>, Phd Thesis of Cyril Six in 2021.</li>
+    <li><a href="https://hal.archives-ouvertes.fr/tel-03356701">Formally Verified Defensive Programming (efficient Coq-verified computations from untrusted ML oracles) &ndash; Chapters 1 to 3</a>, Habilitation Thesis of Sylvain Boulm&eacute; in 2021.</li>
+    <li><a href="https://www-verimag.imag.fr/~boulme/CPP_2022/FASSE-Justus-MSc-Thesis_2021.pdf">Code Transformations to Increase Prepass Scheduling Opportunities in CompCert</a>, MSc Thesis of Justus Fasse in 2021.</li>
+    <li><a href="https://www-verimag.imag.fr/~boulme/CPP_2022/NARDINO-Nicolas-BSc-Thesis_2021.pdf">Register-Pressure-Aware Prepass-Scheduling for CompCert</a>, BSc Thesis of Nicolas Nardino in 2021.</li>
+    <li><a href="https://www.lirmm.fr/afadl2021/papers/afadl2021_paper_9.pdf">Formally verified postpass scheduling with peephole optimization for AArch64</a>, a short AFADL'21 paper, by Gourdin.</li>
+  </ul>
+
+  <p>The people responsible for this version are</p>
+
+  <ul>
+    <li>Sylvain Boulm&eacute; (Grenoble-INP, Verimag)</li>
+    <li>David Monniaux (CNRS, Verimag)</li>
+    <li>Cyril Six (Kalray)</li>
+    <li>L&eacute;o Gourdin (UGA, Verimag)</li>
+  </ul>
+
+
+  <p>with contributions of:</p>
+
   <ul>
-    <li>The Six's thesis:
-      <div><a href=https://hal.archives-ouvertes.fr/tel-03326923>Optimized and formally-verified compilation for a VLIW processor.</a></div></li>
-    <li>Our OOPSLA'20 paper (of Six, Boulm&eacute; and Monniaux):
-      <div><a href=https://hal.archives-ouvertes.fr/hal-02185883>Certified and Efficient Instruction Scheduling. Application to Interlocked VLIW Processors.</a></div></li>
-    <li>A preprint (of Six, Gourdin, Boulm&eacute; and Monniaux):
-        <div><a href=https://hal.archives-ouvertes.fr/hal-03200774>Verified Superblock Scheduling with Related Optimizations.</a></div></li>
-    <li>A short paper published at AFADL'21 (of Gourdin):
-          <div><a href=https://www.lirmm.fr/afadl2021/papers/afadl2021_paper_9.pdf>Formally verified postpass scheduling with peephole optimization for AArch64.</a></div></li>
-    <!--TODO add the CPP'22 publication-->
-    <li>The <tt>README.md</tt> of our <a href=https://gricad-gitlab.univ-grenoble-alpes.fr/certicompil/compcert-kvx>GitLab public repository</a>.</li>
+    <li>Justus Fasse (M2R UGA, now at KU Leuven).</li>
+    <li>Pierre Goutagny and Nicolas Nardino (L3 ENS-Lyon).</li>
   </ul>
+
 </p>
 
 <H2>Introduction</H2>
@@ -120,13 +139,15 @@ inequations by fixpoint iteration.
 <LI><A HREF="html/compcert.lib.Impure.ImpPrelude.html">ImpPrelude</A>: declares the data types exchanged with <tt>Impure</tt> oracles.</LI>
 </UL>
 
-<H4>The <tt>abstractbb</tt> library, introduced for Aarch64 and KVX cores</H4>
+<H4 id="abstractbb">The <tt>abstractbb</tt> library, introduced for Aarch64 and KVX cores</H4>
 This library introduces a block intermediate representation used for postpass scheduling verification. It might be extended to others backends.
 <UL>
 <LI> <A HREF="html/compcert.scheduling.abstractbb.AbstractBasicBlocksDef.html">AbstractBasicBlocksDef</A>: an IR for verifying some semantic properties on basic-blocks.
 <LI> <A HREF="html/compcert.scheduling.abstractbb.Parallelizability.html">Parallelizability</A>: verifying that sequential and parallel semantics are equivalent for a given abstract basic-block.
 <LI> <A HREF="html/compcert.scheduling.abstractbb.ImpSimuTest.html">ImpSimuTest</A>: verifying that a given abstract basic-block is simulated by another one for sequential semantics. This module refines <A HREF="html/compcert.scheduling.abstractbb.SeqSimuTheory.html">SeqSimuTheory</A> with hash-consing and uses <A HREF=https://github.com/boulme/ImpureDemo>the Impure library</A> to reason on physical equality and handling of imperative code in Coq.
 </UL>
+
+<font color=gray>
 <H3>Definitions and theorems used in many parts of the development</H3>
 
 <UL>
@@ -182,11 +203,31 @@ replaced by a linear list of instructions with explicit branches and labels.
 view of the activation record.  
 <LI> <A HREF="html/compcert.kvx.Asm.html"><I>Asm</I></A>: abstract syntax for PowerPC assembly
 code.
+</font>
+
+<H4>Languages introduced in the VERIMAG version</H4>
+
+Generic (or possibly adaptable) Intermediate Representations (IR):
+<UL>
+  <LI> <A HREF="html/compcert.scheduling.BTL.html">BTL</A>: an IR dedicated to defensive certification of middle-end optimizations (before register allocation).
+  BTL stands for "Block Transfer Language". <!-- TODO add a link to some markdown draft here -->
+  <LI> <A HREF="html/compcert.scheduling.postpass_lib.Machblock.html">Machblock</A>: a variant of Mach, with a syntax for basic-blocks, and a block-step semantics (execute one basic-block in one step).
+  This IR is generic over the processor and used for KVX and Aarch64.
+  <LI> <A HREF="html/compcert.kvx.Asmblock.html"><I>Asmblock</I></A>: a variant of Asm, with a big-step semantics of basic-blocks.
+  This IR is an intermediate step between Machblock and Asm on backends featuring postpass scheduling (KVX and Aarch64).
+  <LI> <A HREF="#abstractbb"><I>AbstractBasicBlocks</I></A>: the AbstractBasicBlocks Domain Specific Language (DSL) used in the postpass scheduling verification.
+  This DSL is only used as a library on KVX and Aarch64.
+</UL>
+
+Specific to KVX:
+<UL>
+  <LI> <A HREF="html/compcert.kvx.Asmvliw.html"><I>Asmvliw</I></A>: abstract syntax and semantics for KVX VLIW assembly: atomic instructions are grouped by "bundles". These bundles are executed sequentially, but execution is parallel within bundles.
+  <LI> <A HREF="html/compcert.kvx.Asm.html"><I>kvx/Asm</I></A>: a variant of Asmvliw with a flat syntax for bundles, instead of a structured one (bundle termination is encoded as a pseudo-instruction). This IR is mainly a wrapper of <I>Asmvliw</I> for a smooth integration in CompCert (and an easier pretty-printing of the abstract syntax).
 </UL>
 
 <H3>Compiler passes</H3>
 
-<TABLE cellpadding="5%">
+<TABLE cellpadding="5%" style="color:#808080">
 <TR valign="top">
   <TH align=left>Pass</TH>
   <TH align=left>Source &amp; target</TH>
@@ -301,6 +342,60 @@ code.
   <TD><A HREF="html/compcert.backend.Unusedglobproof.html">Unusedglobproof</A></TD>
 </TR>
 
+<TR valign="top" style="color:#000000">
+  <TD colspan="4"><b>Passes introduced for profiling (for later use in trace selection)</b></TD>
+</TR>
+<TR valign="top" style="color:#000000">
+  <TD>Insert profiling annotations (for recording experiments -- see PROFILE.md).
+  </TD>
+  <TD>RTL to RTL</TD>
+  <TD><A HREF="html/compcert.backend.Profiling.html">Profiling</A></TD>
+  <TD><A HREF="html/compcert.backend.Profilingproof.html">Profilingproof</A></TD>
+</TR>
+<TR valign="top" style="color:#000000">
+  <TD>Update ICond nodes (from recorded experiments -- see PROFILE.md).
+  </TD>
+  <TD>RTL to RTL</TD>
+  <TD><A HREF="html/compcert.backend.ProfilingExploit.html">ProfilingExploit</A></TD>
+  <TD><A HREF="html/compcert.backend.ProfilingExploitproof.html">ProfilingExploitproof</A></TD>
+</TR>
+<TR valign="top" style="color:#000000">
+  <TD colspan="4"><b>Passes introduced for superblock prepass scheduling</b></TD>
+</TR>
+<TR valign="top" style="color:#000000">
+  <TD>Code duplications (trace selection, loop unrollings, etc)
+  </TD>
+  <TD>RTL to RTL</TD>
+  <TD><A HREF="html/compcert.backend.Duplicate.html">Duplicate</A> (generic checker)</TD>
+  <TD><A HREF="html/compcert.backend.Duplicateproof.html">Duplicateproof</A> (generic proof)<BR>
+    <a href="html/compcert.backend.Duplicatepasses.html">Duplicatepasses</a> (several passes from several oracles)</TD>
+</TR>
+<TR valign="top" style="color:#000000">
+  <TD>Superblock selection (with Liveness information)</TD>
+  <TD>RTL to RTLPath</TD>
+  <TD><A HREF="html/compcert.scheduling.RTLpathLivegen.html">RTLpathLivegen</A></TD>
+  <TD><A HREF="html/compcert.scheduling.RTLpathLivegenproof.html">RTLpathLivegenproof</A></TD>
+</TR>
+<TR valign="top" style="color:#000000">
+  <TD>Superblock prepass scheduling</TD>
+  <TD>RTLPath to RTLPath</TD>
+  <TD><A HREF="html/compcert.scheduling.RTLpathScheduler.html">RTLpathScheduler</A></TD>
+  <TD><A HREF="html/compcert.scheduling.RTLpathSchedulerproof.html">RTLpathSchedulerproof</A><BR>
+    with <A HREF="html/compcert.scheduling.RTLpathSE_theory.html">RTLpathSE_theory</A> (the theory of symbolic execution on RTLpath)<BR>
+    and <A HREF="html/compcert.scheduling.RTLpathSE_simu_specs.html">RTLpathSE_simu_specs</A> (the low-level specifications of the simulation checker)<BR>
+    and <A HREF="html/compcert.scheduling.RTLpathSE_impl.html">RTLpathSE_impl</A> (the simulation checker with hash-consing)</TD>
+</TR>
+<TR valign="top" style="color:#000000">
+  <TD>Forgeting superblocks</TD>
+  <TD>RTLPath to RTL</TD>
+  <TD><A HREF="html/compcert.scheduling.RTLpath.html#transf_program">RTLpath.transf_program</A></TD>
+  <TD><A HREF="html/compcert.scheduling.RTLpathproof.html">RTLpathproof</A></TD>
+</TR>
+
+<TR valign="top">
+  <TD colspan="4"><b>Passes from register allocation</b></TD>
+</TR>
+
 <TR valign="top">
   <TD>Register allocation (validation a posteriori)</TD>
   <TD>RTL to LTL</TD>
@@ -311,8 +406,8 @@ code.
 <TR valign="top">
   <TD>Branch tunneling</TD>
   <TD>LTL to LTL</TD>
-  <TD><A HREF="html/compcert.backend.Tunneling.html">Tunneling</A></TD>
-  <TD><A HREF="html/compcert.backend.Tunnelingproof.html">Tunnelingproof</A></TD>
+  <TD><A HREF="html/compcert.backend.LTLTunneling.html">LTLTunneling</A></TD>
+  <TD><A HREF="html/compcert.backend.LTLTunnelingproof.html">LTLTunnelingproof</A></TD>
 </TR>
 
 <TR valign="top">
@@ -346,22 +441,50 @@ code.
       <A HREF="html/compcert.common.Separation.html">Separation</A></TD>
 </TR>
 
-<TR valign="top">
-  <TD>Emission of assembly code</TD>
-  <TD>Mach to Asm</TD>
+<TR valign="top" style="color:#000000">
+  <TD colspan="4"><b>Passes introduced for KVX VLIW</b></TD>
+</TR>
+<TR valign="top" style="color:#000000">
+  <TD>Reconstruction of basic-blocks at Mach level</TD>
+  <TD>Mach to Machblock</TD>
+  <TD><A HREF="html/compcert.scheduling.postpass_lib.Machblockgen.html">Machblockgen</A></TD>
+  <TD><A HREF="html/compcert.scheduling.postpass_lib.ForwardSimulationBlock.html">ForwardSimulationBlock</A><BR>
+      <A HREF="html/compcert.scheduling.postpass_lib.Machblockgenproof.html">Machblockgenproof</A></TD>
+</TR>
+
+<TR valign="top" style="color:#000000">
+  <TD>Emission of purely sequential assembly code</TD>
+  <TD>Machblock to Asmblock</TD>
+  <TD><A HREF="html/compcert.kvx.Asmblockgen.html"><I>Asmblockgen</I></A></TD>
+  <TD><A HREF="html/compcert.kvx.Asmblockgenproof0.html"><I>Asmblockgenproof0</I></A><BR>
+      <A HREF="html/compcert.kvx.Asmblockgenproof1.html"><I>Asmblockgenproof1</I></A><BR>
+      <A HREF="html/compcert.kvx.Asmblockgenproof.html"><I>Asmblockgenproof</I></A></TD>
+</TR>
+
+<TR valign="top" style="color:#000000">
+  <TD>Bundling (and basic-block scheduling)</TD>
+  <TD>Asmblock to Asmvliw</TD>
+  <TD><A HREF="html/compcert.kvx.PostpassScheduling.html"><I>PostpassScheduling</I></A><BR>
+    using <A HREF="html/compcert.kvx.Asmblockdeps.html"><I>Asmblockdeps</I></A><BR>
+    and the <tt>abstractbb</tt> library</TD>
+  <TD><A HREF="html/compcert.kvx.PostpassSchedulingproof.html"><I>PostpassSchedulingproof</I></A></TD>
+</TR>
+
+<TR valign="top" style="color:#000000">
+  <TD>Flattening bundles (only a bureaucratic operation)</TD>
+  <TD>Asmvliw to Asm</TD>
   <TD><A HREF="html/compcert.kvx.Asmgen.html"><I>Asmgen</I></A></TD>
-  <TD><A HREF="html/compcert.backend.Asmgenproof0.html"><I>Asmgenproof0</I></A><BR>
-      <A HREF="html/compcert.kvx.Asmgenproof1.html"><I>Asmgenproof1</I></A><BR>
-      <A HREF="html/compcert.kvx.Asmgenproof.html"><I>Asmgenproof</I></A></TD>
+  <TD><A HREF="html/compcert.kvx.Asmgenproof.html"><I>Asmgenproof</I></A> (whole simulation proof from <tt>Mach</tt> to <tt>Asm</tt>)</TD>
 </TR>
 </TABLE>
 
 <H3>All together (there are many more passes than on vanilla CompCert: their order is specified in Compiler)</H3>
+</font>
+<font color=gray>
 
 <UL>
 <LI> <A HREF="html/compcert.driver.Compiler.html">Compiler</A>: composing the passes together;
 whole-compiler semantic preservation theorems.
-<font color=gray>
 <LI> <A HREF="html/compcert.driver.Complements.html">Complements</A>: interesting consequences of the semantic preservation theorems.
 </UL>