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author | Bernhard Schommer <bschommer@users.noreply.github.com> | 2019-05-28 10:33:34 +0200 |
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committer | Xavier Leroy <xavierleroy@users.noreply.github.com> | 2019-05-28 10:33:34 +0200 |
commit | e10555313645cf3c35f244f42afa5a03fba2bac1 (patch) | |
tree | 7b1e42b23ac78f5866681f12402d7c7aeceaecd3 /powerpc/Asm.v | |
parent | c36514ac4b05f78dd2e02fab3f8886cab8234925 (diff) | |
download | compcert-kvx-e10555313645cf3c35f244f42afa5a03fba2bac1.tar.gz compcert-kvx-e10555313645cf3c35f244f42afa5a03fba2bac1.zip |
Provide a float select operation for PowerPC. (#173)
The FP select for PowerPC stores both addresses in two
subsequent stack slots and loads them using an offset created
from the result of the comparison.
Diffstat (limited to 'powerpc/Asm.v')
-rw-r--r-- | powerpc/Asm.v | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/powerpc/Asm.v b/powerpc/Asm.v index e821c6c4..b9300fd7 100644 --- a/powerpc/Asm.v +++ b/powerpc/Asm.v @@ -231,6 +231,7 @@ Inductive instruction : Type := | Pfres: freg -> freg -> instruction (**r approximate inverse *) | Pfsel: freg -> freg -> freg -> freg -> instruction (**r FP conditional move *) | Pisel: ireg -> ireg -> ireg -> crbit -> instruction (**r integer select *) + | Pfsel_gen: freg -> freg -> freg -> crbit -> instruction (**r floating point select *) | Pisync: instruction (**r ISYNC barrier *) | Picbi: ireg -> ireg -> instruction (**r instruction cache invalidate *) | Picbtls: int -> ireg -> ireg -> instruction (**r instruction cache block touch and lock set *) @@ -867,6 +868,13 @@ Definition exec_instr (f: function) (i: instruction) (rs: regset) (m: mem) : out | _ => Vundef end in Next (nextinstr (rs #rd <- v #GPR0 <- Vundef)) m + | Pfsel_gen rd r1 r2 bit => + let v := + match rs#(reg_of_crbit bit) with + | Vint n => if Int.eq n Int.zero then rs#r2 else rs#r1 + | _ => Vundef + end in + Next (nextinstr (rs #rd <- v #GPR0 <- Vundef)) m | Plbz rd cst r1 => load1 Mint8unsigned rd cst r1 rs m | Plbzx rd r1 r2 => |