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| author | Xavier Leroy <xavier.leroy@college-de-france.fr> | 2020-12-06 10:30:51 +0100 |
|---|---|---|
| committer | Xavier Leroy <xavier.leroy@college-de-france.fr> | 2020-12-06 12:18:57 +0100 |
| commit | ef5477a47b49c405744319fbdef0a689b1bf03d4 (patch) | |
| tree | 47de3060e1e67749e67ec4d7b16046cb5227b1fc /powerpc/Asm.v | |
| parent | e6e036b3f285d2f3ba2a5036a413eb9c7d7534cd (diff) | |
| download | compcert-kvx-ef5477a47b49c405744319fbdef0a689b1bf03d4.tar.gz compcert-kvx-ef5477a47b49c405744319fbdef0a689b1bf03d4.zip | |
Remove Pfcfi, Pfcfiu, Pfctiu pseudoinstructions
Also remove the Ofloatofint, Ofloatofintu, and Ointuoffloat
PowerPC operations.
The pseudoinstructions were used to implement these operations,
as follows:
Pfcfi : Ofloatofint i.e. the conversion signed int32 -> float64
Pfcfiu : Ofloatofintu i.e. the conversion unsigned int32 -> float64
Pfctiu : Ointuoffloat i.e. the conversion float64 -> unsigned int32
These pseudoinstructions were expanded (in Asmexpand.ml) in terms of
Pfcfid : signed int64 -> float64
Pfctidz : float64 -> signed int64
and int32/int64 conversions.
This commit performs this expansion during instruction selection
(SelectOp.vp):
floatofint(n) becomes floatoflong(longofint(n))
floatofintu(n) becomes floatoflong(longuofint(n))
intuoffloat(n) becomes cast32unsigned(longoffloat(n))
Then there is no need for the 3 removed operations and the 3 removed
pseudoinstructions.
More importantly, the correctness of these expansions is now proved as
part of instruction selection, using the corresponding results from
Floats.v.
Diffstat (limited to 'powerpc/Asm.v')
| -rw-r--r-- | powerpc/Asm.v | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/powerpc/Asm.v b/powerpc/Asm.v index 4fb38ff8..6ec20d62 100644 --- a/powerpc/Asm.v +++ b/powerpc/Asm.v @@ -200,12 +200,9 @@ Inductive instruction : Type := | Pfadd: freg -> freg -> freg -> instruction (**r float addition *) | Pfadds: freg -> freg -> freg -> instruction (**r float addition *) | Pfcmpu: freg -> freg -> instruction (**r float comparison *) - | Pfcfi: freg -> ireg -> instruction (**r signed-int-to-float conversion (pseudo, PPC64) *) | Pfcfl: freg -> ireg -> instruction (**r signed-long-to-float conversion (pseudo, PPC64) *) - | Pfcfiu: freg -> ireg -> instruction (**r unsigned-int-to-float conversion (pseudo, PPC64) *) | Pfcfid: freg -> freg -> instruction (**r signed-long-to-float conversion (PPC64) *) | Pfcti: ireg -> freg -> instruction (**r float-to-signed-int conversion, round towards 0 (pseudo) *) - | Pfctiu: ireg -> freg -> instruction (**r float-to-unsigned-int conversion, round towards 0 (pseudo, PPC64) *) | Pfctid: ireg -> freg -> instruction (**r float-to-signed-int conversion, round towards 0 (pseudo, PPC64) *) | Pfctidz: freg -> freg -> instruction (**r float-to-signed-long conversion, round towards 0 (PPC64) *) | Pfctiw: freg -> freg -> instruction (**r float-to-signed-int conversion, round by default *) @@ -825,16 +822,10 @@ Definition exec_instr (f: function) (i: instruction) (rs: regset) (m: mem) : out Next (nextinstr (rs#rd <- (Val.addfs rs#r1 rs#r2))) m | Pfcmpu r1 r2 => Next (nextinstr (compare_float rs rs#r1 rs#r2)) m - | Pfcfi rd r1 => - Next (nextinstr (rs#rd <- (Val.maketotal (Val.floatofint rs#r1)))) m | Pfcfl rd r1 => Next (nextinstr (rs#rd <- (Val.maketotal (Val.floatoflong rs#r1)))) m - | Pfcfiu rd r1 => - Next (nextinstr (rs#rd <- (Val.maketotal (Val.floatofintu rs#r1)))) m | Pfcti rd r1 => Next (nextinstr (rs#FPR13 <- Vundef #rd <- (Val.maketotal (Val.intoffloat rs#r1)))) m - | Pfctiu rd r1 => - Next (nextinstr (rs#FPR13 <- Vundef #rd <- (Val.maketotal (Val.intuoffloat rs#r1)))) m | Pfctid rd r1 => Next (nextinstr (rs#FPR13 <- Vundef #rd <- (Val.maketotal (Val.longoffloat rs#r1)))) m | Pfdiv rd r1 r2 => |