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* Adding both RV expansion methods in kvx-workLéo Gourdin2021-05-191-0/+344
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* Removing expansions from AsmgenLéo Gourdin2021-04-091-344/+0
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* Removing addptrofs draft, next will be mergingLéo Gourdin2021-04-091-14/+0
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* Important commit on expansions' mini CSE, and a draft for addptrofsLéo Gourdin2021-04-061-13/+45
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* a more general way to manage special registers before introducing SPLéo Gourdin2021-03-301-68/+89
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* Now a more general way to perform imm operationsLéo Gourdin2021-03-301-6/+9
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* Adding more expansions, improving miniCSE, and tuning prepassLéo Gourdin2021-03-261-0/+24
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* Merge remote-tracking branch 'origin/riscv-work' into riscv-work-fpinit-stillexpLéo Gourdin2021-03-061-4/+4
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| * Adding a mini CSE pass in the expansion oracleLéo Gourdin2021-03-061-4/+4
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* | Asmcondexp branche useful to benchmark expansionsLéo Gourdin2021-03-021-0/+247
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* Merge conflicts solved and cleaning in Asmgenproof after expansionLéo Gourdin2021-03-021-253/+0
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* Merge remote-tracking branch 'origin/riscV-cmov' into riscv-workLéo Gourdin2021-03-021-0/+25
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| * asmgen OselectlDavid Monniaux2021-02-021-0/+7
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| * Asmgen for bits / floatDavid Monniaux2021-02-011-0/+13
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* | Proof of fsval condition cmp okLéo Gourdin2021-03-011-4/+4
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* | [Admitted checker] Duplicating Asm Ceq/Cne and draft checker proofLéo Gourdin2021-02-111-0/+32
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* | [Admitted checker] Adding cbranch expansions (without scratch) to the checkerLéo Gourdin2021-02-101-1/+1
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* | [Admitted checker] Checker expansion for reg Ocmp (without scratch)Léo Gourdin2021-02-101-14/+14
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* | cond and branches expandedLéo Gourdin2021-02-061-23/+65
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* | All Ocmp expanded in RTLLéo Gourdin2021-02-031-7/+37
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* | Ccomp for longLéo Gourdin2021-02-031-3/+44
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* | Ccompu expansionLéo Gourdin2021-02-021-0/+9
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* | Expansion of Ccompimm in RTL [Admitted checker]Léo Gourdin2021-02-021-2/+38
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* Merge branch 'dm-div2' of https://github.com/monniaux/CompCert into mppa-workDavid Monniaux2020-01-151-10/+20
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| * 64-bit signed division by two codeDavid Monniaux2020-01-141-5/+10
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| * rv32: 3-instruction signed divide-by-two sequence (as opposed to 4)David Monniaux2020-01-141-5/+10
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* | Merge remote-tracking branch 'origin/mppa-work' into mppa-non-trapping-loadDavid Monniaux2019-12-021-0/+2
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| * | fix compile for rv32David Monniaux2019-10-161-0/+2
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* / fix for Risc-VDavid Monniaux2019-09-071-4/+9
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* RISC-V port and assorted changesXavier Leroy2017-04-281-0/+936
This commits adds code generation for the RISC-V architecture, both in 32- and 64-bit modes. The generated code was lightly tested using the simulator and cross-binutils from https://riscv.org/software-tools/ This port required the following additional changes: - Integers: More properties about shrx - SelectOp: now provides smart constructors for mulhs and mulhu - SelectDiv, 32-bit integer division and modulus: implement constant propagation, use the new smart constructors mulhs and mulhu. - Runtime library: if no asm implementation is provided, run the reference C implementation through CompCert. Since CompCert rejects the definitions of names of special functions such as __i64_shl, the reference implementation now uses "i64_" names, e.g. "i64_shl", and a renaming "i64_ -> __i64_" is performed over the generated assembly file, before assembling and building the runtime library. - test/: add SIMU make variable to run tests through a simulator - test/regression/alignas.c: make sure _Alignas and _Alignof are not #define'd by C headers commit da14495c01cf4f66a928c2feff5c53f09bde837f Author: Xavier Leroy <xavier.leroy@inria.fr> Date: Thu Apr 13 17:36:10 2017 +0200 RISC-V port, continued Now working on Asmgen. commit 36f36eb3a5abfbb8805960443d087b6a83e86005 Author: Xavier Leroy <xavier.leroy@inria.fr> Date: Wed Apr 12 17:26:39 2017 +0200 RISC-V port, first steps This port is based on Prashanth Mundkur's experimental RV32 port and brings it up to date with CompCert, and adds 64-bit support (RV64). Work in progress.
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