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| author | Clifford Wolf <clifford@clifford.at> | 2015-07-02 12:29:06 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-02 12:29:06 +0200 |
| commit | c10125eb5cb91968f724cea3092252159af207d7 (patch) | |
| tree | d4d4973f41c1bfbf47c6e09534401767acc4cee5 | |
| parent | 853ce91300977b2afd0bc8e6b107ad1be1e25571 (diff) | |
| download | picorv32-c10125eb5cb91968f724cea3092252159af207d7.tar.gz picorv32-c10125eb5cb91968f724cea3092252159af207d7.zip | |
Added TWO_STAGE_SHIFT parameter
| -rw-r--r-- | README.md | 7 | ||||
| -rw-r--r-- | picorv32.v | 5 |
2 files changed, 11 insertions, 1 deletions
@@ -158,6 +158,13 @@ latches the value internally. This parameter is only available for the `picorv32` core. In the `picorv32_axi` core this is implicitly set to 0. +#### TWO_STAGE_SHIFT (default = 1) + +By default shift operations are performed in two stages: first shift in units +of 4 bits and then shift in units of 1 bit. This speeds up shift operations, +but adds additional hardware. Set this parameter to 0 to disable the two-stage +shift to further reduce the size of the core. + #### CATCH_MISALIGN (default = 1) Set this to 0 to disable the circuitry for catching misaligned memory @@ -36,6 +36,7 @@ module picorv32 #( parameter [ 0:0] ENABLE_REGS_16_31 = 1, parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, parameter [ 0:0] LATCHED_MEM_RDATA = 0, + parameter [ 0:0] TWO_STAGE_SHIFT = 1, parameter [ 0:0] CATCH_MISALIGN = 1, parameter [ 0:0] CATCH_ILLINSN = 1, parameter [ 0:0] ENABLE_PCPI = 0, @@ -885,7 +886,7 @@ module picorv32 #( reg_out <= reg_op1; mem_do_rinst <= mem_do_prefetch; cpu_state <= cpu_state_fetch; - end else if (reg_sh >= 4) begin + end else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin (* parallel_case, full_case *) case (1'b1) instr_slli || instr_sll: reg_op1 <= reg_op1 << 4; @@ -1136,6 +1137,7 @@ module picorv32_axi #( parameter [ 0:0] ENABLE_COUNTERS = 1, parameter [ 0:0] ENABLE_REGS_16_31 = 1, parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, + parameter [ 0:0] TWO_STAGE_SHIFT = 1, parameter [ 0:0] CATCH_MISALIGN = 1, parameter [ 0:0] CATCH_ILLINSN = 1, parameter [ 0:0] ENABLE_PCPI = 0, @@ -1230,6 +1232,7 @@ module picorv32_axi #( .ENABLE_COUNTERS (ENABLE_COUNTERS ), .ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ), .ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT), + .TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ), .CATCH_MISALIGN (CATCH_MISALIGN ), .CATCH_ILLINSN (CATCH_ILLINSN ), .ENABLE_PCPI (ENABLE_PCPI ), |