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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-09 09:23:17 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-09 09:23:17 +0200 |
| commit | d124abbacd655e449becb9a05cb70ff45c50fa9b (patch) | |
| tree | 6f4ae57e56845214418c50f7e1a00fc4c2048812 | |
| parent | e6779ba52b41c3e6551ae95a137c543abc91a4f6 (diff) | |
| download | picorv32-d124abbacd655e449becb9a05cb70ff45c50fa9b.tar.gz picorv32-d124abbacd655e449becb9a05cb70ff45c50fa9b.zip | |
Update README.md
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -92,7 +92,7 @@ This Verilog file contains the following Verilog modules: | `picorv32_axi` | The version of the CPU with AXI4-Lite interface | | `picorv32_axi_adapter` | Adapter from PicoRV32 Memory Interface to AXI4-Lite | | `picorv32_wb` | The version of the CPU with Wishbone Master interface | -| `picorv32_pcpi_mul` | A PCPI core that implements the `MUL[H[SU|U]]` instructions | +| `picorv32_pcpi_mul` | A PCPI core that implements the `MUL[H[SU\|U]]` instructions | | `picorv32_pcpi_fast_mul` | A version of `picorv32_pcpi_fast_mul` using a single cycle multiplier | | `picorv32_pcpi_div` | A PCPI core that implements the `DIV[U]/REM[U]` instructions | |