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| author | Clifford Wolf <clifford@clifford.at> | 2016-04-09 14:35:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-04-09 14:35:17 +0200 |
| commit | df7f5915d77034aa9b442100fbe0dee9b66e6d8b (patch) | |
| tree | a39d3eaad35647a189d96a64f81fdf62b29f64f5 | |
| parent | aa17d587843a78e3d49b5e24bc5e4ab76e8c6383 (diff) | |
| download | picorv32-df7f5915d77034aa9b442100fbe0dee9b66e6d8b.tar.gz picorv32-df7f5915d77034aa9b442100fbe0dee9b66e6d8b.zip | |
Added documentation for COMPRESSED_ISA parameter
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | README.md | 5 |
2 files changed, 6 insertions, 1 deletions
@@ -9,7 +9,7 @@ FIRMWARE_OBJS = firmware/start.o firmware/irq.o firmware/print.o firmware/sieve. GCC_WARNS = -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings GCC_WARNS += -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic # -Wconversion TOOLCHAIN_PREFIX = /opt/riscv32i/bin/riscv32-unknown-elf- -# COMPRESSED_ISA = C +COMPRESSED_ISA = C test: testbench.exe firmware/firmware.hex vvp -N testbench.exe @@ -185,6 +185,11 @@ the ALU. *Note: Enabling this parameter will be most effective when retiming (aka "register balancing") is enabled in the synthesis flow.* +#### COMPRESSED_ISA (default = 0) + +This enables support for the RISC-V Compressed Instruction Set. Currently +this implements the draft version 1.9 of the compressed ISA specification. + #### CATCH_MISALIGN (default = 1) Set this to 0 to disable the circuitry for catching misaligned memory |