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author | Claire Wolf <clifford@clifford.at> | 2020-04-22 17:31:29 +0200 |
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committer | GitHub <noreply@github.com> | 2020-04-22 17:31:29 +0200 |
commit | fe1ee2c739c9225eec1dfc8729d8635c253259c9 (patch) | |
tree | 9510e75332f74162cf55feeaf8cca14586506a0f | |
parent | 65e72ea49e7a15b56ad27eceef1e94f213234b4f (diff) | |
parent | fac01cee1c03f2209078b3e268987814309dc63d (diff) | |
download | picorv32-fe1ee2c739c9225eec1dfc8729d8635c253259c9.tar.gz picorv32-fe1ee2c739c9225eec1dfc8729d8635c253259c9.zip |
Merge pull request #152 from RolinBert/master
Fix #151 (missing irqs)
-rw-r--r-- | picorv32.v | 13 |
1 files changed, 7 insertions, 6 deletions
@@ -1435,15 +1435,9 @@ module picorv32 #( next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx; if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin - if (timer - 1 == 0) - next_irq_pending[irq_timer] = 1; timer <= timer - 1; end - if (ENABLE_IRQ) begin - next_irq_pending = next_irq_pending | irq; - end - decoder_trigger <= mem_do_rinst && mem_done; decoder_trigger_q <= decoder_trigger; decoder_pseudo_trigger <= 0; @@ -1913,6 +1907,13 @@ module picorv32 #( end endcase + if (ENABLE_IRQ) begin + next_irq_pending = next_irq_pending | irq; + if(ENABLE_IRQ_TIMER && timer) + if (timer - 1 == 0) + next_irq_pending[irq_timer] = 1; + end + if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin `debug($display("MISALIGNED WORD: 0x%08x", reg_op1);) |