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| author | Clifford Wolf <clifford@clifford.at> | 2016-06-01 12:39:00 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-06-01 12:39:00 +0200 |
| commit | 490a7345191f9841fa953d18b27c8485171406ce (patch) | |
| tree | ad169a8341e6cb6cdc5505b40b8c019bbe0f8618 /README.md | |
| parent | fd18475e239f396695d7aed5913d0581f6667110 (diff) | |
| download | picorv32-490a7345191f9841fa953d18b27c8485171406ce.tar.gz picorv32-490a7345191f9841fa953d18b27c8485171406ce.zip | |
Encode in q0 LSB if interrupted instruction is compressed
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -463,6 +463,10 @@ address and `q1` contains a bitmask of all IRQs to be handled. This means one call to the interrupt handler needs to service more than one IRQ when more than one bit is set in `q1`. +When support for compressed instructions is enabled, then the LSB of q0 is set +when the interrupted instruction is a compressed instruction. This can be used if +the IRQ handler wants to decode the interrupted instruction. + Registers `q2` and `q3` are uninitialized and can be used as temporary storage when saving/restoring register values in the IRQ handler. |