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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-24 15:20:23 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-24 15:20:23 +0200 |
| commit | 8043c90a04031c1619d0be7b1aba717e4f9968ac (patch) | |
| tree | 2c6f5fb2768459a6d9f32295563225157cf5d049 /README.md | |
| parent | bec8d6a6b966ce494d50a37a257af9f8cc3c8b01 (diff) | |
| download | picorv32-8043c90a04031c1619d0be7b1aba717e4f9968ac.tar.gz picorv32-8043c90a04031c1619d0be7b1aba717e4f9968ac.zip | |
Added REGS_INIT_ZERO parameter
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -256,6 +256,11 @@ Set this to 0 to disable support for the `timer` instruction. Support for the timer is always disabled when ENABLE_IRQ is set to 0. +#### REGS_INIT_ZERO (default = 0) + +Set this to 1 to initialize all registers to zero (using a Verilog `initial` block). +This can be useful for simulation or formal verification. + #### MASKED_IRQ (default = 32'h 0000_0000) A 1 bit in this bitmask corresponds to a permanently disabled IRQ. |