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| author | Clifford Wolf <clifford@clifford.at> | 2015-07-01 22:18:20 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-01 22:18:20 +0200 |
| commit | 84e2202fef487414ab650bac43d60b3d76435812 (patch) | |
| tree | 4f1d876e200dc9bad3ae4fbf9b4773973e1c7a6f /README.md | |
| parent | e72abc0284bb6a04b9a6f1ea8e5cab601181cbb4 (diff) | |
| download | picorv32-84e2202fef487414ab650bac43d60b3d76435812.tar.gz picorv32-84e2202fef487414ab650bac43d60b3d76435812.zip | |
Vivado 2015.2 area evaluation
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 12 |
1 files changed, 6 insertions, 6 deletions
@@ -533,7 +533,7 @@ place&route static timing analysis with `report_timing`. | Xilinx Virtex-7T | -3 | 2.4 ns (416 MHz) | The following table lists the resource utilization in area-optimized synthesis, -as reported by Vivado 2015.1 post optimization with `report_utilization`. +as reported by Vivado 2015.2 post optimization with `report_utilization`. PicoRV32 "small" is the core without counter instructions, with externally latched `mem_rdata`, and without catching of misaligned memory access and @@ -543,9 +543,9 @@ PicoRV32 "regular" is simply the core with its default settings. And PicoRV32 "large" is with enabled PCPI, IRQ and MUL features. -| Core Variant | Slice LUTs | LUTs as Memory | -|:------------------ | ----------:| --------------:| -| PicoRV32 "small" | 828 | 48 | -| PicoRV32 "regular" | 968 | 48 | -| PicoRV32 "large" | 1742 | 88 | +| Core Variant | Slice LUTs | LUTs as Memory | Slice Registers | +|:------------------ | ----------:| --------------:| ---------------:| +| PicoRV32 "small" | 828 | 48 | 422 | +| PicoRV32 "regular" | 968 | 48 | 564 | +| PicoRV32 "large" | 1742 | 88 | 1002 | |