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| author | Clifford Wolf <clifford@clifford.at> | 2015-06-07 08:28:10 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-06-07 11:49:47 +0200 |
| commit | e84f044bc5e740c880ae547e84c3f3a0fe424f51 (patch) | |
| tree | 1b5c3b0519d93eb23a3104e7519880dd4929bf3c /dhrystone/testbench.v | |
| parent | 491cd5e15dc3f96d177493d2e23edc356dcc648e (diff) | |
| download | picorv32-e84f044bc5e740c880ae547e84c3f3a0fe424f51.tar.gz picorv32-e84f044bc5e740c880ae547e84c3f3a0fe424f51.zip | |
Major redesign of main FSM
Diffstat (limited to 'dhrystone/testbench.v')
| -rw-r--r-- | dhrystone/testbench.v | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/dhrystone/testbench.v b/dhrystone/testbench.v index c14779e..bfa9fbc 100644 --- a/dhrystone/testbench.v +++ b/dhrystone/testbench.v @@ -43,11 +43,12 @@ module testbench; assign mem_ready = 1; always @(posedge clk) begin - mem_rdata <= mem_la_read ? memory[mem_la_addr >> 2] : 'bx; + if (mem_la_read) + mem_rdata <= memory[mem_la_addr >> 2]; if (mem_valid) begin case (mem_addr) 32'h1000_0000: begin -`ifndef INSN_TIMING +`ifndef TIMING $write("%c", mem_wdata); $fflush(); `endif @@ -75,14 +76,12 @@ module testbench; end end -`ifdef INSN_TIMING +`ifdef TIMING initial begin repeat (100000) @(posedge clk); $finish; end always @(uut.count_instr[0]) begin - // iverilog -DINSN_TIMING testbench.v ../picorv32.v && ./a.out > x - // sed 's,.*## ,,' x | gawk 'x != "" {print x,$2-y;} {x=$1;y=$2;}' | sort | uniq -c | sort -k3 -n $display("## %-s %d", uut.instruction, uut.count_cycle); end `endif |