Major redesign of main FSM

3 files changed, 23 insertions, 6 deletions

diff --git a/dhrystone/Makefile b/dhrystone/Makefile
index 412ffda..7e077b1 100644
--- a/dhrystone/Makefile
+++ b/dhrystone/Makefile
@@ -5,10 +5,18 @@ CFLAGS = -MD -O3 -m32 -march=RV32I -ffreestanding -nostdlib -DTIME -DRISCV
 test: testbench.exe dhry.hex
 	vvp -N testbench.exe
 
+timing: timing.exe dhry.hex
+	vvp -N timing.exe > timing.txt
+	sed 's,.*## ,,' timing.txt | gawk 'x != "" {print x,$$2-y;} {x=$$1;y=$$2;}' | sort | uniq -c | sort -k3 -n
+
 testbench.exe: testbench.v ../picorv32.v
 	iverilog -o testbench.exe testbench.v ../picorv32.v
 	chmod -x testbench.exe
 
+timing.exe: testbench.v ../picorv32.v
+	iverilog -o timing.exe -DTIMING testbench.v ../picorv32.v
+	chmod -x timing.exe
+
 dhry.hex: dhry.bin ../firmware/makehex.py
 	python3 ../firmware/makehex.py $< > $@
 
@@ -27,7 +35,7 @@ dhry.elf: $(OBJS) ../firmware/sections.lds
 	riscv64-unknown-elf-gcc -c $(CFLAGS) $<
 
 clean:
-	rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.exe testbench.vcd
+	rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.exe testbench.vcd timing.exe timing.txt
 
 .PHONY: test clean
 
diff --git a/dhrystone/start.S b/dhrystone/start.S
index 202727c..092ba96 100644
--- a/dhrystone/start.S
+++ b/dhrystone/start.S
@@ -17,6 +17,16 @@ start:
 	sw a2,0(a0)
 	sw a5,0(a0)
 
+	/* execute some insns for "make timing" */
+	lui a0,0
+	auipc a0,0
+	slli a0,a0,0
+	slli a0,a0,31
+	addi a1,zero,0
+	sll a0,a0,a1
+	addi a1,zero,31
+	sll a0,a0,a1
+
 	/* set stack pointer */
 	lui sp,(64*1024)>>12
 
diff --git a/dhrystone/testbench.v b/dhrystone/testbench.v
index c14779e..bfa9fbc 100644
--- a/dhrystone/testbench.v
+++ b/dhrystone/testbench.v
@@ -43,11 +43,12 @@ module testbench;
 	assign mem_ready = 1;
 
 	always @(posedge clk) begin
-		mem_rdata <= mem_la_read ? memory[mem_la_addr >> 2] : 'bx;
+		if (mem_la_read)
+			mem_rdata <= memory[mem_la_addr >> 2];
 		if (mem_valid) begin
 			case (mem_addr)
 				32'h1000_0000: begin
-`ifndef INSN_TIMING
+`ifndef TIMING
 					$write("%c", mem_wdata);
 					$fflush();
 `endif
@@ -75,14 +76,12 @@ module testbench;
 		end
 	end
 
-`ifdef INSN_TIMING
+`ifdef TIMING
 	initial begin
 		repeat (100000) @(posedge clk);
 		$finish;
 	end
 	always @(uut.count_instr[0]) begin
-		//  iverilog -DINSN_TIMING testbench.v ../picorv32.v && ./a.out > x
-		//  sed 's,.*## ,,' x | gawk 'x != "" {print x,$2-y;} {x=$1;y=$2;}' | sort | uniq -c | sort -k3 -n
 		$display("## %-s %d", uut.instruction, uut.count_cycle);
 	end
 `endif