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| author | Tom Verbeure <tom_verbeure@yahoo.com> | 2016-09-03 08:30:16 -0700 |
|---|---|---|
| committer | Tom Verbeure <tom_verbeure@yahoo.com> | 2016-09-03 08:30:16 -0700 |
| commit | 029b72fecc168d369f5ae94bcce3e760daf0e2fe (patch) | |
| tree | bd6ce313ba4a8583914d8e946accfaf1ebdcda52 /dhrystone | |
| parent | c0d1c551068508afb1670fc3968a3d27d98a043e (diff) | |
| download | picorv32-029b72fecc168d369f5ae94bcce3e760daf0e2fe.tar.gz picorv32-029b72fecc168d369f5ae94bcce3e760daf0e2fe.zip | |
Fix tabs
Diffstat (limited to 'dhrystone')
| -rw-r--r-- | dhrystone/testbench_slow_mem.v | 58 |
1 files changed, 29 insertions, 29 deletions
diff --git a/dhrystone/testbench_slow_mem.v b/dhrystone/testbench_slow_mem.v index e4a4dfa..857d06f 100644 --- a/dhrystone/testbench_slow_mem.v +++ b/dhrystone/testbench_slow_mem.v @@ -13,7 +13,7 @@ module testbench; end wire mem_valid; - reg mem_valid_q; + reg mem_valid_q; wire mem_instr; reg mem_ready; wire [31:0] mem_addr; @@ -49,43 +49,43 @@ module testbench; initial $readmemh("dhry.hex", memory); always @(posedge clk) begin - mem_ready <= 1'b0; + mem_ready <= 1'b0; - mem_rdata[ 7: 0] <= 'bx; - mem_rdata[15: 8] <= 'bx; - mem_rdata[23:16] <= 'bx; - mem_rdata[31:24] <= 'bx; + mem_rdata[ 7: 0] <= 'bx; + mem_rdata[15: 8] <= 'bx; + mem_rdata[23:16] <= 'bx; + mem_rdata[31:24] <= 'bx; if (mem_valid & !mem_valid_q) begin - if (|mem_wstrb) begin - mem_ready <= 1'b1; + if (|mem_wstrb) begin + mem_ready <= 1'b1; - case (mem_addr) - 32'h1000_0000: begin + case (mem_addr) + 32'h1000_0000: begin `ifndef TIMING - $write("%c", mem_wdata); - $fflush(); + $write("%c", mem_wdata); + $fflush(); `endif - end - default: begin - if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0]; - if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8]; - if (mem_wstrb[2]) memory[mem_addr + 2] <= mem_wdata[23:16]; - if (mem_wstrb[3]) memory[mem_addr + 3] <= mem_wdata[31:24]; - end - endcase - end - else begin - mem_ready <= 1'b1; + end + default: begin + if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0]; + if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8]; + if (mem_wstrb[2]) memory[mem_addr + 2] <= mem_wdata[23:16]; + if (mem_wstrb[3]) memory[mem_addr + 3] <= mem_wdata[31:24]; + end + endcase + end + else begin + mem_ready <= 1'b1; - mem_rdata[ 7: 0] <= memory[mem_addr + 0]; - mem_rdata[15: 8] <= memory[mem_addr + 1]; - mem_rdata[23:16] <= memory[mem_addr + 2]; - mem_rdata[31:24] <= memory[mem_addr + 3]; - end + mem_rdata[ 7: 0] <= memory[mem_addr + 0]; + mem_rdata[15: 8] <= memory[mem_addr + 1]; + mem_rdata[23:16] <= memory[mem_addr + 2]; + mem_rdata[31:24] <= memory[mem_addr + 3]; + end end - mem_valid_q <= mem_valid; + mem_valid_q <= mem_valid; end initial begin |