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| author | Clifford Wolf <clifford@clifford.at> | 2015-06-06 20:40:58 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-06-06 20:50:53 +0200 |
| commit | bc8ffd2ecbd262e001ceb2c010375446fbdc5d3b (patch) | |
| tree | 4c453d650574a933745ffa401b972a243c65dda7 /dhrystone | |
| parent | 9df9d7ff905d1d6c49221607efc9a04f042ea003 (diff) | |
| download | picorv32-bc8ffd2ecbd262e001ceb2c010375446fbdc5d3b.tar.gz picorv32-bc8ffd2ecbd262e001ceb2c010375446fbdc5d3b.zip | |
Added memory "look-ahead" read interface
Diffstat (limited to 'dhrystone')
| -rw-r--r-- | dhrystone/testbench.v | 28 |
1 files changed, 16 insertions, 12 deletions
diff --git a/dhrystone/testbench.v b/dhrystone/testbench.v index 1e2de3d..216cc87 100644 --- a/dhrystone/testbench.v +++ b/dhrystone/testbench.v @@ -18,28 +18,32 @@ module testbench; wire [31:0] mem_addr; wire [31:0] mem_wdata; wire [3:0] mem_wstrb; - wire [31:0] mem_rdata; + reg [31:0] mem_rdata; + wire mem_la_read; + wire [31:0] mem_la_addr; picorv32 uut ( - .clk (clk ), - .resetn (resetn ), - .trap (trap ), - .mem_valid(mem_valid), - .mem_instr(mem_instr), - .mem_ready(mem_ready), - .mem_addr (mem_addr ), - .mem_wdata(mem_wdata), - .mem_wstrb(mem_wstrb), - .mem_rdata(mem_rdata) + .clk (clk ), + .resetn (resetn ), + .trap (trap ), + .mem_valid (mem_valid ), + .mem_instr (mem_instr ), + .mem_ready (mem_ready ), + .mem_addr (mem_addr ), + .mem_wdata (mem_wdata ), + .mem_wstrb (mem_wstrb ), + .mem_rdata (mem_rdata ), + .mem_la_read(mem_la_read), + .mem_la_addr(mem_la_addr) ); reg [31:0] memory [0:64*1024/4-1]; initial $readmemh("dhry.hex", memory); assign mem_ready = 1; - assign mem_rdata = memory[mem_addr >> 2]; always @(posedge clk) begin + mem_rdata <= memory[mem_la_addr >> 2]; if (mem_valid) begin case (mem_addr) 32'h1000_0000: begin |