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| author | Clifford Wolf <clifford@clifford.at> | 2017-05-13 12:28:54 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-05-13 12:28:54 +0200 |
| commit | 436544ccab9dcef61d074feda19e52c94fdb5c1b (patch) | |
| tree | 8e746bcc4d0164dcf01cc549a620a4d73d63b754 /picorv32.v | |
| parent | cd30db3425a08261f749523dff1f60f396143e37 (diff) | |
| download | picorv32-436544ccab9dcef61d074feda19e52c94fdb5c1b.tar.gz picorv32-436544ccab9dcef61d074feda19e52c94fdb5c1b.zip | |
Fix decoding of C.ADDI instruction
See https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/mr3H6S6IIts
for discussion. There was a bug in the ISA manual.
Diffstat (limited to 'picorv32.v')
| -rw-r--r-- | picorv32.v | 8 |
1 files changed, 3 insertions, 5 deletions
@@ -890,11 +890,9 @@ module picorv32 #( 2'b01: begin // Quadrant 1 case (mem_rdata_latched[15:13]) 3'b000: begin // C.NOP / C.ADDI - if (!mem_rdata_latched[12:2] || mem_rdata_latched[11:7]) begin - is_alu_reg_imm <= 1; - decoded_rd <= mem_rdata_latched[11:7]; - decoded_rs1 <= mem_rdata_latched[11:7]; - end + is_alu_reg_imm <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[11:7]; end 3'b001: begin // C.JAL instr_jal <= 1; |