picorv32 - Fork of https://github.com/YosysHQ/picorv32.

	Commit message (Expand)	Author	Age	Files	Lines
*	Fix copyright info	Claire Xenia Wolf	2021-12-02	1	-1/+1
*	- fix missing brackets	Robert Korn	2020-03-30	1	-1/+1
*	- fix missed timer interrupts,	Robert Korn	2020-03-27	1	-6/+7
*	Disable verilator warnings, fixes #128	Clifford Wolf	2019-08-06	1	-0/+5
*	Add PICORV32_TESTBUG_nnn ifdefs for testing purposes	Clifford Wolf	2019-06-30	1	-0/+18
*	Add rvfi_ixl	Clifford Wolf	2019-06-26	1	-0/+2
*	Add RVFI CSRs	Clifford Wolf	2019-06-07	1	-0/+39
*	Rename decoded_imm_uj to decoded_imm_jv1.0	Clifford Wolf	2019-03-02	1	-6/+6
*	Add rvfi_mode (set to constant 3 = M-mode)	Clifford Wolf	2018-08-31	1	-0/+2
*	Update riscv-formal altops bitmasks	Clifford Wolf	2017-10-07	1	-8/+8
*	Fix bug in picorv32_pcpi_div, Add RISCV_FORMAL_ALTOPS support	Clifford Wolf	2017-10-06	1	-2/+23
*	Add PICORV32_REGS mechanism for ASIC sram instantiation	Clifford Wolf	2017-10-01	1	-1/+67
*	Silenced some warnings when ENABLE_MUL but not ENABLE_PCPI	Clifford Wolf	2017-09-22	1	-2/+2
*	Add correct interupt handling in RVFI trace	Clifford Wolf	2017-09-13	1	-16/+49
*	Add rvfi_halt and rvfi_intr to picorv32_axi and picorv32_wb	Clifford Wolf	2017-09-13	1	-0/+8
*	Revert "Fix RISCV_FORMAL_BLACKBOX_REGS (broke liveness on branch ops)"	Clifford Wolf	2017-09-13	1	-10/+10
*	Fix RISCV_FORMAL_BLACKBOX_REGS (broke liveness on branch ops)	Clifford Wolf	2017-09-12	1	-10/+10
*	Update rvfi_order according to current rvfi spec	Clifford Wolf	2017-09-05	1	-4/+4
*	Suppress writes to cpuregs[0] to prevent confusion	Clifford Wolf	2017-07-14	1	-2/+2
*	Remove some trailing whitespace	Larry Doolittle	2017-06-13	1	-1/+1
*	Add rvfi_halt and rvfi_intr ports	Clifford Wolf	2017-06-06	1	-0/+4
*	Add RVFI to AXI and WB wrappers modules, Add RVFI monitor support to test bench	Clifford Wolf	2017-05-27	1	-0/+80
*	Fixed jalr, c_jalr, and c_jr insns (bug discovered by riscv-formal)	Clifford Wolf	2017-05-18	1	-2/+2
*	Fix decoding of C.ADDI instruction	Clifford Wolf	2017-05-13	1	-5/+3
*	Add riscv-formal alu/regs blackboxing	Clifford Wolf	2017-05-11	1	-0/+14
*	Fix decoding of illegal/reserved opcodes as other valid opcodes	Clifford Wolf	2017-05-07	1	-21/+29
*	testbench_wb.v: unify verbose output with axi testbench	Antony Pavlov	2017-04-06	1	-2/+3
*	Fix indenting in wishbone code	Clifford Wolf	2017-03-14	1	-53/+46
*	WIP: add WISHBONE interconnect support	Antony Pavlov	2017-03-14	1	-0/+202
*	Fix in rvfi_mem_ handling (when compressed isa is enabled)	Clifford Wolf	2017-02-27	1	-13/+12
*	Add DEBUGNETS debug flag	Clifford Wolf	2017-02-26	1	-1/+6
*	Fix verilog code for modelsim	Clifford Wolf	2017-02-17	1	-1/+7
*	Fix "mem_xfer is used before its declaration" warning	Clifford Wolf	2017-02-11	1	-1/+2
*	Rename RVFI ports	Clifford Wolf	2017-01-27	1	-22/+22
*	Fix picorv32_axi STACKADDR default value	Clifford Wolf	2017-01-15	1	-1/+1
*	Add STACKADDR parameter to picorv32_axi module	Oguz Meteer	2017-01-15	1	-2/+4
*	Added rvfi_mem interface	Clifford Wolf	2016-12-20	1	-4/+28
*	Fixed some linter warnings in picorv32.v	Clifford Wolf	2016-12-15	1	-14/+14
*	Added rvfi_post_trap	Clifford Wolf	2016-12-13	1	-1/+3
*	Fixed catching jumps to misaligned insn	Clifford Wolf	2016-11-29	1	-7/+9
*	Renamed rvfi_opcode to rvfi_insn	Clifford Wolf	2016-11-28	1	-2/+2
*	More RVFI bugfixes	Clifford Wolf	2016-11-27	1	-7/+18
*	Minor RVFI bugfix	Clifford Wolf	2016-11-24	1	-1/+1
*	Added RISC-V Formal Interfcae (RVFI)	Clifford Wolf	2016-11-23	1	-0/+74
*	Another bugfix regarding compressed ISA and unaligned insns	Clifford Wolf	2016-11-18	1	-2/+2
*	Fixed the nontrivial compressed ISA bug found by tracecmp2	Clifford Wolf	2016-09-16	1	-3/+15
*	More fixes related to assertpmux checks	Clifford Wolf	2016-09-13	1	-2/+9
*	Added more asserts for the memory interface	Clifford Wolf	2016-09-13	1	-2/+35
*	Merge pull request #21 from wallclimber21/mem_wdata	Clifford Wolf	2016-09-08	1	-1/+3
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\| *	Fix tabs	Tom Verbeure	2016-09-07	1	-2/+2