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author | Clifford Wolf <clifford@clifford.at> | 2017-10-06 17:33:44 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2017-10-06 17:33:44 +0200 |
commit | 7b6aa21f344c0482cb3f88b44bb47230bbf23882 (patch) | |
tree | b672ee903e467e7b0384c9bc5b1fb4da29ce9d71 /picorv32.v | |
parent | ad08edd2e54494e4894c4534cf5f125ac61ba46e (diff) | |
download | picorv32-7b6aa21f344c0482cb3f88b44bb47230bbf23882.tar.gz picorv32-7b6aa21f344c0482cb3f88b44bb47230bbf23882.zip |
Fix bug in picorv32_pcpi_div, Add RISCV_FORMAL_ALTOPS support
Diffstat (limited to 'picorv32.v')
-rw-r--r-- | picorv32.v | 25 |
1 files changed, 23 insertions, 2 deletions
@@ -2329,7 +2329,15 @@ module picorv32_pcpi_fast_mul #( assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1]; assign pcpi_wait = 0; assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1]; +`ifdef RISCV_FORMAL_ALTOPS + assign pcpi_rd = + instr_mul ? (pcpi_rs1 + pcpi_rs2) ^ 32'h4d554c01 : + instr_mulh ? (pcpi_rs1 + pcpi_rs2) ^ 32'h4d554c02 : + instr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32'h4d554c03 : + instr_mulhu ? (pcpi_rs1 + pcpi_rs2) ^ 32'h4d554c04 : 1'bx; +`else assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd); +`endif endmodule @@ -2370,8 +2378,8 @@ module picorv32_pcpi_div ( endcase end - pcpi_wait <= instr_any_div_rem; - pcpi_wait_q <= pcpi_wait; + pcpi_wait <= instr_any_div_rem && resetn; + pcpi_wait_q <= pcpi_wait && resetn; end reg [31:0] dividend; @@ -2401,17 +2409,30 @@ module picorv32_pcpi_div ( running <= 0; pcpi_ready <= 1; pcpi_wr <= 1; +`ifdef RISCV_FORMAL_ALTOPS + case (1) + instr_div: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h44495601; + instr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h44495602; + instr_rem: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h52454D01; + instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h52454D02; + endcase +`else if (instr_div || instr_divu) pcpi_rd <= outsign ? -quotient : quotient; else pcpi_rd <= outsign ? -dividend : dividend; +`endif end else begin if (divisor <= dividend) begin dividend <= dividend - divisor; quotient <= quotient | quotient_msk; end divisor <= divisor >> 1; +`ifdef RISCV_FORMAL_ALTOPS + quotient_msk <= quotient_msk >> 5; +`else quotient_msk <= quotient_msk >> 1; +`endif end end endmodule |