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| author | Clifford Wolf <clifford@clifford.at> | 2016-11-29 18:30:11 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-11-29 18:36:05 +0100 |
| commit | 54a8e4b311e207fa1d07226627dbf9dea6c13836 (patch) | |
| tree | 0d7fd7e986b5f7f66d1e0de0878206f41f4e7a89 /picorv32.v | |
| parent | 17c7da49f48a68cd4197e4580ec0b2954d510b6c (diff) | |
| download | picorv32-54a8e4b311e207fa1d07226627dbf9dea6c13836.tar.gz picorv32-54a8e4b311e207fa1d07226627dbf9dea6c13836.zip | |
Fixed catching jumps to misaligned insn
Diffstat (limited to 'picorv32.v')
| -rw-r--r-- | picorv32.v | 16 |
1 files changed, 9 insertions, 7 deletions
@@ -1564,7 +1564,7 @@ module picorv32 #( latched_branch <= 1; latched_store <= 1; `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) - reg_out <= cpuregs_rs1; + reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1; dbg_rs1val <= cpuregs_rs1; dbg_rs1val_valid <= 1; cpu_state <= cpu_state_fetch; @@ -1849,12 +1849,14 @@ module picorv32 #( irq_pending <= next_irq_pending & ~MASKED_IRQ; - if (COMPRESSED_ISA) begin - reg_pc[0] <= 0; - reg_next_pc[0] <= 0; - end else begin - reg_pc[1:0] <= 0; - reg_next_pc[1:0] <= 0; + if (!CATCH_MISALIGN) begin + if (COMPRESSED_ISA) begin + reg_pc[0] <= 0; + reg_next_pc[0] <= 0; + end else begin + reg_pc[1:0] <= 0; + reg_next_pc[1:0] <= 0; + end end current_pc = 'bx; end |