| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix copyright info | Claire Xenia Wolf | 2021-12-02 | 1 | -1/+1 |
| | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | ||||
| * | - fix missing brackets | Robert Korn | 2020-03-30 | 1 | -1/+1 |
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| * | - fix missed timer interrupts, | Robert Korn | 2020-03-27 | 1 | -6/+7 |
| | | | | | when another interrupt activates shortly before | ||||
| * | Disable verilator warnings, fixes #128 | Clifford Wolf | 2019-08-06 | 1 | -0/+5 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add PICORV32_TESTBUG_nnn ifdefs for testing purposes | Clifford Wolf | 2019-06-30 | 1 | -0/+18 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add rvfi_ixl | Clifford Wolf | 2019-06-26 | 1 | -0/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add RVFI CSRs | Clifford Wolf | 2019-06-07 | 1 | -0/+39 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Rename decoded_imm_uj to decoded_imm_jv1.0 | Clifford Wolf | 2019-03-02 | 1 | -6/+6 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add rvfi_mode (set to constant 3 = M-mode) | Clifford Wolf | 2018-08-31 | 1 | -0/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Update riscv-formal altops bitmasks | Clifford Wolf | 2017-10-07 | 1 | -8/+8 |
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| * | Fix bug in picorv32_pcpi_div, Add RISCV_FORMAL_ALTOPS support | Clifford Wolf | 2017-10-06 | 1 | -2/+23 |
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| * | Add PICORV32_REGS mechanism for ASIC sram instantiation | Clifford Wolf | 2017-10-01 | 1 | -1/+67 |
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| * | Silenced some warnings when ENABLE_MUL but not ENABLE_PCPI | Clifford Wolf | 2017-09-22 | 1 | -2/+2 |
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| * | Add correct interupt handling in RVFI trace | Clifford Wolf | 2017-09-13 | 1 | -16/+49 |
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| * | Add rvfi_halt and rvfi_intr to picorv32_axi and picorv32_wb | Clifford Wolf | 2017-09-13 | 1 | -0/+8 |
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| * | Revert "Fix RISCV_FORMAL_BLACKBOX_REGS (broke liveness on branch ops)" | Clifford Wolf | 2017-09-13 | 1 | -10/+10 |
| | | | | | This reverts commit 624bc05f989e3fdb3ca499d71a1705d0aac569c5. | ||||
| * | Fix RISCV_FORMAL_BLACKBOX_REGS (broke liveness on branch ops) | Clifford Wolf | 2017-09-12 | 1 | -10/+10 |
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| * | Update rvfi_order according to current rvfi spec | Clifford Wolf | 2017-09-05 | 1 | -4/+4 |
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| * | Suppress writes to cpuregs[0] to prevent confusion | Clifford Wolf | 2017-07-14 | 1 | -2/+2 |
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| * | Remove some trailing whitespace | Larry Doolittle | 2017-06-13 | 1 | -1/+1 |
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| * | Add rvfi_halt and rvfi_intr ports | Clifford Wolf | 2017-06-06 | 1 | -0/+4 |
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| * | Add RVFI to AXI and WB wrappers modules, Add RVFI monitor support to test bench | Clifford Wolf | 2017-05-27 | 1 | -0/+80 |
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| * | Fixed jalr, c_jalr, and c_jr insns (bug discovered by riscv-formal) | Clifford Wolf | 2017-05-18 | 1 | -2/+2 |
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| * | Fix decoding of C.ADDI instruction | Clifford Wolf | 2017-05-13 | 1 | -5/+3 |
| | | | | | | See https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/mr3H6S6IIts for discussion. There was a bug in the ISA manual. | ||||
| * | Add riscv-formal alu/regs blackboxing | Clifford Wolf | 2017-05-11 | 1 | -0/+14 |
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| * | Fix decoding of illegal/reserved opcodes as other valid opcodes | Clifford Wolf | 2017-05-07 | 1 | -21/+29 |
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| * | testbench_wb.v: unify verbose output with axi testbench | Antony Pavlov | 2017-04-06 | 1 | -2/+3 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unification of testbench output makes it possible to use the diff utility for comparing testbench instruction traces. Alas the testbench and testbench_wb traces are differ because of interrupts, e.g. picorv32$ make testbench_wb.vvp iverilog -o testbench_wb.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench_wb.v picorv32.v chmod -x testbench_wb.vvp picorv32$ make testbench.vvp iverilog -o testbench.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench.v picorv32.v chmod -x testbench.vvp picorv32$ vvp -N testbench_wb.vvp +verbose | head -n 856 > /tmp/testbench_wb.log picorv32$ vvp -N testbench.vvp +verbose | head -n 856 > /tmp/testbench.log picorv32$ diff -u /tmp/testbench.log /tmp/testbench_wb.log --- /tmp/testbench.log 2017-04-06 06:56:06.079804549 +0300 +++ /tmp/testbench_wb.log 2017-04-06 06:55:58.763485130 +0300 @@ -850,7 +850,7 @@ RD: ADDR=000056a0 DATA=00000013 INSN RD: ADDR=000056a4 DATA=fff00113 INSN RD: ADDR=000056a8 DATA=00000013 INSN -RD: ADDR=000056ac DATA=14208463 INSN <--- testbench: no interrupt -RD: ADDR=000056b0 DATA=00120213 INSN -RD: ADDR=000056b4 DATA=00200293 INSN -RD: ADDR=000056b8 DATA=fe5212e3 INSN +RD: ADDR=00000010 DATA=0200a10b INSN <--- testbench_wb: interrupt +RD: ADDR=00000014 DATA=0201218b INSN +RD: ADDR=00000018 DATA=000000b7 INSN +RD: ADDR=0000001c DATA=16008093 INSN Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> | ||||
| * | Fix indenting in wishbone code | Clifford Wolf | 2017-03-14 | 1 | -53/+46 |
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| * | WIP: add WISHBONE interconnect support | Antony Pavlov | 2017-03-14 | 1 | -0/+202 |
| | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> | ||||
| * | Fix in rvfi_mem_ handling (when compressed isa is enabled) | Clifford Wolf | 2017-02-27 | 1 | -13/+12 |
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| * | Add DEBUGNETS debug flag | Clifford Wolf | 2017-02-26 | 1 | -1/+6 |
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| * | Fix verilog code for modelsim | Clifford Wolf | 2017-02-17 | 1 | -1/+7 |
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| * | Fix "mem_xfer is used before its declaration" warning | Clifford Wolf | 2017-02-11 | 1 | -1/+2 |
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| * | Rename RVFI ports | Clifford Wolf | 2017-01-27 | 1 | -22/+22 |
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| * | Fix picorv32_axi STACKADDR default value | Clifford Wolf | 2017-01-15 | 1 | -1/+1 |
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| * | Add STACKADDR parameter to picorv32_axi module | Oguz Meteer | 2017-01-15 | 1 | -2/+4 |
| | | | | | Signed-off-by: Oguz Meteer <info@guztech.nl> | ||||
| * | Added rvfi_mem interface | Clifford Wolf | 2016-12-20 | 1 | -4/+28 |
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| * | Fixed some linter warnings in picorv32.v | Clifford Wolf | 2016-12-15 | 1 | -14/+14 |
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| * | Added rvfi_post_trap | Clifford Wolf | 2016-12-13 | 1 | -1/+3 |
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| * | Fixed catching jumps to misaligned insn | Clifford Wolf | 2016-11-29 | 1 | -7/+9 |
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| * | Renamed rvfi_opcode to rvfi_insn | Clifford Wolf | 2016-11-28 | 1 | -2/+2 |
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| * | More RVFI bugfixes | Clifford Wolf | 2016-11-27 | 1 | -7/+18 |
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| * | Minor RVFI bugfix | Clifford Wolf | 2016-11-24 | 1 | -1/+1 |
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| * | Added RISC-V Formal Interfcae (RVFI) | Clifford Wolf | 2016-11-23 | 1 | -0/+74 |
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| * | Another bugfix regarding compressed ISA and unaligned insns | Clifford Wolf | 2016-11-18 | 1 | -2/+2 |
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| * | Fixed the nontrivial compressed ISA bug found by tracecmp2 | Clifford Wolf | 2016-09-16 | 1 | -3/+15 |
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| * | More fixes related to assertpmux checks | Clifford Wolf | 2016-09-13 | 1 | -2/+9 |
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| * | Added more asserts for the memory interface | Clifford Wolf | 2016-09-13 | 1 | -2/+35 |
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| * | Merge pull request #21 from wallclimber21/mem_wdata | Clifford Wolf | 2016-09-08 | 1 | -1/+3 |
| |\ | | | | | Only clock mem_wdata when necesssary | ||||
| | * | Fix tabs | Tom Verbeure | 2016-09-07 | 1 | -2/+2 |
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